CN105824158A - Array substrate, display device and array substrate manufacturing method - Google Patents
Array substrate, display device and array substrate manufacturing method Download PDFInfo
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- CN105824158A CN105824158A CN201610369998.1A CN201610369998A CN105824158A CN 105824158 A CN105824158 A CN 105824158A CN 201610369998 A CN201610369998 A CN 201610369998A CN 105824158 A CN105824158 A CN 105824158A
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- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 14
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 38
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 15
- 239000010410 layer Substances 0.000 description 84
- 230000005540 biological transmission Effects 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 230000002708 enhancing effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000010412 perfusion Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- Nonlinear Science (AREA)
- Geometry (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses an array substrate, a display device and an array substrate manufacturing method and belongs to the field of displayers. The array substrate comprises a substrate body and an electrode layer arranged on the substrate body. The electrode layer comprises multiple first electrodes and multiple second electrodes. The first electrodes and the second electrodes are arranged on the substrate body alternately at intervals. Any second electrode is higher than any first electrode. The first electrodes and the second electrodes are opposite in polarity. According to the array substrate, the second electrodes in the electrode layer are arranged to be higher than the first electrodes, so that when a horizontal electric field between the second electrodes and the first electrodes inclines, the component in the horizontal direction of the electric field in the middle of the intervals between the second electrodes and the first electrodes is stronger than that of the horizontal electric field; as a result, the angle of deflection of liquid crystals corresponding to the position between every two corresponding electrodes is increased, and then the light transmissivity of the position between every two corresponding electrodes is improved.
Description
Technical field
The present invention relates to field of display, particularly to a kind of array base palte, display device and array substrate manufacturing method.
Background technology
In lcd technology, senior super Wei Chang conversion (AdvancedSuperDimensionSwitch, be called for short ADS) technology is with one of transmitance height, visual angle width, fast response time and the advantage important technology being increasingly becoming field of liquid crystal display such as low in energy consumption.Display floater based on ADS pattern is by electric field produced between gap electrode in gap electrode layer, and the electric field formation multi-dimensional electric field that gap electrode layer produces with plate electrode interlayer, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can produce rotation, thus improve liquid crystal work efficiency and increase light transmission efficiency.
Existing display floater based on ADS pattern includes color membrane substrates, array base palte and both are to the liquid crystal of perfusion after box, wherein, array base palte includes common electrode layer (i.e. plate electrode layer), insulating barrier and the pixel electrode layer (i.e. gap electrode layer) being successively set on underlay substrate.When making alive, liquid crystal is distorted rotation under electric field action, thus reaches to control the purpose of light.
Pixel electrode layer includes multiple anelectrodes and the negative electrode that alternate intervals arranges, anelectrode and the interval region of negative electrode that each two is adjacent form horizontal component of electric field, this horizontal component of electric field is the most on a declining curve in interval region, therefore the horizontal component of electric field in the centre position of this interval region is minimum, liquid crystal deflection angle corresponding to this position is less, the light transmission rate causing this position is crossed less, thus affects the display effect of display floater.
Summary of the invention
The problem too small in order to solve the centre position light transmission rate at the interval of two adjacent electrodes, embodiments provides a kind of array base palte, display device and array substrate manufacturing method.Described technical scheme is as follows:
First aspect, embodiments provide a kind of array base palte, described array base palte includes substrate and arranges electrode layer on the substrate, described electrode layer includes multiple first electrode and multiple second electrode, the plurality of first electrode and the plurality of second electrode alternate intervals are arranged on the substrate, and the height of arbitrary described second electrode is more than the height of arbitrary described first electrode；Described first electrode and the opposite polarity of described second electrode.
In a kind of implementation of the embodiment of the present invention, described substrate includes underlay substrate, the common electrode layer being arranged on described underlay substrate, the insulating barrier that is arranged in described common electrode layer, described electrode layer is arranged on described insulating barrier, and described first electrode and described second electrode are pixel electrode.
In the another kind of implementation of the embodiment of the present invention, described insulating barrier includes: the strip collets that insulating sublayer layer and the multiple parallel interval being arranged on described insulating sublayer layer are arranged；The plurality of first electrode is arranged on described insulating sublayer layer, and the plurality of second electrode is separately positioned on multiple collets, and arranges described second electrode on each described collets.
In the another kind of implementation of the embodiment of the present invention, described second electrode covers on the end face of described collets.
In the another kind of implementation of the embodiment of the present invention, described collets cross section on the length direction being perpendicular to described collets is trapezoidal, and described second electrode covers on the end face and side of described collets.
In the another kind of implementation of the embodiment of the present invention, described collets cross section on the length direction being perpendicular to described collets is isosceles trapezoid.
In the another kind of implementation of the embodiment of the present invention, the base angle of described isosceles trapezoid is 75-85 degree.
In the another kind of implementation of the embodiment of the present invention, a height of 1 micron-3 microns of described isosceles trapezoid.
In the another kind of implementation of the embodiment of the present invention, described collets are resin mass.
In the another kind of implementation of the embodiment of the present invention, described insulating barrier includes the strip boss that multiple parallel interval is arranged, the plurality of first electrode is arranged between multiple boss, the plurality of second electrode is separately positioned on the plurality of boss, and arranges second electrode on each described boss.
Second aspect, the embodiment of the present invention additionally provides a kind of display device, and described display device includes the array base palte described in any one of first aspect.
The third aspect, the embodiment of the present invention additionally provides a kind of array substrate manufacturing method, and described method includes:
Make substrate；
Substrate is formed electrode layer, described electrode layer includes multiple first electrode and multiple second electrode, the plurality of first electrode and the plurality of second electrode alternate intervals are arranged on the substrate, and the height of arbitrary described second electrode is more than the height of arbitrary described first electrode；Described first electrode and the opposite polarity of described second electrode.
In a kind of implementation of the embodiment of the present invention, described making substrate, including:
Underlay substrate makes common electrode layer；
Making insulating barrier in described common electrode layer, described electrode layer is arranged on described insulating barrier, and described first electrode and described second electrode are pixel electrode.
In the another kind of implementation of the embodiment of the present invention, described insulating barrier includes: the strip collets that described insulating sublayer layer and multiple parallel interval of being arranged on described insulating sublayer layer are arranged, and described makees insulating barrier in described common electrode layer, including:
Described common electrode layer makes insulating sublayer layer；
Described insulating sublayer layer makes multiple collets；
The plurality of first electrode is arranged on described insulating sublayer layer, and the plurality of second electrode is separately positioned on the plurality of collets, and arranges described second electrode on each described collets.
In the another kind of implementation of the embodiment of the present invention, described make insulating barrier in described common electrode layer, including:
Depositing insulating layer in described common electrode layer；
On described insulating barrier, the strip boss that multiple parallel interval is arranged is formed by patterning processes, the plurality of first electrode is arranged between multiple boss, the plurality of second electrode is separately positioned on the plurality of boss, and arranges second electrode on each described boss.
The technical scheme that the embodiment of the present invention provides has the benefit that
In the present invention, by the second electrode in electrode layer is arranged to higher than the first electrode, so that the second electrode and the first interelectrode horizontal component of electric field run-off the straight, after inclination, the component in the middle position electric field level direction of the interval region of the second electrode and the first electrode becomes strong for horizontal component of electric field, make the liquid crystal deflection angle increase that two electrode centre positions are corresponding, thus improve two electrode centre position light transmission rates.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, in describing embodiment below, the required accompanying drawing used is briefly described, apparently, accompanying drawing in describing below is only some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of a kind of array base palte that the embodiment of the present invention provides；
Fig. 2 is the structural representation of the another kind of array base palte that the embodiment of the present invention provides；
Fig. 3 is the transmitance schematic diagram of existing array base-plate structure；
Fig. 4 is the transmitance schematic diagram of array base-plate structure shown in Fig. 2；
Fig. 5 is the structural representation of the another kind of array base palte that the embodiment of the present invention provides；
Fig. 6 is the structural representation of the another kind of array base palte that the embodiment of the present invention provides；
Fig. 7 is the structural representation of the another kind of array base palte that the embodiment of the present invention provides；
Fig. 8 is the flow chart of a kind of array substrate manufacturing method that the embodiment of the present invention provides；
Fig. 9 is the flow chart of the another kind of array substrate manufacturing method that the embodiment of the present invention provides；
Figure 10 is the structural representation in the array base palte manufacturing process that the embodiment of the present invention provides；
Figure 11 is the structural representation in the array base palte manufacturing process that the embodiment of the present invention provides；
Figure 12 is the structural representation in the array base palte manufacturing process that the embodiment of the present invention provides；
Figure 13 is the structural representation in the array base palte manufacturing process that the embodiment of the present invention provides；
Figure 14 is the flow chart of the another kind of array substrate manufacturing method that the embodiment of the present invention provides；
Figure 15 is the structural representation in the array base palte manufacturing process that the embodiment of the present invention provides；
Figure 16 is the structural representation in the array base palte manufacturing process that the embodiment of the present invention provides；
Figure 17 is the structural representation in the array base palte manufacturing process that the embodiment of the present invention provides.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
Fig. 1 is the structural representation of a kind of array base palte that the embodiment of the present invention provides, see Fig. 1, array base palte includes substrate 100 and arranges electrode layer 200 on the substrate 100, electrode layer 200 includes multiple first electrode 201 and multiple second electrode 202, multiple first electrodes 201 and multiple second electrode 202 alternate intervals are arranged on the substrate 100, and the height of arbitrary second electrode 202 is more than the height of arbitrary first electrode 201；First electrode 201 and the opposite polarity of the second electrode 202.
Wherein, the height of the second electrode 202 is the end face distance to substrate 100 of the second electrode 202, and the height of the first electrode 201 is the end face distance to substrate 100 of the first electrode 201.Or, the height of the second electrode 202 is the end face distance to the bottom surface of the second electrode 202 of the second electrode 202, and the height of the first electrode 201 is the end face distance to the bottom surface of the first electrode 201 of the first electrode 201.The end face of the first electrode 201 and the second electrode 202 is the one side away from substrate 100, and the bottom surface of the first electrode 201 and the second electrode 202 is the one side near substrate 100.
In the present invention, by the second electrode in electrode layer is arranged to higher than the first electrode, so that the second electrode and the first interelectrode horizontal component of electric field run-off the straight, after inclination, the component in the middle position electric field level direction of the interval region of the second electrode and the first electrode becomes strong for horizontal component of electric field, make the liquid crystal deflection angle increase that two electrode centre positions are corresponding, thus improve two electrode centre position light transmission rates.
The above-mentioned array base palte that the present embodiment provides is applicable to ADS type display panels, and when the array base palte that this array base palte is ADS type display panels, the first electrode 201 and the second electrode 202 are pixel electrode.
When implementing, the height height more than the first electrode 201 of the second electrode 202, the array base palte provided referring specifically to hereinafter Fig. 2～Fig. 7 can be made by design supporter (can be specifically boss hereinafter or collets).
When implementing, it is also possible to by increasing the thickness (thickness of the second electrode 202 is more than the thickness of the first electrode 201) of the second electrode 202 so that the height of the second electrode 202 is more than the height of the first electrode 201.
In addition, the above-mentioned array base palte that the present embodiment provides can be applicable to other kinds of display floater, such as plane conversion (In-PlaneSwitching, it is called for short IPS) type display panels, when the array base palte that this array base palte is IPS type display panels, first electrode 201 is pixel electrode, and the second electrode 202 is public electrode；Or, the first electrode 201 is public electrode, and the second electrode 202 is pixel electrode.
When implementing, equally use the mode of the thickness of design supporter or increase the second electrode so that the height of the second electrode 202, more than the height of the first electrode 201, repeats no more here.
Fig. 2 is the structural representation of a kind of array base palte that the embodiment of the present invention provides, see Fig. 2, array base palte includes underlay substrate 101, the common electrode layer 102 being arranged on underlay substrate 101, the insulating barrier 103 being arranged in common electrode layer 102, the pixel electrode layer 200 being arranged on insulating barrier 103, pixel electrode layer 200 includes multiple first pixel electrode 201 (namely aforementioned first electrode) and multiple second pixel electrode 202 (namely aforementioned second electrode), multiple first pixel electrodes 201 and multiple second pixel electrode 202 alternate intervals are arranged on insulating barrier 103, and the height of arbitrary second pixel electrode 202 is more than the height of arbitrary first pixel electrode 201；First pixel electrode 201 and the opposite polarity of the second pixel electrode 202.
In the present invention, by the second pixel electrode 202 in pixel electrode layer 200 is arranged to higher than the first pixel electrode 201, so that the horizontal component of electric field run-off the straight between the second pixel electrode 202 and the first pixel electrode 201, after inclination, the component in the middle position electric field level direction of the interval region of the second pixel electrode 202 and the first pixel electrode 201 becomes strong for horizontal component of electric field, make the liquid crystal deflection angle increase that two pixel electrode centre positions are corresponding, thus improve two pixel electrode centre position light transmission rates.
Fig. 3 show the transmitance schematic diagram of existing array base-plate structure (the first pixel electrode and the second pixel electrode are arranged on same level), and in figure, position shown in A is the centre position of the interval region of two pixel electrodes.Fig. 4 show the transmitance schematic diagram of array base-plate structure in Fig. 2.According to Fig. 3 and Fig. 4 it can be seen that array base-plate structure shown in employing Fig. 2 can improve the transmitance in the centre position of the interval region of two pixel electrodes.
In array base palte as shown in Figure 2, above-mentioned insulating barrier 103 is structure as a whole, multiple boss 103A it is formed with on insulating barrier 103, the plurality of first electrode is arranged between the plurality of boss, multiple second pixel electrodes 202 are separately positioned on multiple boss 103A, and on each boss 103A, second pixel electrode 202 is set, as shown in Figure 2.
Wherein, multiple boss 103A can be the strip boss that multiple parallel interval is arranged.In the embodiment of the present invention, be arrangeding in parallel refers to the length direction of strip boss and be arranged in parallel or width be arranged in parallel.
In the present embodiment, underlay substrate 101 can be glass substrate, and common electrode layer 102 and pixel electrode layer 200 can be tin indium oxide (IndiumTinOxides is called for short ITO) thin layer.Insulating barrier 103 can be silicon nitride or silicon oxynitride layer.
Fig. 5 is the structural representation of the another kind of array base palte that the embodiment of the present invention provides, see Fig. 5, this array base palte is with the difference of the array base palte shown in Fig. 2, and insulating barrier 103 includes: insulating sublayer layer 1031 and the multiple collets 1032 being arranged on insulating sublayer layer 1031.
Multiple first pixel electrodes 201 are arranged on insulating sublayer layer 1031, and multiple second pixel electrodes 202 are separately positioned on multiple collets 1032, and arrange second pixel electrode 202 on each collets 1032.In this implementation, by being arranged on collets 1032 by the second pixel electrode 202, thus raise the height of the second pixel electrode 202 so that horizontal component of electric field run-off the straight.
Wherein, multiple collets 1032 can be the strip collets that multiple parallel interval is arranged.In the embodiment of the present invention, be arrangeding in parallel refers to the length direction of strip collets and be arranged in parallel or width be arranged in parallel.
In the another kind of implementation of the embodiment of the present invention, the second pixel electrode 202 covers on the end face of collets 1032.This set both can guarantee that the normal layout of the second pixel electrode 202, is unlikely to again, so that collets 1032 occupied area is excessive, to affect the setting of adjacent pixel electrodes.
In embodiments of the present invention, insulating sublayer layer 1031 can be silicon nitride or silicon oxynitride layer.Collets 1032 can be resin mass.Use resin material, not only good insulation preformance, and light transmission is good.The most in other embodiments, collets 1032 can also use other insulant to make, such as silicon nitride, silicon oxynitride etc..
Fig. 6 is the structural representation of the another kind of array base palte that the embodiment of the present invention provides, see Fig. 6, this array base palte is with the difference of the array base palte of Fig. 2: boss 103A cross section on the length direction being perpendicular to boss 103A is trapezoidal, second pixel electrode 202 covers on trapezoidal end face and side, this mode can improve the horizontal component of electric field intensity in the centre position between two pixel electrodes further, thus further increases the transmitance in the centre position between two pixel electrodes.
Further, boss 103A cross section on the length direction being perpendicular to boss 103A is isosceles trapezoid.
Specifically, the base angle of isosceles trapezoid can be 75-85 degree, and this angle arranges and is obtained in that preferable horizontal component of electric field intensity enhancing effect.
Specifically, the height of isosceles trapezoid can be 1 micron-3 microns.The most too small, it is impossible to make the component in two pixel electrode middle position electric field level directions obtain enough enhancings；The most excessive, array base palte can be caused blocked up.
Fig. 7 is the structural representation of the another kind of array base palte that the embodiment of the present invention provides, see Fig. 7, this array base palte is with the difference of the array base palte of Fig. 5: the collets 1032 cross section on the length direction being perpendicular to collets 1032 is trapezoidal, and the second pixel electrode 202 covers on trapezoidal end face and side.
Further, the collets 1032 cross section on the length direction being perpendicular to collets 1032 is isosceles trapezoid.
Specifically, the base angle of isosceles trapezoid can be 75-85 degree.
Specifically, the height of isosceles trapezoid can be 1 micron-3 microns.The height of isosceles trapezoid is too small, it is impossible to make the component in two pixel electrode middle position electric field level directions obtain enough enhancings；The most excessive, array base palte can be caused blocked up.
In embodiments of the present invention, collets 1032 can be resin mass.Use resin material, not only good insulation preformance, and light transmission is good.The most in other embodiments, collets 1032 can also use other insulant to make, such as silicon nitride, silicon oxynitride etc..
The embodiment of the present invention additionally provides a kind of display device, and this display device includes the array base palte that Fig. 1～Fig. 7 provides.
In the specific implementation, the display device that the embodiment of the present invention provides can be any product with display function or the parts such as mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
In the present invention, by the second electrode in electrode layer is arranged to higher than the first electrode, so that the second electrode and the first interelectrode horizontal component of electric field run-off the straight, after inclination, the component in the middle position electric field level direction of the interval region of the second electrode and the first electrode becomes strong for horizontal component of electric field, make the liquid crystal deflection angle increase that two electrode centre positions are corresponding, thus improve two electrode centre position light transmission rates.
Fig. 8 is the flow chart of a kind of array substrate manufacturing method that the embodiment of the present invention also provides for, and sees Fig. 8, and method includes:
Step 301: make substrate.
Step 302: forming electrode layer on substrate, electrode layer includes that multiple first electrode and multiple second electrode, multiple first electrodes and multiple second electrode alternate intervals are arranged on substrate, and the height of arbitrary second electrode is more than the height of arbitrary first electrode；First electrode and the opposite polarity of the second electrode.
The above-mentioned array substrate manufacturing method that the present embodiment provides is applicable to the array base palte of ADS type display panels and makes, when this array substrate manufacturing method is for making the array base palte of ADS type display panels, above-mentioned first electrode and the second electrode are pixel electrode.
When implementing, the height height more than the first electrode of the second electrode, the array substrate manufacturing method provided referring specifically to hereinafter Fig. 9～Figure 10 can be made by design supporter (can be specifically boss hereinafter or collets).
When implementing, it is also possible to by increasing the thickness (thickness of the second electrode is more than the thickness of the first electrode) of the second electrode so that the height of the second electrode is more than the height of the first electrode.
In addition, the above-mentioned array substrate manufacturing method that the present embodiment provides can be applicable to the array base palte of other kinds of display floater and makes, such as plane conversion (In-PlaneSwitching, it is called for short IPS) type display panels, when this array substrate manufacturing method is for making the array base palte of IPS type display panels, above-mentioned first electrode is pixel electrode, and the second electrode is public electrode；Or, the first electrode is public electrode, and the second electrode is pixel electrode.
When implementing, equally use the mode of the thickness of design supporter or increase the second electrode so that the height of the second electrode, more than the height of the first electrode, repeats no more here.
In the present invention, by the second electrode in electrode layer is arranged to higher than the first electrode, so that the second electrode and the first interelectrode horizontal component of electric field run-off the straight, after inclination, the component in the middle position electric field level direction of the interval region of the second electrode and the first electrode becomes strong for horizontal component of electric field, make the liquid crystal deflection angle increase that two electrode centre positions are corresponding, thus improve two electrode centre position light transmission rates.
Fig. 9 is the flow chart of the another kind of array substrate manufacturing method that the embodiment of the present invention also provides for, and sees Fig. 9, and method includes:
Step 401: make common electrode layer on underlay substrate.
As shown in Figure 10, underlay substrate 101 makes common electrode layer 102.
Wherein, underlay substrate can be glass substrate, and common electrode layer can be ito thin film layer.
Step 402: make insulating sublayer layer in common electrode layer.
As shown in figure 11, common electrode layer 102 makes insulating sublayer layer 1031.
Wherein, insulating sublayer layer can be silicon nitride or silicon oxynitride layer.
Step 403: make the strip collets that multiple parallel interval is arranged on insulating sublayer layer.
As shown in Figure 12 or Figure 11, insulating sublayer layer 1031 makes multiple collets 1032.
Wherein, collets can be resin mass.Use resin material, not only good insulation preformance, and light transmission is good.The most in other embodiments, collets can also use other insulant to make, such as silicon nitride, silicon oxynitride etc..
Step 404: make pixel electrode layer on the insulating layer, pixel electrode layer includes multiple first pixel electrode and multiple second pixel electrode, multiple first pixel electrodes and multiple second pixel electrode alternate intervals are arranged on the insulating layer, multiple first pixel electrodes are arranged on insulating sublayer layer, multiple second pixel electrodes are separately positioned on multiple collets, and arrange second pixel electrode on each collets.
As shown in figure 13, in a kind of implementation of the embodiment of the present invention, the collets 1032 cross section on the length direction being perpendicular to collets 1032 is rectangle, and in this implementation, the second pixel electrode 202 covers on the end face of collets 1032, as shown in Figure 5.
As shown in figure 12, in the another kind of implementation of the embodiment of the present invention, the collets 1032 cross section on the length direction being perpendicular to collets 1032 is trapezoidal, in this implementation, second pixel electrode 202 covers on the end face and side of collets 1032, as shown in Figure 7.
Specifically, collets cross section on the length direction being perpendicular to collets is isosceles trapezoid.
Wherein, the base angle of isosceles trapezoid can be 75-85 degree.
Wherein, the height of isosceles trapezoid can be 1 micron-3 microns.The height of isosceles trapezoid is too small, it is impossible to make the component in two pixel electrode middle position electric field level directions obtain enough enhancings；The most excessive, array base palte can be caused blocked up.
In the present embodiment, pixel electrode layer can be ito thin film layer.
In the present invention, by the second pixel electrode in pixel electrode layer is arranged to higher than the first pixel electrode, so that the horizontal component of electric field run-off the straight between the second pixel electrode and the first pixel electrode, after inclination, the component in the middle position electric field level direction of the interval region of the second pixel electrode and the first pixel electrode becomes strong for horizontal component of electric field, make the liquid crystal deflection angle increase that two pixel electrode centre positions are corresponding, thus improve two pixel electrode centre position light transmission rates.
Figure 14 is the flow chart of the another kind of array substrate manufacturing method that the embodiment of the present invention also provides for, and this manufacture method is that from the difference of the method that Fig. 9 provides the step making insulating barrier is different, sees Figure 14, and method includes:
Step 501: make common electrode layer on underlay substrate.
As shown in Figure 10, underlay substrate 101 makes common electrode layer 102.
Step 502: depositing insulating layer in common electrode layer.
As shown in figure 15, depositing insulating layer 103 in common electrode layer 102.
Step 503: formed the strip boss that multiple parallel interval is arranged by patterning processes on the insulating layer.
As shown in Figure 16 or Figure 15, on insulating barrier 103, form multiple boss 103A by patterning processes.
Step 404: make pixel electrode layer on the insulating layer, pixel electrode layer includes multiple first pixel electrode and multiple second pixel electrode, multiple first pixel electrodes and multiple second pixel electrode alternate intervals are arranged on the insulating layer, and multiple first electrode is arranged between multiple boss, multiple second pixel electrodes are separately positioned on multiple boss, and arrange second pixel electrode on each boss.
As shown in figure 17, in a kind of implementation of the embodiment of the present invention, boss 103A cross section on the length direction being perpendicular to boss 103A is rectangle, and in this implementation, the second pixel electrode 202 covers on the end face of boss 103A, as shown in Figure 2.
As shown in figure 16, in the another kind of implementation of the embodiment of the present invention, boss 103A cross section on the length direction being perpendicular to boss 103A is trapezoidal, in this implementation, second pixel electrode 202 covers on the end face and side of boss 103A, as shown in Figure 6.
Further, boss cross section on the length direction being perpendicular to boss is isosceles trapezoid.
Specifically, the base angle of isosceles trapezoid can be 75-85 degree.
Specifically, the height of isosceles trapezoid can be 1 micron-3 microns.The height of isosceles trapezoid is too small, it is impossible to make the component in two pixel electrode middle position electric field level directions obtain enough enhancings；The most excessive, array base palte can be caused blocked up.
In the present invention, by the second pixel electrode in pixel electrode layer is arranged to higher than the first pixel electrode, so that the horizontal component of electric field run-off the straight between the second pixel electrode and the first pixel electrode, after inclination, the component in the middle position electric field level direction of the interval region of the second pixel electrode and the first pixel electrode becomes strong for horizontal component of electric field, make the liquid crystal deflection angle increase that two pixel electrode centre positions are corresponding, thus improve two pixel electrode centre position light transmission rates.
These are only presently preferred embodiments of the present invention, not in order to limit the present invention, all within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.
Claims (15)
1. an array base palte, it is characterized in that, described array base palte includes substrate and arranges electrode layer on the substrate, described electrode layer includes multiple first electrode and multiple second electrode, the plurality of first electrode and the plurality of second electrode alternate intervals are arranged on the substrate, and the height of arbitrary described second electrode is more than the height of arbitrary described first electrode；Described first electrode and the opposite polarity of described second electrode.
Array base palte the most according to claim 1, it is characterized in that, described substrate includes underlay substrate, the common electrode layer being arranged on described underlay substrate, the insulating barrier that is arranged in described common electrode layer, described electrode layer is arranged on described insulating barrier, and described first electrode and described second electrode are pixel electrode.
Array base palte the most according to claim 2, it is characterised in that described insulating barrier includes: the strip collets that insulating sublayer layer and the multiple parallel interval being arranged on described insulating sublayer layer are arranged；The plurality of first electrode is arranged on described insulating sublayer layer, and the plurality of second electrode is separately positioned on multiple collets, and arranges described second electrode on each described collets.
Array base palte the most according to claim 3, it is characterised in that described second electrode covers on the end face of described collets.
Array base palte the most according to claim 3, it is characterised in that described collets cross section on the length direction being perpendicular to described collets is trapezoidal, described second electrode covers on the end face and side of described collets.
Array base palte the most according to claim 5, it is characterised in that described collets cross section on the length direction being perpendicular to described collets is isosceles trapezoid.
Array base palte the most according to claim 6, it is characterised in that the base angle of described isosceles trapezoid is 75-85 degree.
Array base palte the most according to claim 6, it is characterised in that a height of 1 micron-3 microns of described isosceles trapezoid.
Array base palte the most according to claim 3, it is characterised in that described collets are resin mass.
Array base palte the most according to claim 2, it is characterized in that, described insulating barrier includes the strip boss that multiple parallel interval is arranged, the plurality of first electrode is arranged between multiple boss, the plurality of second electrode is separately positioned on the plurality of boss, and arranges second electrode on each described boss.
11. 1 kinds of display devices, it is characterised in that described display device includes the array base palte described in any one of claim 1 to 10.
12. 1 kinds of array substrate manufacturing methods, it is characterised in that described method includes:
Make substrate；
Substrate is formed electrode layer, described electrode layer includes multiple first electrode and multiple second electrode, the plurality of first electrode and the plurality of second electrode alternate intervals are arranged on the substrate, and the height of arbitrary described second electrode is more than the height of arbitrary described first electrode；Described first electrode and the opposite polarity of described second electrode.
13. methods according to claim 12, it is characterised in that described making substrate, including:
Underlay substrate makes common electrode layer；
Making insulating barrier in described common electrode layer, described electrode layer is arranged on described insulating barrier, and described first electrode and described second electrode are pixel electrode.
14. methods according to claim 13, it is characterised in that described insulating barrier includes: the strip collets that described insulating sublayer layer and multiple parallel interval of being arranged on described insulating sublayer layer are arranged, described make insulating barrier in described common electrode layer, including:
Described common electrode layer makes insulating sublayer layer；
Described insulating sublayer layer makes multiple collets；
The plurality of first electrode is arranged on described insulating sublayer layer, and the plurality of second electrode is separately positioned on the plurality of collets, and arranges described second electrode on each described collets.
15. methods according to claim 13, it is characterised in that described make insulating barrier in described common electrode layer, including:
Depositing insulating layer in described common electrode layer；
On described insulating barrier, the strip boss that multiple parallel interval is arranged is formed by patterning processes, the plurality of first electrode is arranged between multiple boss, the plurality of second electrode is separately positioned on the plurality of boss, and arranges second electrode on each described boss.
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