CN105810606A - Method for positioning failure point at contact hole level of memory circuit - Google Patents
Method for positioning failure point at contact hole level of memory circuit Download PDFInfo
- Publication number
- CN105810606A CN105810606A CN201610242345.7A CN201610242345A CN105810606A CN 105810606 A CN105810606 A CN 105810606A CN 201610242345 A CN201610242345 A CN 201610242345A CN 105810606 A CN105810606 A CN 105810606A
- Authority
- CN
- China
- Prior art keywords
- electrode
- contact hole
- voltage contrast
- hole level
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a method for positioning a failure point at a contact hole level of a memory circuit. Aiming at a machine free of microprobe equipment, a line is firstly repaired by a focus ion beam; an electrode in a suspended state is short connected to a nearby node with a stable potential; and then voltage contrast analysis is carried out. According to the method, the suspended electrode is short connected to the nearby node with the stable potential by the focus ion beam; and charges accumulated on the suspended electrode can be timely guided away when electron beam bombardment is carried out in voltage contrast, so that the suspended electrode is always kept in a stable state; and the interference of the charges during voltage contrast analysis is eliminated.
Description
Technical field
The present invention relates to test of semiconductor integrated circuit field, particularly relate to a kind of for memory circuitry contact hole level failpoint localization method.
Background technology
In ic manufacturing process, due to defective workmanship, equipment error or even the reason such as artificial, it is possible to defect can be caused at chip internal.The defect finding to occur in ic manufacturing process can be monitored in time extremely important for the lifting of yield, owing to the characteristic size of manufacturing process constantly reduces, the position that abnormal short circuit occurs may be more small, when uncertain concrete short circuit position, searching these extremely may be extremely difficult, it is easy to be left in the basket.
Detection method commonly used in the industry at present is with focused ion bundle (FIB:FocusIonBeam) cutting equipment, step-by-step movement propelling, and problem chip doubt region is carried out large area section observation, thus finding the position of abnormal short circuit.Owing to defective locations is uncertain during the operation of this method, purposiveness is not strong, it is necessary to expend resource when substantial amounts of manpower and equipment machine, and effect is but not good.The problem being additionally, since resolution, it is likely that weak short circuit is left in the basket because of carelessness in the process of cutting.Accordingly, it would be desirable to a kind of more efficient voltage contrast method detects these abnormal problems of analysis.Voltage contrast (VC:VoltageContrast) is the contrast formed due to specimen surface current potential difference in SEM.Utilize the signal that sample surfaces potential state is sensitive, such as secondary electron, as the modulation signal of image reproducer, can obtain resolution higher, the obvious voltage contrast picture of comparison of light and shade, as it is shown in figure 1, be a kind of general failure analysis means, at contact hole level, understructure can be differentiated.Can determine whether that whether understructure is normal in conjunction with expected design.
But for memory circuitry, having extremely long row common word line (grid) with the memory element in a line, this wordline is floating state because of it, owing to beam bombardment can produce charging phenomenon in the VC analysis process of contact hole level.With current potential after gate charges, have impact on the on off state of respective devices, thus the contact hole VC result in source, leakage is produced impact, this impact can introduce interference, is an impediment to being accurately positioned of failpoint, as shown in Figure 2:
Passive type voltage contrast, positively biased pattern:
Passive type voltage contrast is used to analyze, under positively biased pattern, contact hole secondary electron yield is more than incident electron, and positive charge accumulates, after the gate charges of floating, NMOS enters opening, becomes a bigger charge storage region after now reverse-biased source drain junction connection.More charge can be accumulated compared to single reverse biased junction and SE yield is more.
For PMOS under positively biased pattern, source drain junction positively biased, surface voltage is subject to clamp, and the SE yield affected by surface potential declines limited.
Due to problem be derived from floating state gate charge accumulation, therefore solution can be change grid annexation, by its by the indeterminate state of floating be changed to can be clear and definite steady statue.The scheme that can adopt is: what have microprobe equipment can apply steady potential to grid.But the ultramicroscope price with microprobe equipment is high, it is difficult to universal, it is therefore desirable to the scheme of the low cost of a kind of simplicity solves this problem.
Summary of the invention
The technical problem to be solved is to provide a kind of memory circuitry contact hole level failure positioning method, by reducing surrounding interference efficiently location failure of removal point.
For solving the problems referred to above, the present invention provides a kind of memory circuitry contact hole level failure positioning method, is for the board without microprobe equipment, uses focused ion Shu Jinhang circuit to repair, there is near being shorted to by the electrode of floating state the node of steady potential, then carry out voltage contrast analysis.
The described node with steady potential, including the trap of earthing potential.
When carrying out voltage contrast and analyzing, the electrode of beam bombardment floating state, the electric charge of electrode accumulation can pass through to be shorted to the node of steady potential, makes electrode remain stable current potential.
The electrode of described floating state, material is polysilicon, or is metal.
Memory circuitry contact hole level failure positioning method of the present invention, for the board without microprobe equipment, when carrying out voltage contrast and analyzing, focused ion Shu Jinhang circuit is used to repair, the electrode of floating is shorted to neighbouring steady potential node, and when voltage contrast carries out beam bombardment, the electric charge of electrode accumulation can be led away in time, make electrode pole remain and stable state eliminate interference when voltage contrast is analyzed by it.
Accompanying drawing explanation
Fig. 1 is that voltage substrate is as schematic diagram.
Fig. 2 is the sectional view of memory circuitry cellular construction.
Fig. 3 is for memory array short circuit floating electrode schematic diagram.
Fig. 4 is that the present invention uses front and back voltage contrast picture contrast schematic diagram.
Fig. 5 is trouble point section view microgram.
Fig. 6 is the inventive method schematic diagram.
Detailed description of the invention
The present invention provides a kind of memory circuitry contact hole level failure positioning method, is for the board without microprobe equipment, uses focused ion Shu Jinhang circuit to repair, has the node of steady potential near being shorted to by floating electrode.Described node includes the trap of earthing potential.When carrying out voltage contrast and analyzing, the electrode of beam bombardment floating state, the electric charge of floating electrode accumulation can pass through to be shorted to the node of steady potential, makes the current potential that floating electrode remains stable for, and is about to " floating " state and changes into the state of " non-floating ".
Specifically, such as memory array as shown in Figure 3, at contact hole level, utilizing focused ion bundle to dig pit, being shorted on the earthy sink nodes of connection by wordline (polysilicon material) to lower floor, (concrete path is that wordline is connected to substrate through trap, substrate connects load sample platform, by load sample platform ground connection), so change the floating state of wordline, in voltage contrast process, the electric charge of accumulation can import to ground in time, and wordline maintains earth potential all the time.
In voltage contrast picture, as shown in Figure 4, it is do not use the voltage contrast picture before the present invention, interference due to floating electrode stored charge, on tens of up to a hundred addresses, possible defect point (leak current fault) is in whole image and inconspicuous so that be difficult to failpoint is carried out the location of precise and high efficiency.But, the current potential of floating electrode is being carried out after stably, as shown on the right of Fig. 4, defect point (circle circle note place) obtains and highlights, identification is greatly promoted, quickly trouble point can be positioned, as it is shown in figure 5, find after this defect point is analyzed that this place is implicitly present in the leak current fault of abnormal short circuit.
Memory circuitry contact hole level failure positioning method of the present invention, for the board without microprobe equipment, when carrying out voltage contrast and analyzing, focused ion Shu Jinhang circuit is used to repair, floating electrode is shorted to neighbouring steady potential node, and when voltage contrast carries out beam bombardment, the electric charge of floating electrode accumulation can be led away in time, remain stable potential state, eliminate interference when voltage contrast is analyzed by it.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (4)
1. a memory circuitry contact hole level failpoint localization method, it is characterized in that: be for the board without microprobe equipment, use focused ion Shu Jinhang circuit to repair, there is near being shorted to by the electrode of floating state the node of steady potential, then carry out voltage contrast analysis.
2. memory circuitry contact hole level failpoint localization method as claimed in claim 1, it is characterised in that: described in there is the node of steady potential, including the trap of earthing potential.
3. memory circuitry contact hole level failpoint localization method as claimed in claim 1, it is characterized in that: when carrying out voltage contrast and analyzing, the electrode of beam bombardment floating state, the electric charge of electrode accumulation can pass through to be shorted to the node of steady potential, makes the current potential that electrode remains stable for.
4. memory circuitry contact hole level failpoint localization method as claimed in claim 1, it is characterised in that: the electrode of described floating state, material is polysilicon, or is metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610242345.7A CN105810606A (en) | 2016-04-19 | 2016-04-19 | Method for positioning failure point at contact hole level of memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610242345.7A CN105810606A (en) | 2016-04-19 | 2016-04-19 | Method for positioning failure point at contact hole level of memory circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105810606A true CN105810606A (en) | 2016-07-27 |
Family
ID=56458131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610242345.7A Pending CN105810606A (en) | 2016-04-19 | 2016-04-19 | Method for positioning failure point at contact hole level of memory circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105810606A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991598A (en) * | 2017-11-16 | 2018-05-04 | 长江存储科技有限责任公司 | A kind of measuring method for three-dimensional storage raceway groove conduction |
| CN109342920A (en) * | 2018-09-30 | 2019-02-15 | 上海华力集成电路制造有限公司 | IC chip failure independent positioning method |
| CN114093786A (en) * | 2022-01-24 | 2022-02-25 | 澳芯集成电路技术(广东)有限公司 | A contact hole connection position detection method for FDSOI device |
| CN115172195A (en) * | 2022-06-23 | 2022-10-11 | 上海华虹宏力半导体制造有限公司 | Dislocation failure analysis method of read-only memory |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04243147A (en) * | 1991-01-18 | 1992-08-31 | Nec Corp | Failure analyzing method of semiconductor device |
| US20070229092A1 (en) * | 2006-03-29 | 2007-10-04 | International Business Machines Corporation | Test structures and method of defect detection using voltage contrast inspection |
| CN102053098A (en) * | 2009-11-05 | 2011-05-11 | 上海华虹Nec电子有限公司 | Method for positioning low impedance tiny flaws in comb metal wire structure |
| CN103400749A (en) * | 2013-07-23 | 2013-11-20 | 上海华力微电子有限公司 | Failure analysis method for MIM capacitor |
| CN104316813A (en) * | 2014-08-11 | 2015-01-28 | 上海华虹宏力半导体制造有限公司 | Voltage contrast method for determining abnormal short-circuit position |
| CN104535885A (en) * | 2015-01-05 | 2015-04-22 | 武汉新芯集成电路制造有限公司 | Positioning method of word line electric leakage point |
-
2016
- 2016-04-19 CN CN201610242345.7A patent/CN105810606A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04243147A (en) * | 1991-01-18 | 1992-08-31 | Nec Corp | Failure analyzing method of semiconductor device |
| US20070229092A1 (en) * | 2006-03-29 | 2007-10-04 | International Business Machines Corporation | Test structures and method of defect detection using voltage contrast inspection |
| CN102053098A (en) * | 2009-11-05 | 2011-05-11 | 上海华虹Nec电子有限公司 | Method for positioning low impedance tiny flaws in comb metal wire structure |
| CN103400749A (en) * | 2013-07-23 | 2013-11-20 | 上海华力微电子有限公司 | Failure analysis method for MIM capacitor |
| CN104316813A (en) * | 2014-08-11 | 2015-01-28 | 上海华虹宏力半导体制造有限公司 | Voltage contrast method for determining abnormal short-circuit position |
| CN104535885A (en) * | 2015-01-05 | 2015-04-22 | 武汉新芯集成电路制造有限公司 | Positioning method of word line electric leakage point |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107991598A (en) * | 2017-11-16 | 2018-05-04 | 长江存储科技有限责任公司 | A kind of measuring method for three-dimensional storage raceway groove conduction |
| CN107991598B (en) * | 2017-11-16 | 2020-09-11 | 长江存储科技有限责任公司 | Method for measuring conductivity of three-dimensional memory channel |
| CN109342920A (en) * | 2018-09-30 | 2019-02-15 | 上海华力集成电路制造有限公司 | IC chip failure independent positioning method |
| CN114093786A (en) * | 2022-01-24 | 2022-02-25 | 澳芯集成电路技术(广东)有限公司 | A contact hole connection position detection method for FDSOI device |
| CN114093786B (en) * | 2022-01-24 | 2022-04-15 | 澳芯集成电路技术(广东)有限公司 | Contact hole connection position detection method of FDSOI device |
| CN115172195A (en) * | 2022-06-23 | 2022-10-11 | 上海华虹宏力半导体制造有限公司 | Dislocation failure analysis method of read-only memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI526697B (en) | Structure for inspecting defects in word line array fabricated by sadp process and method thereof | |
| CN109686675B (en) | Failure positioning method | |
| CN105810606A (en) | Method for positioning failure point at contact hole level of memory circuit | |
| US6504393B1 (en) | Methods and apparatus for testing semiconductor and integrated circuit structures | |
| US7514681B1 (en) | Electrical process monitoring using mirror-mode electron microscopy | |
| CN110706732B (en) | Failure analysis method of memory chip | |
| US20160341791A1 (en) | Voltage Contrast Based Fault and Defect Inference in Logic Chips | |
| US8748815B2 (en) | Method and system for detecting or reviewing open contacts on a semiconductor device | |
| CN104535885B (en) | The localization method of word line leakage point | |
| CN103456654B (en) | Method of measurement | |
| CN104316813A (en) | Voltage contrast method for determining abnormal short-circuit position | |
| CN104751875A (en) | Failure bitmap analysis method applied to NVM (Non-Volatile Memory) chip | |
| CN105046007A (en) | Positioning method for reverse engineering of integrated circuit chip | |
| US20240361381A1 (en) | In-line electrical detection of defects at wafer level | |
| CN110361644A (en) | A kind of detection device and method of LED chip electric property | |
| TWI473239B (en) | Semiconductor structure and fault location detecting system | |
| CN106251908A (en) | A kind of verification method of the corresponding relation of electrical address and physical address | |
| CN113075533B (en) | Chip detection method and chip detection device | |
| CN116190258A (en) | Failure positioning method and electronic equipment | |
| US9244112B2 (en) | Method for detecting an electrical defect of contact/via plugs | |
| CN104237719A (en) | Leakage defect detection method | |
| CN204289434U (en) | MIM capacitor test structure and MIM capacitor are with reference to test structure | |
| Richter et al. | Implementation of early monitor by advanced ebeam metrology for charging damage failure mechanism | |
| CN114252680B (en) | Voltage contrast method for detecting leakage between source and drain | |
| Xu et al. | A method of contact level PVC enhancement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160727 |