CN116190258A - Failure positioning method and electronic equipment - Google Patents

Abstract

The invention provides a failure positioning method and electronic equipment. Specifically, after the polysilicon gate electrode is grounded, no matter the voltage applied by the probe is positive or negative, the first conductive plug in the active region which is in short circuit with the polysilicon gate electrode can always keep a conducting state, that is, the principle that only the electric signal of the first conductive plug which is in short circuit with the polysilicon gate electrode can be seen on the formed PicoCurrent image all the time is utilized, the region which is formed by the polysilicon line containing the positioned hot spot and a plurality of adjacent polysilicon lines in the measured sample is modified by the FIB line, that is, the formed region is grounded, and then a picoampere current diagram of the measured sample is formed by combining an atomic force microscope, so that the defect position of electric leakage caused by the short circuit between the polysilicon gate electrode in the active region and the conductive plugs positioned at two sides of the polysilicon gate electrode in the measured structure in the measured sample can be rapidly and accurately positioned according to the bright light spots in the picoampere current diagram.

Description

A failure location method and electronic equipment

technical field

The invention relates to the technical field of integrated circuit manufacturing, in particular to a failure location method and electronic equipment.

Background technique

In the semiconductor process, it is usually necessary to design various test structures to monitor various semiconductor process problems on the production line. If an electrical failure event occurs during the monitoring of the test structures, the failure of these test structures can be analyzed. The reason is to help solve the problems existing in the process technology online, and then promote the research and development process of the semiconductor process.

Usually, for a failure analysis of a test structure, the conventional failure analysis process includes: electrical confirmation, failure location location, physical property analysis to find the root cause of the failure; among them, failure location location is a very critical step. At present, in semiconductor The methods commonly used in the industry to locate failure locations can be roughly divided into thermal emission microscopy (Thermal), photon radiation microscopy (EMMI), photoresistance change microscopy (OBIRCH), electron beam resistance change microscopy (EBIRCH), etc.

However, as the semiconductor process technology becomes more and more advanced, the test structures used for testing are not only large in area and high in density, but also more complex. Therefore, the leakage of many test structures due to failure becomes smaller, and the defects that cause failure become It is very small, that is, it is impossible to accurately determine the failure position on the test structure by using the conventional failure position location analysis method adopted in the prior art, or the location is difficult and the location accuracy is not enough.

Therefore, it is necessary to propose a new failure analysis method, which can accurately locate the failure position in the test structure with large area density, high structure and complexity, so that after the failure cause is found through subsequent further failure analysis, the failure can be determined. Products are improved.

Contents of the invention

The object of the present invention is to provide a failure localization method and electronic equipment to solve the problem that in the prior art, it is impossible to precisely locate the gate in the active region of the semiconductor structure or its corresponding test structure and the power grid located on both sides thereof. The leakage failure position between the conductive plugs that are electrically connected to the source and the drain, as well as the technical problems of difficult positioning and insufficient positioning accuracy.

In the first aspect, in order to solve the above technical problems, the present invention provides a failure location method, which may at least include the following steps:

A test structure is provided, the test structure includes an active area, a gate area, and a plurality of polysilicon lines arranged at intervals and passing through the active area and the gate area, and each of the lines corresponding to the active area A plurality of first conductive plugs are also arranged on both sides of the polysilicon circuit;

Performing an electrical failure analysis on the test structure to determine a leakage failure path in the test structure;

performing hotspot capture on the determined leakage failure path to locate the hotspot, and detecting the polysilicon circuit including the located hotspot located in the gate region and a plurality of adjacent polysilicon circuits around it FIB line repair is performed on the measurement sample of the test structure, so that the polysilicon line including the positioned hot spot and the first conductive plugs located in the active region on both sides thereof are in a conducting state;

Using an atomic force microscope, obtain a picoampere current map of the measurement sample of the polysilicon circuit containing the hot spot, and locate the current in the test structure corresponding to the measurement sample according to the picoampere current map Leakage failure location.

Further, the test structure may further include a plurality of second conductive plugs located in the gate region and covering the polysilicon line.

Further, the test structure may further include a first metal layer covering the first conductive plug and the second conductive plug and used for externally connecting the test pad.

Further, using the photoresistance value change microscope and the electron beam resistance value change mode, the determined leakage failure path is captured for hot spots.

Further, after the step of locating the hot spot and before the step of repairing the FIB line on the measurement sample, the failure location method provided by the present invention may further include: removing the first metal layer to expose removing the top surfaces of the first conductive plugs distributed in the active region and the second metal plugs distributed in the gate region.

Further, the step of repairing the FIB circuit on the measurement sample of the test structure including the polysilicon circuit containing the positioned hot spot in the gate region and a plurality of adjacent polysilicon circuits around it may specifically include:

Setting the polysilicon line containing the located hot spot as the target polysilicon line, and taking the target polysilicon line as the center, and setting the target polysilicon line located in the gate region along the direction across the target polysilicon line and multiple polysilicon circuits around it are grounded.

Further, the step of using an atomic force microscope to obtain a picoamp level current map of the measurement sample of the polysilicon circuit containing the hot spot may specifically include:

applying a reverse voltage to the first conductive plug in the active region, so that the polysilicon line corresponding to the non-leakage failure path in the test structure included in the measurement sample is formed by the active region The PN junction is reverse biased;

The picoamp level current map is formed by using an atomic force microscope, wherein the highlighted areas in the picoamp level current map correspond to the electrical signals of the first conductive plug connected to the leakage failure position one by one.

Further, after the step of locating the leakage failure position included in the test structure corresponding to the measurement sample according to the picoamp level current diagram, the failure analysis method provided by the present invention may further include: A step of performing further physical failure analysis on the test structure included in the measurement sample to determine the failure cause of the leakage failure location.

Further, the step of performing electrical failure analysis on the test structure to determine the leakage failure path in the test structure may specifically include:

Provide a voltage to the first conductive pad and the second conductive pad through the test pad to determine the area where the short-circuit failure problem occurs on the test structure, and define the area where the short-circuit failure problem occurs as The leakage failure path.

In the second aspect, based on the same inventive concept as the failure location method described above in the present invention, the present invention also provides an electronic device, which may specifically include a processor, a communication interface, a memory, and a communication bus, wherein, The processor, the communication interface, and the memory communicate with each other through the communication bus;

memory for storing computer programs;

The processor is configured to implement the steps of any one of the fault location methods described in the first aspect when executing the program stored in the memory.

In the third aspect, based on the same inventive concept as the failure location method described above in the present invention, the present invention also provides a computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, When the computer program is executed by a processor, the method steps of any one of the fault location methods in the first aspect are implemented.

In the fourth aspect, based on the same inventive concept as the failure location method described above in the present invention, the present invention also provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the above-mentioned The method steps of the failure location method described in any one of the first aspect.

Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

In a failure location method proposed by the present invention, when the polysilicon gate terminal is grounded, no matter whether the voltage applied by the probe is positive or negative, the first conductive element in the active region that is short-circuited with the polysilicon gate terminal The plug can always remain in the conduction state, that is to say, only the electrical signal of the first conductive plug that is short-circuited with the polysilicon gate can be seen on the formed picoamp level current map (PicoCurrent image), and the measured The region consisting of the polysilicon circuit containing the located hot spot and the surrounding polysilicon circuits in the sample is modified by FIB circuit, that is, the formed region is grounded, and then combined with the atomic force microscope to form the picoampere of the measurement sample. level current diagram, the polysilicon gate in the active region and the conductive plugs on both sides of the test structure in the measurement sample can be quickly and accurately located according to the bright spots in the picoampere current diagram A defective location that causes leakage due to a short circuit.

Apparently, in the failure location method provided by the present invention, it only needs to remove the first metal layer covering the surface of the first conductive plug and the second conductive plug used for external power supply in the test structure, so as to Expose the conductive plug, and then use the FIB line modification function of the FIB device to ground the part of the second conductive plug on the surface of the suspended and exposed polysilicon line in the gate region (realize the grounding of the polysilicon line purpose), the atomic force microscope can be used to quickly and accurately determine the location of the leakage failure, so as to improve the efficiency of failure analysis and reduce the cost of failure analysis, and to find the root cause of the failure of the location of leakage failure for subsequent further use of physical failure analysis , and provide powerful help for the development of new processes and the improvement of yield.

Description of drawings

1 is a schematic layout diagram of a test structure used in the prior art to determine whether there is a leakage defect caused by a short circuit between a polysilicon gate and a metal plug in an active region on both sides thereof;

Figure 2 is a heat map of hotspots located by OBIRCH;

Figure 3 is a SEM plan view of VC positioned to the abnormal first metal plug;

Fig. 4 is a SEM plan view of the verified result of the electrical test again for the first metal plug with abnormal VC;

FIG. 5 is a flow chart of a failure location method provided in an embodiment of the present invention;

FIG. 6 is a schematic diagram of the layout of the final test structure obtained by using a failure location method provided in the embodiment of the present invention;

FIG. 7 is a plan view of a part of the region P including the target polysilicon circuit obtained after repairing the FIB circuit in the gate region 2 by using the failure location method provided by the present invention in an embodiment of the present invention;

FIG. 8 is a cross-sectional view obtained after converting the planar TEM sample formed corresponding to FIG. 7 into a cross-sectional TEM sample in an embodiment of the present invention.

Detailed ways

As mentioned in the background, at present, as the semiconductor process technology becomes more and more advanced, the test structures used for testing are not only large in area and high in density, but also more complex. Therefore, the leakage of many test structures due to failure becomes very small, and the The defect causing the failure also becomes very small, that is, the conventional failure location analysis method adopted in the prior art cannot accurately locate the failure location on the test structure, or the location is difficult and the location accuracy is not enough.

1 is a schematic layout diagram of a test structure used in the prior art to determine whether there is a leakage defect caused by a short circuit between a polysilicon gate and a metal plug in an active region on both sides thereof. Wherein, 100 is a polysilicon gate strip, 120 is a first metal plug located in the active area and electrically connected to the active area, and 130 is a polysilicon gate strip 100 located in the non-active area. The second metal plugs 140a and 140b are metal layers for electrically connecting the first metal plug 120 and the second metal plug 130 respectively. Moreover, the metal layers 140a and 140b are connected to external pads (not shown).

At present, for the layout of the test structure shown in FIG. 1, the second metal plug 130 of the polysilicon gate strip 100 leads to the test pad through the metal layer 140b, and the two first plugs located in the active area The metal plugs 120 are respectively connected to different test pads through the metal layer 140 a to monitor the leakage between the polysilicon gate bar 100 and the first metal plug 120 . The conventional analysis process is to first use OBIRCH/EBIRCH to grab points, but hot spots can only be roughly located. For example, the size of the test structure corresponding to the test structure layout shown in Figure 1 is about 60um*120um, and the corresponding test structure contains There are tens of thousands of polysilicon gate strips 100 and metal plugs, and such hot spots are not enough to find leakage failure locations. It is necessary to further process the measurement sample to the CT layer (metal plug layer), use the nano detector (NanoProber) device to tie the probe on the first metal plug of dozens or even dozens of polysilicon gate strips near the hot spot, and Apply an appropriate voltage to the probe, and use the SEM mode to view the secondary electron image. According to the principle of AVC, the first metal plug that leaks from the polysilicon gate bar will appear different from other first metal plugs in the SEM image. According to the voltage contrast, the first metal plug that leaks with the polysilicon gate strip is highlighted, so as to accurately locate the defect position. However, this method has a large workload and a low success rate. First, the location of the hot spot is not accurate and requires multiple tests. Second, the difference in contrast brought about by VC is not obvious, which requires rich experience of engineers.

Taking the actual case as an example, Figure 2 is a plan view of the hot spot located by OBIRCH. In a test structure with a size of 60um*120um, after roughly measuring the distance between the hot spot and the edge of the structure, the measurement sample is ground to the metal plug layer Finally, stick a needle of the NanoProber on the second metal plug of the polysilicon gate strip, use the AVC principle, focus on the hot spot, combine SEM observation, and try repeatedly until the first metal plug with VC abnormality is found until. Figure 3 is the SEM plan view of VC positioned to the abnormal first metal plug. It can be seen that the difference in VC is very weak, and this step has very high requirements for engineers. Figure 4 is a SEM plan view of the electrical test again for the first metal plug with abnormal VC, and the result of verification, which shows that the first metal plug with abnormal VC is indeed short-circuited with the polysilicon gate strip, that is, it is located where the occurrence occurred The exact location of the leakage failure. Next, TEM analysis is performed. Obviously, the above-mentioned failure analysis method adopted in the prior art has technical problems such as difficulty, time-consuming and high cost, and difficult to grasp the analysis accuracy.

In view of this problem, the inventors of the present invention have found through analysis that: when the polysilicon gate terminal is grounded, no matter whether the voltage applied by the probe is positive or negative, the first conductive plug in the active region short-circuited with the polysilicon gate terminal can be Always keep the conduction state, that is to say, only the electrical signal of the first conductive plug that is short-circuited with the polysilicon gate can be seen on the formed picoamp level current map (PicoCurrent image). Therefore, as long as the probe Applying a reverse voltage to make the first conductive plug in the active region that is not short-circuited with the polysilicon gate terminal reversely bias the PN junction formed by it, then it cannot be in the picoamp level current diagram (PicoCurrent image), that is, the highlighted area in the picoamp level current map (Pico Current image) corresponds to the electrical signal of the first conductive plug connected to the leakage failure position, so that accurate positioning can be achieved Purpose of leakage failure location.

For this reason, the present invention provides a failure localization method and electronic equipment to solve the problem that in the prior art, it is impossible to precisely locate the gate in the active region of the semiconductor structure or its corresponding test structure and the gate located on both sides thereof. The leakage failure position between the conductive plugs used to electrically connect the source and the drain, as well as the technical problems of difficult positioning and insufficient positioning accuracy.

The failure location method and electronic equipment proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention. In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.

As indicated in this application and claims, the terms "a", "an", "an" and/or "the" do not refer to the singular and may include the plural unless the context clearly indicates an exception. Generally speaking, the terms "comprising" and "comprising" only suggest the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also contain other steps or elements. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

Referring to FIG. 5, FIG. 5 is a flowchart of a failure location method provided in an embodiment of the present invention. As shown in FIG. 5, the failure location method provided by the present invention may at least include the following steps:

Step S501, providing a test structure, the test structure includes an active region, a gate region, and a plurality of polysilicon lines arranged at intervals and passing through the active region and the gate region, and located in the corresponding A plurality of first conductive plugs are also arranged on both sides of each polysilicon line;

Step S502, performing electrical failure analysis on the test structure to determine the leakage failure path in the test structure;

Step S503, perform hotspot capture on the determined leakage failure path to locate the hot spot, and search the polysilicon circuit including the located hot spot in the gate region and multiple lines around it performing FIB circuit repair on the test sample of the test structure adjacent to the polysilicon circuit, so that the polysilicon circuit including the positioned hot spot and the first conductive plugs located in the active region on both sides thereof are in a conducting state;

Step S504, using an atomic force microscope to obtain a picoamp level current map of the measurement sample of the polysilicon circuit including the hot spot, and locate the corresponding test structure of the measurement sample according to the picoamp level current map Included leakage failure locations.

In the above step S501, a test structure is firstly provided, wherein the test structure is a metal plug used to test whether the polysilicon gate exists and is located in the active region (namely, the first conductive plug CT1 named in the present invention) ) whether there is a short circuit, and the test structure of the leakage defect problem caused by it, therefore, in this embodiment, it can be the test structure corresponding to the layout shown in Figure 1, but the failure analysis method adopted by the present invention will Subsequent adjustments are made to the test structure, so as to obtain the test structure corresponding to the test structure layout shown in FIG. 6 that is finally used in the present invention.

Specifically, referring to FIG. 6, the test structure used in step S501 may include an active region 1, a gate region 2, and a plurality of polysilicon lines P1 arranged at intervals and passing through the active region 1 and the gate region 2. ~Pn, and a plurality of first conductive plugs CT1 are arranged on both sides of each polysilicon line corresponding to the active region 1 .

Moreover, the test structure used in this step also includes a plurality of second conductive plugs CT2 located in the gate region 2 covering the polysilicon lines, and covering the first conductive plugs CT2. The first metal layer (not shown) on CT1 and the second conductive plug CT2 is used to connect to the test pad.

It can be understood that the test structure including the above components can be formed by using a conventional semiconductor manufacturing process. Gallium, indium phosphide or other III/V compound semiconductors, or divide active regions and gates for silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, and germanium-on-insulator area, and then form a plurality of polysilicon lines spaced apart and through the active area and the gate area on the surface of the entire material, and then form a connection to the active area on both sides of each polysilicon line in the active area. Steps such as CT1 in the region and CT2 for connecting polysilicon lines on the gate region will not be repeated here.

In step S502, electrical failure analysis can be performed on the test structure described in step S501 (also can be understood as the test structure corresponding to the test structure layout shown in FIG. 1 ), so as to determine the leakage in the test structure failure path.

As a preferred example, the step of performing electrical failure analysis on the test structure to determine the leakage failure path in the test structure may include:

Step S502.1, providing a voltage to the first conductive pad and the second conductive pad through the test pad to determine the area where the short-circuit failure occurs on the test structure, and the short-circuit failure occurs The problem area is defined as the leakage failure path. Then, the following step S503 is performed to capture the hot spots of the leakage failure path.

In step S503, a photoresistance change microscope and an electron beam resistance change mode (OBIRCH/EBIRCH) can be used to capture the hot spot of the determined leakage failure path to locate the hot spot; then, use the FIB device The sample preparation function of this test structure is prepared to obtain a measurement sample (not shown), and then the polysilicon circuit containing the positioned hot spot in the gate region 2 and its surrounding The measurement samples of the test structures adjacent to the polysilicon lines are repaired by FIB lines, that is, to obtain the layout corresponding to the final test structure modified by the present invention as shown in FIG. The polysilicon line of the hot spot and the first conductive plugs located in the active region on both sides thereof are in a conduction state.

Wherein, after the hot spot is located in step S503, and before the step of repairing the FIB line on the measurement sample, the failure location method also needs to perform the following steps:

Step S503.1, removing the part used to electrically connect the first conductive plug CT1 and the second conductive plug CT2 included in the test structure described in step S501 and corresponding to the test layout shown in FIG. The first metal layer (not shown) exposes the top surfaces of the first conductive plugs CT1 distributed in the active region 1 and the second metal plugs CT2 distributed in the gate region 2 .

Apparently, in this embodiment, the purpose of removing the first metal layer covering the surfaces of the first conductive plug and the second conductive plug for external power supply in the test structure is to expose the conductive plug Plugs, that is, the second conductive plug CT2 electrically connected to the polysilicon line and the first conductive plug CT1 electrically connected to the active area, and the two will form a PN junction in the active area due to the doping process Therefore, in the step S503, the step of performing FIB line repair on the test sample of the polysilicon line containing the located hot spot and a plurality of adjacent polysilicon lines around it is to suspend and expose the gate region. A part of the area of the second conductive plug CT2 on the surface of the polysilicon line that is exposed is grounded, that is, the purpose of grounding the polysilicon line is achieved.

Then, when the polysilicon gate terminal is grounded, regardless of whether the voltage applied by the probe is positive or negative, the first conductive plug CT1 in the active region 1 that is short-circuited to the polysilicon gate terminal can always maintain a conduction state, That is to say, only the electrical signal of the first conductive plug CT1 short-circuited with the polysilicon gate can always be seen on the formed PicoCurrent image (picoamp level current map), and the purpose of the present invention can be achieved.

As a preferred example, the present invention provides a method for performing FIB on a measurement sample of a test structure including the polysilicon line including the positioned hot spot located in the gate region 2 and a plurality of adjacent polysilicon lines around it. The specific steps of line repair include:

Step S503.2, setting the polysilicon line containing the located hotspot as the target polysilicon line, and taking the target polysilicon line as the center, along the direction across the target polysilicon line, place the The target polysilicon circuit and the multiple polysilicon circuits around it (the area Mark shown in FIG. 6 ) are all grounded.

In this embodiment, after removing the first metal layer as a whole from the measurement sample and processing it to the conductive plug layer, it can be transferred to the FIB device, and the area Mark corresponding to the original area Mark shown in Figure 6 can be repaired using the FIB line repair function The plurality of polysilicon lines are grounded, specifically, the target polysilicon line including the positioned hot spot can be centered, and extended left and right along the X direction (along the direction across the target polysilicon line) in the gate region 2 , make sure to include the polysilicon circuit (that is, the gate Poly) near the hot spot; after that, design a grounding Mark that meets the requirements, and measure the relative angle between the sample and the I-beam can be between 0-52 degrees Select, here take an angle of 52 degrees as an example, select "Cleaning regular section" for the ion beam action mode, the etching depth is required to be Substrate, and the scanning direction is arbitrary.

In step S504, referring to FIG. 7, the atomic force microscope is used to obtain the picoamp level current diagram of the measurement sample of the polysilicon circuit containing the hot spot, and the corresponding position of the measurement sample is located according to the picoamp level current diagram. The leakage failure positions included in the test structure are bridge positions as shown in FIG. 8 .

In this embodiment, the measurement sample prepared in the above steps is transferred to the AFMbaseNano Prober for PicoCurrent test, and finally a picoamp level current map is obtained.

As a preferred example, the step of using an atomic force microscope to obtain a picoamp level current map of the measurement sample of the polysilicon circuit containing the hot spot includes:

Step S504.1, applying a reverse voltage to the first conductive plug in the active region, so that the polysilicon line corresponding to the non-leakage failure path in the test structure included in the measurement sample and the The PN junction formed by the active region is reverse biased;

Step S504.2, using an atomic force microscope to form the picoamp level current map, wherein the highlighted area in the picoamp level current map is one by one with the electrical signal of the first conductive plug connected to the leakage failure position correspond.

Further, after the step of locating the leakage failure location contained in the test structure corresponding to the measurement sample according to the picoamp level current diagram in step S504, the failure analysis method further includes:

Step S505 , performing further physical failure analysis on the test structure contained in the measurement sample, so as to determine the failure cause of the leakage failure location.

To sum up, in a failure localization method proposed by the present invention, when the polysilicon gate terminal is grounded, no matter whether the voltage applied by the probe is positive or negative, the active region short-circuited with the polysilicon gate terminal The first conductive plug in the circuit can always remain in the conduction state, that is to say, only the electrical signal of the first conductive plug that is short-circuited with the polysilicon gate can always be seen on the formed picoamp level current map (PicoCurrent image). The principle is to modify the FIB line in the area composed of the polysilicon line containing the positioned hot spot and the surrounding polysilicon lines in the measurement sample, that is, ground the formed area, and then combine the atomic force microscope to form the FIB line. By measuring the picoamp level current diagram of the sample, the polysilicon gate and the polysilicon gate in the active region existing in the test structure in the measurement sample can be quickly and accurately located according to the bright spots in the picoamp level current diagram. The conductive plug on the side is short-circuited, which leads to the defective position of leakage.

Apparently, in the failure location method provided by the present invention, it only needs to remove the first metal layer covering the surface of the first conductive plug and the second conductive plug used for external power supply in the test structure, so as to Expose the conductive plug, and then use the FIB line modification function of the FIB device to ground the part of the second conductive plug on the surface of the suspended and exposed polysilicon line in the gate region (realize the grounding of the polysilicon line purpose), the atomic force microscope can be used to quickly and accurately determine the location of the leakage failure, so as to improve the efficiency of failure analysis and reduce the cost of failure analysis, and to find the root cause of the failure of the location of leakage failure for subsequent further use of physical failure analysis , and provide powerful help for the development of new processes and the improvement of yield.

In addition, an embodiment of the present invention also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory complete communication with each other through the communication bus,

memory for storing computer programs;

The processor is configured to implement the method steps described in the failure location method above when executing the program stored in the memory.

For the specific implementation of each step of the method and related explanations, refer to the method embodiment shown in FIG. 6 above, and details are not repeated here.

In addition, other implementations of the application setting method implemented by the processor executing the program stored in the memory are the same as the implementations mentioned in the foregoing method embodiments, and will not be repeated here.

In yet another embodiment provided by the present invention, the embodiment of the present invention also provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the above-mentioned The steps of the failure location method.

In yet another embodiment provided by the present invention, the embodiment of the present invention further provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the above fault location method.

In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, all or part of the processes or functions according to the embodiments of the present invention will be generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, DSL) or wireless (eg, infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrated with one or more available media. The available medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, ), or a semiconductor medium (for example, a Solid State Disk (SSD)).

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. any such actual relationship or order exists between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Each embodiment in this specification is described in a related manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, user terminal, computer-readable storage medium, and computer program product embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For relevant parts, please refer to the part of the description of the method embodiments.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present invention are included in the protection scope of the present invention.

Claims (10)

1. The failure positioning method is characterized by at least comprising the following steps:

providing a test structure, wherein the test structure comprises an active region, a gate region and a plurality of polysilicon lines which are arranged at intervals and penetrate through the active region and the gate region, and a plurality of first conductive plugs are arranged on two sides of each polysilicon line corresponding to the active region;

performing electrical failure analysis on the test structure to determine a leakage failure path in the test structure;

performing hot spot grabbing on the determined leakage failure path to locate the hot spot, and performing FIB circuit repairing on a measurement sample including a polysilicon circuit located in the gate region and including the located hot spot and a plurality of test structures adjacent to the polysilicon circuit around the polysilicon circuit, so that the polysilicon circuit including the located hot spot and first conductive plugs located in the active region on two sides of the polysilicon circuit;

and acquiring a Pian-level current diagram of the measurement sample of the polysilicon line containing the hot spot by adopting an atomic force microscope, and positioning the leakage failure position contained in the test structure corresponding to the measurement sample according to the Pian-level current diagram.

2. The failure localization method of claim 1, wherein the test structure further comprises a plurality of second conductive plugs in the gate region overlying the polysilicon lines.

3. The failure localization method of claim 2, wherein the test structure further comprises a first metal layer overlying the first and second conductive plugs for circumscribing a test pad.

4. The failure positioning method according to claim 1, wherein the determined leakage failure path is subjected to hot spot capturing by using a photoresistance change microscope and an electron beam photoresistance change mode.

5. A failure localization method as claimed in claim 3, wherein after the step of locating the hot spot and before the step of FIB line repair of the measurement sample, the failure localization method further comprises: the first metal layer is removed to expose top surfaces of the first conductive plugs distributed in the active region and the second metal plugs distributed in the gate region.

6. The failure localization method of claim 5, wherein performing FIB line repair on a measurement sample including a polysilicon line including the located hot spot in the gate region and a plurality of test structures surrounding the polysilicon line, comprises:

and setting the polysilicon line containing the positioned hot spot as a target polysilicon line, and taking the target polysilicon line as a center, and carrying out grounding treatment on the target polysilicon line and a plurality of polysilicon lines around the target polysilicon line in the gate region along the direction crossing the target polysilicon line.

7. The failure localization method of claim 1, wherein the step of acquiring a picoampere-scale current map of the measurement sample of the polysilicon line containing the hot spot using an atomic force microscope comprises:

applying a reverse voltage to the first conductive plug in the active region to reverse bias a PN junction formed by the polysilicon line corresponding to the non-leakage failure path in the test structure contained in the measurement sample and the active region;

and forming the Pitaan-level current diagram by using an atomic force microscope, wherein the marked area in the Pitaan-level current diagram corresponds to the electric signal of the first conductive plug connected with the electric leakage failure position one by one.

8. The failure localization method of claim 1, wherein after the step of locating the leakage failure location contained in the test structure corresponding to the measurement sample according to the picoampere-level current map, the failure analysis method further comprises: and further performing physical failure analysis on the test structure contained in the measurement sample to determine the failure reason of the leakage failure position.

9. A failure localization method as claimed in claim 3, wherein the step of performing an electrical failure analysis on the test structure to determine a leakage failure path in the test structure comprises:

and providing a voltage for the first conductive bonding pad and the second conductive bonding pad through the test bonding pad so as to determine the area of the test structure where the short-circuit failure problem occurs, and defining the area where the short-circuit failure problem occurs as the leakage failure path.

10. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;

a memory for storing a computer program;

a processor for implementing the method steps of the failure localization method according to any one of claims 1 to 9 when executing a program stored on a memory.

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