CN105763047B - A kind of all-wave inductive current sample circuit - Google Patents

Abstract

The invention discloses a full-wave inductor current sampling circuit, which includes a system power stage circuit, a proportional MOS tube current sampling circuit, a voltage-to-current and current summation circuit, and a sampling DC correction and sampling integration circuit. The power stage circuit of the system The first output end is further connected to the first input end of the sampling DC correction and sampling integration circuit through the proportional MOS tube current sampling circuit, and the second output end of the system power stage circuit is further connected to the voltage-to-current and current summation circuit. The second input end of the sampling DC correction and sampling integration circuit. The present invention can realize accurate full-wave inductor current sampling through the system power level circuit, proportional MOS tube current sampling circuit, voltage-to-current and current summation circuit, sampling DC correction and sampling integration circuit, and can obtain continuous sampling signals, effectively avoiding There is a glitch problem. The invention can be widely applied in the field of electronic circuits.

Description

A full-wave inductor current sampling circuit

technical field

The invention relates to the technical field of electronic circuits, in particular to a full-wave inductor current sampling circuit.

Background technique

Single-inductor multiple-output (Single-Inductor Multiple-Output, SIMO) DC-DC converter is a new type of DC-DC converter structure in which inductors are time-division multiplexed. The system only needs one inductor to provide multiple independent output. Therefore, the number of off-chip inductors is greatly reduced, the volume of the converter is reduced, and the cost is reduced. In recent years, the automatic buck-boost single-inductance multi-output DC-DC converter has expanded the application range of this type of converter.

The power stage circuit of the automatic lifting type single-inductance multi-output DC-DC converter is shown in Figure 1. The power stage circuit includes an input-stage switch group and an output-stage switch group. The input-stage switch group includes a PMOS transistor M _ip and a The NMOS transistor M _in , the output stage switch group includes an NMOS transistor M _on and n PMOS transistors M _op1 -M _opn . When the converter is working, the control signals G _{o1 ˜G on} control the switch groups of the output stage to be turned on sequentially, and simultaneous conduction will not occur.

At present, the most widely used control method of single-inductor multiple-output DC-DC converter is Ordered Power Distributive Control (OPDC), that is, within one cycle, the inductor is charged once, and then according to a certain Discharge each output channel sequentially. In order to implement current-mode control, over-current protection, and detect discontinuous conduction mode (Discontinuous Conduction Mode, DCM), we must accurately sense the inductor current during the entire duty cycle. At present, the commonly used inductor current sampling circuit with high sampling accuracy is the proportional MOS tube inductor current sampling circuit.

Figure 2 shows a half-wave proportional MOS tube inductor current sampling circuit, in which the width-to-length ratio of the power switch tube M _ip is K times the width-to-length ratio of the sampling tube M _psen . When the power switch M _ip is turned on (that is, the power switch M _in is cut off), the switch S ₁ is disconnected, the switch S ₂ is closed, V _X1 is connected to the inverting input terminal of the operational amplifier Amp1, and the operational amplifier Amp1 and the adjustment tube M _n makes the potentials of the non-inverting input terminal and the inverting input terminal of the operational amplifier equal, at this time, the potentials of the gate, source and drain of the power switch M _ip and the sampling tube M _psen are respectively equal, and the power switch M The width-to-length ratio of _ip is K times the width-to-length ratio of the sampling tube M _psen , so the current flowing through the sampling tube M _psen is 1/K of the current of the power switch tube M _ip (equal to the inductor current during this period), and then The sampling current is converted into a voltage V _{sen through the sampling resistor R sen .} The relationship between them is When the power switch M _in is turned on (that is, the power switch M _ip is cut off), the switch S ₂ is turned off, the switch S ₁ is closed, and V _in is connected to the inverting input terminal of the operational amplifier Amp1, so the output of the operational amplifier is When it is pulled low, the adjustment tube M _{n is} cut off, and V _sen is 0. At this time, the inductor current information cannot be detected, so it is a half-wave inductor current sampling. The advantage of this proportional MOS tube current sampling circuit is that the circuit structure is simple, the sampling accuracy is high, the power consumption is relatively small, and it can work in a switching frequency circuit above 10MHz; the disadvantage is that it can only sample the half-wave inductor current and cannot be used in automatic Buck-boost single inductor multiple output DC-DC converter.

Figure 3 shows the full-wave proportional MOS tube inductor current sampling circuit. The essence of this circuit is to combine two half-wave sampling circuits. The two half-wave sampling circuits respectively detect the conduction period of the power switch tube M _ip and the power switch The inductor current during the turn-on period of the tube _Min , and then the detected current is converted into a voltage V _sen through the same sampling resistor R _sen . Although this method obtains full-wave inductor current information, there are still many shortcomings. First, due to the dead time between the conduction of the power switch M _ip and the conduction of the power switch M _in and the action of the switches S ₁ ~ S ₄ , there are many glitches in the detected current waveform during switching, as shown in the figure 4, this can cause false triggering of the system. Second, due to the problem of circuit mismatch, the detected current waveform will change suddenly when switching (as shown in the dotted ellipse in Figure 4, the sampling voltage V _sen will change suddenly), but in fact the inductor current is not Mutations may occur, which may cause system instability.

Contents of the invention

In order to solve the above technical problems, the object of the present invention is to provide a full-wave inductor current sampling circuit capable of continuous sampling and high sampling accuracy.

The technical scheme that the present invention takes is:

A full-wave inductor current sampling circuit, including a system power stage circuit, a proportional MOS tube current sampling circuit, a voltage-to-current and current summation circuit, and a sampling DC correction and sampling integration circuit, the first output terminal of the system power stage circuit The proportional MOS tube current sampling circuit is further connected to the first input terminal of the sampling DC correction and sampling integration circuit, and the second output terminal of the system power stage circuit is further connected to the sampling DC correction and the sampling integration circuit through the voltage-to-current and current summation circuit. The second input terminal of the sampling integration circuit.

As a further improvement of the present invention, the system power stage circuit includes a first PMOS transistor, a first NMOS transistor, a second NMOS transistor and an inductor, and the source of the first PMOS transistor is connected to the input of the proportional MOS transistor current sampling circuit respectively. terminal is connected to the voltage input terminal, and the drain of the first PMOS tube is connected to the second input terminal of the proportional MOS tube current sampling circuit, the drain of the first NMOS tube, and the input terminal of the voltage-to-current and current summation circuit respectively The drain of the first PMOS transistor is connected to the drain of the second NMOS transistor through an inductor, and the drain of the second NMOS transistor is connected to the third input end of the voltage-to-current and current summation circuit.

As a further improvement of the present invention, the voltage-to-current and current summation circuit includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth An NMOS transistor, a sixth NMOS transistor, a first resistor, a second resistor, a first operational amplifier, and a second operational amplifier, the source of the second PMOS transistor, the source of the third PMOS transistor, and the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are connected to the power supply terminal, and the gate of the second PMOS transistor is respectively connected to the drain of the second PMOS transistor, the drain of the third NMOS transistor, and the gate of the third PMOS transistor , the gate of the fifth PMOS transistor is respectively connected to the drain of the fifth PMOS transistor, the drain of the fourth NMOS transistor and the gate of the fourth PMOS transistor, and the drain of the third PMOS transistor is respectively connected to the sampling DC The second input terminal of the correction and sampling integration circuit is connected to the drain of the fifth NMOS transistor, and the drain of the fourth PMOS transistor is respectively connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor, and the fifth NMOS transistor. The gate of the transistor is connected, the gate of the third NMOS transistor is connected to the output terminal of the first operational amplifier, and the source of the third NMOS transistor is respectively connected to the first end of the first resistor and the opposite of the first operator. The non-inverting input terminal of the first operator is connected to the drain of the first PMOS transistor, the gate of the fourth NMOS transistor is connected to the output terminal of the second operational amplifier, and the fourth NMOS transistor The source of the second resistor is respectively connected to the first terminal of the second resistor and the inverting input terminal of the second operator, and the non-inverting input terminal of the second operator is connected to the drain of the second NMOS transistor.

As a further improvement of the present invention, the sampling DC correction and sampling integration circuit includes a buffer, a switch and a sampling integration capacitor, the output end of the proportional MOS tube current sampling circuit is connected to the input end of the buffer, and the output end of the buffer is The output end is connected to the first end of the sampling integration capacitor through the switch, and the first end of the sampling integration capacitor is connected to the drain of the third PMOS transistor.

As a further improvement of the present invention, the sampling DC correction and sampling integration circuit includes a third operational amplifier, a sampling integration capacitor, a first capacitor, a second capacitor, a third resistor, a fourth resistor, a sixth PMOS transistor, and a seventh PMOS transistor. tube, the eighth PMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube and the eleventh NMOS tube, the output end of the proportional MOS tube current sampling circuit is connected to the third operational amplifier The inverting input terminal of the third operational amplifier, the output terminal of the third operational amplifier is respectively connected to the first terminal of the first capacitor and the gate of the seventh NMOS transistor, and the output terminal of the third operational amplifier is connected to the first terminal through the third resistor. The first end of the second capacitor, the source of the sixth PMOS transistor, the source of the seventh PMOS transistor and the source of the eighth PMOS transistor are all connected to the power supply terminal, and the gate of the sixth PMOS transistor is connected to the first PMOS transistor respectively. The drains of the six PMOS transistors are connected to the drains of the seventh NMOS transistors, and the gates of the seventh PMOS transistors are respectively connected to the drains of the seventh PMOS transistors, the gates of the eighth PMOS transistors, and the drains of the eighth NMOS transistors. The source of the seventh NMOS transistor is respectively connected to the first end of the fourth resistor and the drain of the ninth NMOS transistor, and the source of the eighth NMOS transistor is respectively connected to the second end of the fourth resistor and the drain of the ninth NMOS transistor. The drain of the tenth NMOS transistor is connected, the grid of the ninth NMOS transistor, the grid of the tenth NMOS transistor and the grid of the eleventh NMOS transistor are all connected to the bias voltage terminal, and the gate of the third operational amplifier The non-inverting input end is respectively connected with the drain of the eighth PMOS transistor, the drain of the eleventh NMOS transistor, the first terminal of the sampling integration capacitor and the drain of the third PMOS transistor.

The beneficial effects of the present invention are:

A full-wave inductor current sampling circuit of the present invention can realize accurate full-wave inductor current sampling through a system power stage circuit, a proportional MOS tube current sampling circuit, a voltage-to-current and current summation circuit, and a sampling DC correction and sampling integration circuit, and The continuous sampling signal can be obtained, effectively avoiding the problem of glitches, and can be used for precise control, overcurrent protection, and detection of discontinuous inductor current modes in single-inductor multi-output DC-DC converters.

Description of drawings

The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing:

Figure 1 is a power stage circuit diagram of an automatic lifting type single-inductance multi-output DC-DC converter;

Figure 2 is a schematic diagram of a half-wave proportional MOS tube inductance current sampling circuit;

Fig. 3 is a schematic diagram of a full-wave proportional MOS tube inductance current sampling circuit;

Fig. 4 is a typical sampling waveform diagram of a full-wave proportional MOS tube inductance current sampling circuit;

Fig. 5 is the principle block diagram of a kind of full-wave inductor current sampling circuit of the present invention;

Fig. 6 is the circuit principle diagram of a kind of full-wave inductor current sampling circuit embodiment 1 of the present invention;

FIG. 7 is a schematic circuit diagram of Embodiment 2 of a full-wave inductor current sampling circuit of the present invention.

Detailed ways

With reference to Fig. 5, a kind of full-wave inductor current sampling circuit of the present invention comprises system power level circuit, proportional MOS tube current sampling circuit, voltage conversion current and current summation circuit and sampling DC correction and sampling integral circuit, described system power level The first output terminal of the circuit is further connected to the first input terminal of the sampling DC correction and sampling integration circuit through the proportional MOS tube current sampling circuit, and the second output terminal of the system power stage circuit is further connected to the voltage-to-current and current summation circuit. Connect to the second input end of the sampling DC correction and sampling integration circuit.

As a further preferred embodiment, the system power stage circuit includes a first PMOS transistor M1, a first NMOS transistor N1, a second NMOS transistor N2 and an inductor L, and the source of the first PMOS transistor M1 is connected to the proportional MOS transistor The input end of the current sampling circuit is connected to the voltage input end, and the drain electrode of the first PMOS transistor M1 is respectively connected to the second input end of the proportional MOS transistor current sampling circuit, the drain electrode of the first NMOS transistor N1, and the voltage conversion current and the current The input end of the summation circuit is connected, the drain of the first PMOS transistor M1 is connected to the drain of the second NMOS transistor N2 through the inductor L, and the drain of the second NMOS transistor N2 is converted from voltage to current and summed The third input terminal of the circuit is connected.

In the embodiment of the present invention, the voltage-to-current and current summation circuit includes two voltage-to-current circuits and a current summation circuit. The two voltage-to-current circuits convert the voltages V _X1 and V _X2 at both ends of the inductor L into currents, and then subtract the two currents. The subtracted current charges the sampling capacitor, and the voltage at both ends of the sampling capacitor is the sampling signal. . Due to the impact of non-ideal factors such as the DC resistance DCR of the inductor L, the DC value of the sampling signal is offset, so a sampling DC correction circuit is needed to perform DC correction. In the calibration process, a reference signal needs to be obtained by traditional proportional MOS tube sampling method.

In an ideal situation, that is, regardless of the influence of the DC resistance DCR of the inductor L, according to the relationship between the current of the inductor L and the voltage across the inductor L, it can be known that the current of the inductor L at a certain moment is: Assuming that the gains of the two voltage-to-current circuits are both g _m , then the voltages V _X1 (τ) and V _X2 (τ) across the inductor L are converted into currents, respectively g _m *V _X1 (τ) and g _m *V _X2 (τ), the two currents are subtracted to charge the sampling capacitor. According to the relationship between the voltage across the capacitor and the charging current of the capacitor, it can be known that the voltage across the capacitor at a certain moment is: From this we get: or It can be seen that the voltage u _C (t) across the capacitor at a certain moment is proportional to the current i _L (t) flowing through the inductor L, and the proportionality coefficient g _m L/C is a fixed value, so it can be said that the capacitor The voltage u _C (t) across both ends is the sampling value of the current i _L (t) of the inductor L.

But in the actual situation, the inductor L has a DC resistance DCR, so there will be a DC voltage error u _DC (t)=i _L (t)*DCR, in this case, the current of the inductor L at a certain moment is:

The voltage across the capacitor is still: From this we get: Since the current of the inductor L in the DC-DC cannot flow backwards, that is, i _L (t)≥0, so u _DC (t)≥0. So it can be seen that the voltage u _C (t) across the capacitor at a certain moment is no longer proportional to the current i _L (t) flowing through the inductor L, but there is an error Moreover, this error will become larger and larger as time goes by, resulting in a DC deviation in the inductor L current value obtained by capacitance sampling, so sampling DC correction and sampling integration circuits are required for DC correction. In the calibration process, a reference signal needs to be obtained by traditional proportional MOS tube sampling method.

Referring to FIG. 6, in Embodiment 1 of the present invention, the voltage-to-current and current summation circuit includes a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth PMOS transistor M5, and a third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the first resistor R1, the second resistor R2, the first operational amplifier Amp1 and the second operational amplifier Amp2, the second PMOS transistor M2 The source, the source of the third PMOS transistor M3, the source of the fourth PMOS transistor M4 and the source of the fifth PMOS transistor M5 are all connected to the power supply terminal, and the gate of the second PMOS transistor M2 is connected to the second PMOS transistor M2 respectively. The drain of the transistor M2, the drain of the third NMOS transistor N3 are connected to the gate of the third PMOS transistor M3, and the gate of the fifth PMOS transistor M5 is respectively connected to the drain of the fifth PMOS transistor M5 and the fourth NMOS transistor. The drain of N4 is connected to the gate of the fourth PMOS transistor M4, the drain of the third PMOS transistor M3 is respectively connected to the input terminal of the sampling DC correction and sampling integration circuit and the drain of the fifth NMOS transistor N5, and the drain of the third PMOS transistor M3 is connected to the drain of the fifth NMOS transistor N5. The drain of the fourth PMOS transistor M4 is respectively connected to the drain of the sixth NMOS transistor N6, the gate of the sixth NMOS transistor N6, and the gate of the fifth NMOS transistor N5, and the gate of the third NMOS transistor N3 is connected to the gate of the sixth NMOS transistor N6. The output terminal of an operational amplifier Amp1 is connected, the source of the third NMOS transistor N3 is respectively connected with the first terminal of the first resistor R1 and the inverting input terminal of the first computing unit, and the non-inverting input terminal of the first computing unit The terminal is connected to the drain of the first PMOS transistor M1, the gate of the fourth NMOS transistor N4 is connected to the output end of the second operational amplifier Amp2, and the source of the fourth NMOS transistor N4 is respectively connected to the second resistor R2. The first end is connected to the inverting input end of the second arithmetic unit, and the non-inverting input end of the second arithmetic unit is connected to the drain of the second NMOS transistor N2. The sampling direct current correction and sampling integration circuit includes a buffer Buffer, a switch S and a sampling integration capacitor C, the output end of the proportional MOS tube current sampling circuit is connected with the input end of the buffer Buffer, and the output end of the buffer Buffer The switch S is connected to the first terminal of the sampling and integrating capacitor C, and the first terminal of the sampling and integrating capacitor C is connected to the drain of the third PMOS transistor M3.

Wherein, refer to FIG. 1 for a detailed introduction of the power stage circuit of the system. The proportional MOS tube current sampling circuit can either adopt the half-wave proportional MOS tube inductance current sampling circuit in FIG. 2 or the full-wave proportional MOS tube inductance current sampling circuit in FIG. background part. In the voltage-to-current and current summation circuit, the voltage-to-current circuit 1 composed of the first operational amplifier Amp1, the third NMOS transistor N3, and the first resistor R1 is composed of the second operational amplifier Amp2, the fourth NMOS transistor N4, and the second resistor The voltage-to-current circuit 2 composed of R2, three pairs of current circuits composed of the second PMOS transistor M2 and the third PMOS transistor M3, the fourth PMOS transistor M4 and the fifth PMOS transistor M5, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 mirror. The voltage-to-current circuit 1 converts the voltage at V _X1 into a current, and then copies the current mirror through the current mirror composed of the second PMOS transistor M2 and the third PMOS transistor M3, and then injects current into the V _sense node; the voltage-to-current circuit 2 Convert the voltage at V _X2 into a current, and then copy the current mirror through the current mirror composed of the fifth PMOS transistor M5 and the fourth PMOS transistor M4, the fifth NMOS transistor N5 and the sixth NMOS transistor N6, and then from the V _sense node The current is pulled out, so that the current subtraction is realized at this node, that is, the subtracted current flows out from the V _sense node to charge the sampling integration capacitor C. Finally, there is a sampling DC correction circuit and a sampling integration capacitor C module, which includes a buffer Buffer, a switch S and a sampling integration capacitor C. The input of the buffer Buffer is connected to the V _sen output of the proportional MOS tube current sampling circuit. When the proportional MOS tube current sampling circuit works stably, its output V _sen is relatively accurate, so the switch S can be closed for a period of time at this time. In a short period of time, the voltage of the sampling integration capacitor C is forced to be equal to the output V _sen of the proportional MOS tube current sampling circuit, thereby realizing reset correction. According to the previous analysis, the size of the error signal is If the switch S is closed for a short period of time in each working cycle of SIMO DC-DC to realize a reset, the error accumulation time is short, so the error generated is very small, and the sampling voltage obtained on the sampling capacitor can accurately reflect the inductance current information.

Referring to FIG. 7, in Embodiment 2 of the present invention, the voltage-to-current and current summation circuit includes a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a fifth PMOS transistor M5, and a third NMOS transistor. N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the first resistor R1, the second resistor R2, the first operational amplifier Amp1 and the second operational amplifier Amp2, the second PMOS transistor M2 The source, the source of the third PMOS transistor M3, the source of the fourth PMOS transistor M4 and the source of the fifth PMOS transistor M5 are all connected to the power supply terminal, and the gate of the second PMOS transistor M2 is connected to the second PMOS transistor M2 respectively. The drain of the transistor M2, the drain of the third NMOS transistor N3 are connected to the gate of the third PMOS transistor M3, and the gate of the fifth PMOS transistor M5 is respectively connected to the drain of the fifth PMOS transistor M5 and the fourth NMOS transistor. The drain of N4 is connected to the gate of the fourth PMOS transistor M4, the drain of the third PMOS transistor M3 is respectively connected to the input terminal of the sampling DC correction and sampling integration circuit and the drain of the fifth NMOS transistor N5, and the drain of the third PMOS transistor M3 is connected to the drain of the fifth NMOS transistor N5. The drain of the fourth PMOS transistor M4 is respectively connected to the drain of the sixth NMOS transistor N6, the gate of the sixth NMOS transistor N6, and the gate of the fifth NMOS transistor N5, and the gate of the third NMOS transistor N3 is connected to the gate of the sixth NMOS transistor N6. The output terminal of an operational amplifier Amp1 is connected, the source of the third NMOS transistor N3 is respectively connected with the first terminal of the first resistor R1 and the inverting input terminal of the first computing unit, and the non-inverting input terminal of the first computing unit The terminal is connected to the drain of the first PMOS transistor M1, the gate of the fourth NMOS transistor N4 is connected to the output end of the second operational amplifier Amp2, and the source of the fourth NMOS transistor N4 is respectively connected to the second resistor R2. The first end is connected to the inverting input end of the second arithmetic unit, and the non-inverting input end of the second arithmetic unit is connected to the drain of the second NMOS transistor N2. The sampling DC correction and sampling integration circuit includes a third operational amplifier Amp3, a sampling integration capacitor C, a first capacitor C1, a second capacitor C2, a third resistor R3, a fourth resistor R4, a sixth PMOS transistor M6, and a seventh PMOS transistor Tube M7, eighth PMOS tube M8, seventh NMOS tube N7, eighth NMOS tube N8, ninth NMOS tube N9, tenth NMOS tube N10 and eleventh NMOS tube N11, the output of the proportional MOS tube current sampling circuit terminal is connected to the inverting input terminal of the third operational amplifier Amp3, the output terminal of the third operational amplifier Amp3 is respectively connected to the first terminal of the first capacitor C1 and the gate of the seventh NMOS transistor N7, the third operational amplifier The output end of the amplifier Amp3 is connected to the first end of the second capacitor C2 through the third resistor R3, the source of the sixth PMOS transistor M6, the source of the seventh PMOS transistor M7 and the source of the eighth PMOS transistor M8 are all The gate of the sixth PMOS transistor M6 is connected to the drain of the sixth PMOS transistor M6 and the drain of the seventh NMOS transistor N7 respectively, and the gate of the seventh PMOS transistor M7 is connected to the drain of the seventh NMOS transistor M7 respectively. The drain of the PMOS transistor M7, the gate of the eighth PMOS transistor M8, and the drain of the eighth NMOS transistor N8 are connected, and the source of the seventh NMOS transistor N7 is respectively connected to the first end of the fourth resistor R4 and the ninth end of the fourth resistor R4. The drain of the NMOS transistor N9 is connected, the source of the eighth NMOS transistor N8 is respectively connected to the second end of the fourth resistor R4 and the drain of the tenth NMOS transistor N10, the gate of the ninth NMOS transistor N9, Both the gate of the tenth NMOS transistor N10 and the gate of the eleventh NMOS transistor N11 are connected to the bias voltage terminal, and the non-inverting input terminal of the third operational amplifier Amp3 is respectively connected to the drain of the eighth PMOS transistor M8 and the tenth PMOS transistor M8. The drain of an NMOS transistor N11, the first terminal of the sampling integration capacitor C and the drain of the third PMOS transistor M3 are connected.

Wherein, refer to FIG. 1 for a detailed introduction of the power stage circuit of the system. The proportional MOS tube current sampling circuit is the full-wave proportional MOS tube inductance current sampling circuit in FIG. 3 . For a detailed introduction, refer to the introduction to FIG. 3 in the technical background section. The voltage-to-current circuit and the current summation circuit module are the same as those in Embodiment 1, and the subtracted current flows out from the V _sense node to charge the sampling integration capacitor C. Finally, it is a sampling DC correction and sampling integration circuit. This circuit module includes a proportional integrator (in the dotted line box in Fig. 7) composed of the third operational amplifier Amp3, the first capacitor C1, the second capacitor C2, and the third resistor R3; A current subtraction circuit composed of the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, the tenth NMOS transistor N10, the eleventh NMOS transistor N11 and the fourth resistor R4. The non-inverting input terminal of the third operational amplifier Amp3 is connected to the sampling voltage V _sense on the sampling integration capacitor C, and the inverting input terminal is connected to the sampling voltage V _sen of the proportional MOS tube current sampling circuit. After passing through the proportional integrator, the output terminal of the proportional integrator Connect to the gate of the seventh NMOS transistor N7. The ninth NMOS transistor N9, the tenth NMOS transistor N10 and the eleventh NMOS transistor N11 are biased by the same fixed voltage V _bias , so the ninth NMOS transistor N9, the tenth NMOS transistor N10 and the eleventh NMOS transistor N11 are equivalent In three constant current sources, and the currents are equal.

When the input V _sense of the proportional integrator is equal to V _sen , the output of the proportional integrator is the common mode output of the operational amplifier, and its value is about V _CC /2. At this time, the seventh NMOS transistor N7 and the eighth NMOS transistor N8 The bias conditions are the same, so the currents flowing through the MOS transistors N7 and N8 are equal, and they are all equal to the constant currents provided by the MOS transistors N9, N10 and N11. Since the seventh NMOS transistor N7 and the eighth NMOS transistor N8 form a current mirror, the current flowing through the eighth PMOS transistor M8 is equal to the current flowing through the seventh PMOS transistor M7, which is also equal to the ninth NMOS transistor N9 and the tenth NMOS transistor N10 and the constant current provided by the eleventh NMOS transistor N11, so the output current of the DC correction circuit at the V _sense node is 0, and the current flowing through the fourth resistor R4 is also 0, and correction is not required at this time.

When the input V _sense of the proportional integrator is greater than V _sen , the output of the proportional integrator increases, so the current flowing through the seventh NMOS transistor N7 increases, and flows through the ninth NMOS transistor N9, the tenth NMOS transistor N10 and The current of the eleventh NMOS transistor N11 is a constant value, so the excess current flows to the tenth NMOS transistor N10 through the fourth resistor R4, and the current flowing through the eighth NMOS transistor N8 decreases, so it flows through the seventh PMOS transistor M7 and The current of the eighth PMOS transistor M8 decreases. At this time, for the V _sense node, the current poured through the eighth PMOS transistor M8 is smaller than the current pulled out through the eleventh NMOS transistor N11, so the sampling integration capacitor C will be discharged by the sampling DC correction and sampling integration circuit, and the node The voltage of V _sense decreases until V _sense is equal to V _sen , thus achieving correction.

When the input V _sense of the proportional integrator is smaller than V _sen , the output of the proportional integrator decreases, so the current flowing through the seventh NMOS transistor N7 decreases, and flows through the ninth NMOS transistor N9, the tenth NMOS transistor N10 and the The current of the eleventh NMOS transistor N11 is a constant value, so the insufficient current is provided by the eighth NMOS transistor N8 through the fourth resistor R4, so the current flowing through the eighth NMOS transistor N8 increases, so it flows through the seventh PMOS transistor M7 and The current of the eighth PMOS transistor M8 also increases. At this time, for the V _sense node, the current poured in through the eighth PMOS transistor M8 is greater than the current pulled out through the eleventh NMOS transistor N11, so the sampling integration capacitor C will be charged by the sampling DC correction circuit, and the node V _sense The voltage will increase until V _sense is equal to V _sen , thus achieving correction.

The sampling voltage V _sense on the corrected sampling integration capacitor C is equal to the voltage V _sen sampled by the proportional MOS tube current sampling circuit, which not only realizes accurate sampling of the inductor L current, but also has a continuous waveform, and switches between circuit states Therefore, it can be used for precise control of automatic buck-boost single-inductor L multi-output DC-DC converter, over-current protection, and detection of discontinuous inductance L current mode (DCM). There will be no false triggers and no system instability.

The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent deformations or replacements without violating the spirit of the present invention. , these equivalent modifications or replacements are all within the scope defined by the claims of the present application.

Claims (5)

1. A full-wave inductance current sampling circuit is characterized in that: comprise system power level circuit, proportional MOS tube current sampling circuit, voltage conversion current and current summation circuit and sampling DC correction and sampling integral circuit, described system power level The first output terminal of the circuit is further connected to the first input terminal of the sampling DC correction and sampling integration circuit through the proportional MOS tube current sampling circuit, and the second output terminal of the system power stage circuit is further connected to the voltage-to-current and current summation circuit. Connect to the second input end of the sampling DC correction and sampling integration circuit. 2. A kind of full-wave inductor current sampling circuit according to claim 1, characterized in that: said system power stage circuit comprises a first PMOS transistor, a first NMOS transistor, a second NMOS transistor and an inductor, said first The source of the PMOS tube is connected to the input terminal and the voltage input terminal of the proportional MOS tube current sampling circuit respectively, and the drain of the first PMOS tube is connected to the second input terminal of the proportional MOS tube current sampling circuit and the first NMOS tube respectively. The drain is connected to the input terminal of the voltage-to-current and current summation circuit, the drain of the first PMOS transistor is connected to the drain of the second NMOS transistor through an inductor, and the drain of the second NMOS transistor is connected to the voltage-to-current and the third input terminal of the current summation circuit. 3. A kind of full-wave inductance current sampling circuit according to claim 2, is characterized in that: described voltage turns current and current summation circuit comprises second PMOS transistor, the 3rd PMOS transistor, the 4th PMOS transistor, the 5th PMOS transistor PMOS transistor, third NMOS transistor, fourth NMOS transistor, fifth NMOS transistor, sixth NMOS transistor, first resistor, second resistor, first operational amplifier and second operational amplifier, the source of the second PMOS transistor , the source of the third PMOS transistor, the source of the fourth PMOS transistor, and the source of the fifth PMOS transistor are all connected to the power supply terminal, and the gate of the second PMOS transistor is connected to the drain of the second PMOS transistor, the drain of the second PMOS transistor, and the source of the fifth PMOS transistor. The drains of the three NMOS transistors are connected to the gates of the third PMOS transistors, and the gates of the fifth PMOS transistors are respectively connected to the drains of the fifth PMOS transistors, the drains of the fourth NMOS transistors, and the gates of the fourth PMOS transistors. connected, the drain of the third PMOS transistor is respectively connected to the second input terminal of the sampling DC correction and sampling integration circuit and the drain of the fifth NMOS transistor, and the drain of the fourth PMOS transistor is respectively connected to the sixth NMOS transistor The drain of the sixth NMOS transistor is connected to the gate of the fifth NMOS transistor, the gate of the third NMOS transistor is connected to the output terminal of the first operational amplifier, and the sources of the third NMOS transistor are respectively It is connected with the first end of the first resistor and the inverting input end of the first operator, the non-inverting input end of the first operator is connected with the drain of the first PMOS transistor, and the gate of the fourth NMOS transistor is connected with the The output end of the second operational amplifier is connected, the source of the fourth NMOS transistor is respectively connected to the first end of the second resistor and the inverting input end of the second operational unit, and the non-inverting input end of the second operational unit is connected to the inverting input end of the second operational unit. The drain connection of the second NMOS transistor. 4. A kind of full-wave inductance current sampling circuit according to claim 3, is characterized in that: described sampling DC correction and sampling integration circuit comprise buffer, switch and sampling integration capacitor, the ratio MOS tube current sampling circuit The output end is connected to the input end of the buffer, and the output end of the buffer is connected to the first end of the sampling integration capacitor through the switch, and the first end of the sampling integration capacitor is connected to the drain of the third PMOS transistor. 5. a kind of full-wave inductive current sampling circuit according to claim 3 is characterized in that: described sampling direct current correction and sampling integration circuit comprise the 3rd operational amplifier, sampling integration capacitance, first electric capacity, second electric capacity, the first The third resistor, the fourth resistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor and the eleventh NMOS transistor, the The output terminal of the proportional MOS tube current sampling circuit is connected to the inverting input terminal of the third operational amplifier, and the output terminal of the third operational amplifier is respectively connected to the first terminal of the first capacitor and the gate of the seventh NMOS tube, so The output end of the third operational amplifier is connected to the first end of the second capacitor through the third resistor, and the source electrode of the sixth PMOS transistor, the source electrode of the seventh PMOS transistor and the source electrode of the eighth PMOS transistor are all connected to power supply end, the gate of the sixth PMOS transistor is connected to the drain of the sixth PMOS transistor and the drain of the seventh NMOS transistor respectively, and the gate of the seventh PMOS transistor is respectively connected to the drain of the seventh PMOS transistor, The gate of the eighth PMOS transistor is connected to the drain of the eighth NMOS transistor, the source of the seventh NMOS transistor is respectively connected to the first end of the fourth resistor and the drain of the ninth NMOS transistor, and the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor. The source of the NMOS transistor is respectively connected to the second end of the fourth resistor and the drain of the tenth NMOS transistor, the gate of the ninth NMOS transistor, the gate of the tenth NMOS transistor and the gate of the eleventh NMOS transistor are connected to the bias voltage end, and the non-inverting input end of the third operational amplifier is respectively connected to the drain of the eighth PMOS transistor, the drain of the eleventh NMOS transistor, the first end of the sampling integration capacitor, and the third PMOS transistor. connected to the drain.