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CN105762127A - 封装基板、半导体封装件及其制法 - Google Patents

封装基板、半导体封装件及其制法 Download PDF

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Publication number
CN105762127A
CN105762127A CN201410791135.4A CN201410791135A CN105762127A CN 105762127 A CN105762127 A CN 105762127A CN 201410791135 A CN201410791135 A CN 201410791135A CN 105762127 A CN105762127 A CN 105762127A
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Prior art keywords
line layer
packaging
base plate
electric connection
support plate
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CN105762127B (zh
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孙铭成
林俊贤
沈子杰
邱士超
白裕呈
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract

一种封装基板、半导体封装件及其制法，该封装基板包括：具有相对的第一表面及第二表面的绝缘层；嵌埋于该绝缘层中并由该第一表面所外露出且具有多个第一电性连接垫的第一线路层；嵌埋于该绝缘层中并由该第二表面所外露出且具有多个第二电性连接垫的第二线路层；形成于该第一表面上以电性连接该第一线路层的第三线路层；分别对应形成于各该第一电性连接垫上的多个第一金属凸部；以及竖埋于该绝缘层中以电性连接该第二线路层和第三线路层的至少一导电通孔。本发明能进一步缩小第一电性连接垫的面积并防止第一电性连接垫与导电凸块上的焊料之间发生不沾钖(non-wetting)的问题。

Description

封装基板、半导体封装件及其制法
技术领域
本发明提供一种封装基板、半导体封装件及其制法，尤指一种提升覆晶接合强度的封装基板、半导体封装件及其制法。
背景技术
随着提高电子产品功能的需求，对具有与芯片覆晶接合的密集电性连接垫的封装基板的制造技术的要求也不断提高，遂产生了各种封装基板的制造技术。
请参照图1，其为现有的封装基板1的剖视图。封装基板1包括绝缘层15、第一线路层11、第二线路层12、导电通孔13及第三电性连接垫18。
如上所述的绝缘层15具有相对的第一表面15a及第二表面15b，而该第一线路层11具有嵌设于该第一表面15a并由该第一表面15a露出的第一电性连接垫111，该第二线路层12具有嵌设于该第二表面15b并由该第二表面15b露出的第二电性连接垫121及导电垫122，且该绝缘层15中形成有导电通孔13以电性连接该导电垫122，另该第一表面15a上形成有第三电性连接垫18以电性连接该导电通孔13，而可选择地，在该导电垫122与该导电通孔13之间及该绝缘层15与该导电通孔13之间则可形成有导电层16。
然而，由于芯片功能不断增强，故与封装基板覆晶接合所须的电性接点的数目也不断提高，而在轻薄化电子产品的要求下，有限的电性接点分布面积及不断提高的电性接点的数目自然造成与芯片覆晶接合的第一电性连接垫面积的缩小，而在现有的封装基板中，由于第一电性连接垫与芯片覆晶接合的表面为平面，故在缩小面积的第一电性连接垫与芯片覆晶接合时往往造成第一电性连接垫与芯片的导电凸块上的焊料之间的接合强度不足，并发生不沾钖(non-wetting)的问题，从而导致产品信赖度及良率大幅下降。
因此，如何避免上述现有技术中的种种问题，实为目前业界所急需解决的课题。
发明内容
有鉴于上述现有技术的缺失，本发明提供一种封装基板、半导体封装件及其制法，能进一步缩小第一电性连接垫的面积并防止第一电性连接垫与导电凸块上的焊料之间发生不沾钖(non-wetting)的问题。
本发明的封装基板，包括：具有相对的第一表面及第二表面的绝缘层；嵌埋于该绝缘层中并由该第一表面所外露出且具有多个第一电性连接垫的第一线路层；嵌埋于该绝缘层中并由该第二表面所外露出且具有多个第二电性连接垫的第二线路层；形成于该第一表面上以电性连接该第一线路层的第三线路层；分别对应形成于各该第一电性连接垫上的多个第一金属凸部；以及竖埋于该绝缘层中以电性连接该第二线路层和第三线路层的至少一导电通孔。
本发明并提供一种半导体封装件，包括：封装基板，其具有相对的第一表面及第二表面的绝缘层；嵌埋于该绝缘层中并由该第一表面所外露出且具有多个第一电性连接垫的第一线路层；嵌埋于该绝缘层中并由该第二表面所外露出且具有多个第二电性连接垫的第二线路层；形成于该第一表面上以电性连接该第一线路层的第三线路层；分别对应形成于各该第一电性连接垫上的多个第一金属凸部；及竖埋于该绝缘层中以电性连接该第二线路层和第三线路层的至少一导电通孔；覆晶设于该封装基板上的至少一半导体组件；以及形成于该封装基板上并包覆该半导体组件的封装胶体。
本发明又提供一种封装基板的制法，包括：准备第一载板和第二载板，该第一载板上形成有具多个第一电性连接垫的第一线路层，该第二载板上形成有具多个第二电性连接垫的第二线路层；在该第一线路层和第二线路层面对面的情况下，形成包覆该第一线路层和第二线路层的绝缘层，其中，该绝缘层具有相对的第一表面及第二表面；移除该第一载板和第二载板，以令该第一表面外露出该第一线路层，该第二表面外露出该第二线路层；以及于该第一表面上形成第三线路层，并对应于该第一电性连接垫上形成第一金属凸部，及于该绝缘层中形成电性连接该第二线路层和第三线路层的至少一导电通孔。
本发明另提供一种半导体封装件的制法，包括：准备第一载板和第二载板，该第一载板上形成有具多个第一电性连接垫的第一线路层，该第二载板上形成有具多个第二电性连接垫的第二线路层；在该第一线路层和第二线路层面对面的情况下，形成包覆该第一线路层和第二线路层的绝缘层，其中，该绝缘层具有相对的第一表面及第二表面；移除该第一载板和第二载板，以令该第一表面外露出该第一线路层，该第二表面外露出该第二线路层；以及于该第一表面上形成第三线路层，并对应于该第一电性连接垫上形成第一金属凸部，及于该绝缘层中形成电性连接该第二线路层和第三线路层的至少一导电通孔，以形成封装基板；于该封装基板上覆晶设置至少一半导体组件；以及于该封装基板上形成封装胶体，以包覆该半导体组件。
本发明的封装基板及其制法藉由形成在第一电性连接垫的露出表面上且投影面积小于露出的第一电性连接垫的投影面积的第一金属凸部而使之后覆晶接合于第一电性连接垫的芯片的导电凸块上的焊料能提升第一电性连接垫与导电凸块上的焊料之间的接合强度，进而可使第一电性连接垫能进一步缩小面积并防止第一电性连接垫与导电凸块上的焊料于覆晶接合时发生不沾钖(non-wetting)的问题，以提升产品信赖度及良率。
附图说明
图1为现有的封装基板的剖视图；
图2A至图2E为本发明的封装基板的制法的一实施例的剖视图，而图2A’-1及图2A’-2为本发明的封装基板的图2A制法的另一实施例的剖视图，且图2B-1及图2B-2为本发明的封装基板的图2B制法的另一实施例的剖视图；
图3为本发明的半导体封装件及其制法的剖视图；
图4A至图4E为本发明的封装基板的制法的另一实施例的剖视图；以及
图5为本发明的半导体封装件及其制法的另一实施例的剖视图。
主要组件符号说明
1、2封装基板
3半导体组件
3a作用面
3b非作用面
4封装胶体
11、21第一线路层
12、22第二线路层
13、23导电通孔
15、25绝缘层
15a、25a第一表面
15b、25b第二表面
16、26导电层
18第三电性连接垫
28第三线路层
24板体
24a第一载板
24b第二载板
25’绝缘材
27a第一金属凸部
27b第二金属凸部
31导电柱
32焊料
111、211第一电性连接垫
121、221第二电性连接垫
122、222导电垫
252通孔
H段差。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。本发明也可藉由其它不同的具体实施例加以施行或应用，本说明书中的各项细节也可基于不同观点与应用，在不悖离本发明的精神下进行各种修饰与变更。
请参照图2A至图2E，其为本发明的封装基板的制法的一实施例的剖视图。
如图2A所示，本发明的封装基板的制法为首先准备第一载板24a和第二载板24b，该第一载板24a上形成有具多个第一电性连接垫211的第一线路层21，该第二载板24b上形成有具多个第二电性连接垫221的第二线路层22。而该第一载板24a和第二载板24b的准备也可如图2A’-1般先提供一包括相互迭接的第一载板24a和第二载板24b的板体24，且于该第一载板24a上形成具多个第一电性连接垫211的第一线路层21，该第二载板24b上形成具多个第二电性连接垫221的第二线路层22，并接着分离该二载板，得到如图2A’-2般分离该第一载板24a和第二载板24b。
详而言之，在图2A’-1例子中，该板体24的该第一载板24a与第二载板24b之间可夹置有黏着层(未图示)以黏着该第一载板24a及第二载板24b，而在该板体24是由单一板体所构成的情况下，可裁切该板体24为该第一载板24a及第二载板24b。而该第二线路层22也可具有导电垫222，而其电性连接的细节为本技術領域的技術人員所熟知，在此不再赘述。
其次，如图2B至图2B-2所示，在该第一线路层21和第二线路层22面对面的情况下，形成包覆该第一线路层21和第二线路层22的绝缘层25，其中，该绝缘层25具有相对的第一表面25a及第二表面25b。
详而言之但非限定而言，形成绝缘层25的绝缘材25’除了绝缘材料，也可为用做介电材料、封装材料或其组合的材料，且形成绝缘层25的方式可因制程策略的不同而有以下非限制性实施例，例如，可在该第一载板24a和第二载板24b的至少一者上形成绝缘材25’，例如，如图2B所示，在该第一载板24a上形成绝缘材25’，再压合该第一载板24a和第二载板24b，以形成该绝缘层25，或者如图2B-1所示，可先提供一绝缘材25’，再于该第一线路层21和第二线路层22面对面的情况下，将该第一线路层21和第二线路层22压入该绝缘材25’，以形成该绝缘层25，又或者如图2B-2所示，于该第一线路层21和第二线路层22面对面的情况下，于该第一线路层21和第二线路层22之间填充绝缘材25’，以形成该绝缘层25。
接着，如图2C所示，移除该该第一载板24a和第二载板24b，以令该第一表面25a外露出该第一线路层21，该第二表面25b外露出该第二线路层22。
此外，如图2D所示，在该绝缘层25中由该第一表面25a侧形成露出该第二线路层22的导电垫222的通孔252，而可选择地，可在该通孔252中、由该通孔252露出的该导电垫222上及该第一表面25a上形成导电层26。
最后，如图2E所示，于该绝缘层25中形成电性连接该第二线路层22的至少一导电通孔23，及于该第一表面25a上形成电性连接该导电通孔23的第三线路层28，并对应于该第一电性连接垫211上形成第一金属凸部27a，以形成本发明的封装基板2。而各该第一金属凸部27a在该第一表面25a上的投影面积小于该第一电性连接垫211的面积。另外，值得注意的是，该第三线路层28电性连接该第一金属凸部27a或第一线路层21，而该第三线路层28电性连接该第一金属凸部27a或第一线路层21的方式可依设计而改变，而其细节为本技術領域的技術人員可依设计而实施，在此不再赘述。
详而言之但非限制而言，在形成该导电通孔23及第一金属凸部27a之前，可以阻层(未图示)遮蔽不欲形成该导电通孔23及第一金属凸部27a处的该导电层26，并于形成该导电通孔23及第一金属凸部27a后，移除未形成该导电通孔23及第一金属凸部27a处的该导电层26。而可选择地，本发明可于形成该第一金属凸部27a时，分别对应于各该第二电性连接垫221上形成第二金属凸部27b，且该第二金属凸部27b在该第二表面25b上的投影面积小于该第二电性连接垫221的面积，而该第二金属凸部27b与该第二电性连接垫221之间也形成有导电层26，其形成方式与该第一电性连接垫211和第一金属凸部27a之间的导电层26大同小异，不再赘述。
本发明还提供一种封装基板2，其一实施例如图2E所示，该封装基板2包括：具有相对的第一表面25a及第二表面25b的绝缘层25、嵌埋于该绝缘层25中并由该第一表面25a所外露出且具有多个第一电性连接垫211的第一线路层21、嵌埋于该绝缘层25中并由该第二表面25b所外露出且具有多个第二电性连接垫221的第二线路层22、形成于该第一表面25a上以电性连接该第一线路层21的第三线路层28、分别对应形成于各该第一电性连接垫211上的多个第一金属凸部27a以及竖埋于该绝缘层25中以电性连接该第二线路层22和第三线路层28的至少一导电通孔23。并且，各该第一金属凸部27a在该第一表面25a上的投影面积小于该第一电性连接垫211的面积，而该导电通孔23延伸至该第一表面25a，并与该第一表面25a共平面。另外，本发明的封装基板2还包括多个第二金属凸部27b，其分别对应形成于各该第二电性连接垫221上，且各该第二金属凸部27b在该第二表面25b上的投影面积小于该第二电性连接垫221的面积。
请参照图3，其为本发明的半导体封装件及其制法的剖视图。本发明的半导体封装件为于如图2E所示的封装基板2上覆晶设置至少一半导体组件3，并于该封装基板2上形成包覆该半导体组件3的封装胶体4。
详而言之但非限定而言，该半导体组件3具有作用面3a及非作用面3b，且该作用面3a上可具有导电柱31及导电柱31上的焊料32，而可选择地，该半导体组件3可以回焊方式而使该焊料32包覆该第一金属凸部27a，以令该半导体组件3覆晶设于该封装基板2的第一表面25a，进而形成如图3所示的半导体封装件，或者，该半导体组件3可以回焊方式而使该焊料32包覆该第二金属凸部27b，以令该半导体组件3覆晶设于该封装基板2的第二表面25b(未图示此情况)。
请参照图4A至图4E，其为本发明的封装基板的制法的另一实施例的剖视图，基于该第一线路层21和第二线路层22若由电镀形成，该第一载板24a表面和第二载板24b表面皆可先形成导电层26，而该第一线路层21和第二线路层22形成于该导电层26上，故于如图4C所示般移除该第一载板24a和第二载板24b后，图4C与图2C的差异在于再移除该导电层26，且于移除该导电层26时可移除一部分外露的该第一线路层21，而于移除该导电层26时也可移除一部分外露的该第二线路层22，故外露的该第一线路层21的表面与该第一表面25a可具有段差H，而外露的该第二线路层22的表面与该第二表面25b也可具有段差H。也就是，该外露的该第一线路层21的表面可与该第一表面25a构成凹部，外露的该第二线路层22的表面也可与该第二表面25b构成凹部。其余制法与图2B、图2D及图2E所示者大同小异，不再赘述。另外，如图4E所示的本发明的封装基板2的另一实施例与图2E所示者的差异也在于外露的该第一线路层21的表面与该第一表面25a可具有段差H，且外露的该第二线路层22的表面与该第二表面25b也可具有段差H。而该第一金属凸部27a及第二金属凸部27b的高度皆分别突出第一表面25a和第二表面25b。
请参照图5，其为本发明的半导体封装件及其制法的另一实施例的剖视图，其与图3的差异也在于外露的该第一线路层21的表面可与该第一表面25a具有段差H，且外露的该第二线路层22的表面也可与该第二表面25b具有段差H。
综上所述，相较于先前技术，由于本发明藉由形成在第一电性连接垫(或第二电性连接垫)的露出表面上且投影面积小于露出的第一电性连接垫(或第二电性连接垫)的投影面积的第一金属凸部(或第二金属凸部)，而使之后覆晶接合于第一电性连接垫的半导体组件的导电凸块上的焊料能同时与第一电性连接垫及第一金属凸部的露出表面接合，或者使之后覆晶接合于第二电性连接垫的半导体组件的导电凸块上的焊料能同时与第二电性连接垫及第二金属凸部的露出表面接合，从而提升导电凸块上的焊料与第一电性连接垫或第二电性连接垫之间的接合强度，进而可使第一电性连接垫或第二电性连接垫能进一步缩小面积并防止导电凸块上的焊料与第一电性连接垫或第二电性连接垫于覆晶接合时发生不沾钖(non-wetting)的问题，以提升产品信赖度及良率。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (31)

1.一种封装基板，其特征为，包括：
绝缘层，其具有相对的第一表面及第二表面；
第一线路层，其嵌埋于该绝缘层中，且该第一表面外露出该第一线路层，其中，该第一线路层具有多个第一电性连接垫；
第二线路层，其嵌埋于该绝缘层中，且该第二表面外露出该第二线路层，其中，该第二线路层具有多个第二电性连接垫；
第三线路层，其形成于该第一表面上，以电性连接该第一线路层；
多个第一金属凸部，其分别对应形成于各该第一电性连接垫上；以及
至少一导电通孔，其竖埋于该绝缘层中，以电性连接该第二线路层和第三线路层。
2.如权利要求1所述的封装基板，其特征为，各该第一金属凸部在该第一表面上的投影面积小于该第一电性连接垫的面积。
3.如权利要求1所述的封装基板，其特征为，外露的该第一线路层的表面与该第一表面具有段差。
4.如权利要求1所述的封装基板，其特征为，外露的该第二线路层的表面与该第二表面具有段差。
5.如权利要求1所述的封装基板，其特征为，该导电通孔，其延伸至该第一表面，并与该第一表面共平面。
6.如权利要求1所述的封装基板，其特征为，该封装基板还包括多个第二金属凸部，其分别对应形成于各该第二电性连接垫上。
7.如权利要求6所述的封装基板，其特征为，各该第二金属凸部在该第二表面上的投影面积小于该第二电性连接垫的面积。
8.一种半导体封装件，其包括：
如权利要求1所述的封装基板；
至少一半导体组件，其覆晶设于该封装基板上；以及
封装胶体，其形成于该封装基板上，并包覆该半导体组件。
9.如权利要求8所述的半导体封装件，其特征为，该半导体组件覆晶设于该封装基板的第一表面。
10.如权利要求9所述的半导体封装件，其特征为，该半导体组件具有焊料，以藉其包覆该第一金属凸部。
11.如权利要求8所述的半导体封装件，其特征为，该半导体组件覆晶设于该封装基板的第二表面。
12.如权利要求11所述的半导体封装件，其特征为，该封装基板还包括分别对应形成于各该第二电性连接垫上的多个第二金属凸部，且该半导体组件具有焊料，以藉其包覆该第二金属凸部。
13.如权利要求12所述的半导体封装件，其特征为，各该第二金属凸部在该第二表面上的投影面积小于该第二电性连接垫的面积。
14.如权利要求8所述的半导体封装件，其特征为，各该第一金属凸部在该第一表面上的投影面积小于该第一电性连接垫的面积。
15.如权利要求8所述的半导体封装件，其特征为，外露的该第一线路层的表面与该第一表面具有段差。
16.如权利要求8所述的半导体封装件，其特征为，外露的该第二线路层的表面与该第二表面具有段差。
17.如权利要求8所述的半导体封装件，其特征为，该导电通孔，其延伸至该第一表面，并与该第一表面共平面。
18.一种封装基板的制法，其特征为，该制法包括：
准备第一载板和第二载板，该第一载板上形成有具多个第一电性连接垫的第一线路层，该第二载板上形成有具多个第二电性连接垫的第二线路层；
在该第一线路层和第二线路层面对面的情况下，形成包覆该第一线路层和第二线路层的绝缘层，其中，该绝缘层具有相对的第一表面及第二表面；
移除该第一载板和第二载板，以令该第一表面外露出该第一线路层，该第二表面外露出该第二线路层；
于该绝缘层中形成电性连接该第二线路层的至少一导电通孔；以及
于该第一表面上形成电性连接该导电通孔的第三线路层，并对应于该第一电性连接垫上形成第一金属凸部。
19.如权利要求18所述的封装基板的制法，其特征为，该第一载板和第二载板的准备包括：
提供一包括相互迭接的第一载板和第二载板的板体；
于该该第一载板上形成具多个第一电性连接垫的第一线路层，该第二载板上形成具多个第二电性连接垫的第二线路层；以及
分离该第一载板和第二载板。
20.如权利要求18所述的封装基板的制法，其特征为，该第一载板表面和第二载板表面皆具有导电层，该第一线路层和第二线路层形成于该导电层上，且于移除该第一载板和第二载板后，外露的该第一线路层的表面与该第一表面具有段差，外露的该第二线路层的表面与该第二表面具有段差。
21.如权利要求18所述的封装基板的制法，其特征为，形成该绝缘层的方式包括在该第一载板和第二载板的至少一者上形成绝缘材，再压合该第一载板和第二载板，以形成该绝缘层。
22.如权利要求18所述的封装基板的制法，其特征为，形成该绝缘层的方式包括提供一绝缘材，再于该第一线路层和第二线路层面对面的情况下，将该第一线路层和第二线路层压入该绝缘材，以形成该绝缘层。
23.如权利要求18所述的封装基板的制法，其特征为，形成该绝缘层的方式包括于该第一线路层和第二线路层面对面的情况下，于该第一线路层和第二线路层之间填充绝缘材，以形成该绝缘层。
24.如权利要求18所述的封装基板的制法，其特征为，各该第一金属凸部在该第一表面上的投影面积小于该第一电性连接垫的面积。
25.如权利要求18所述的封装基板的制法，其特征为，该制法还包括于形成该第一金属凸部时，分别对应于各该第二电性连接垫上形成第二金属凸部。
26.如权利要求25所述的封装基板的制法，其特征为，各该第二金属凸部在该第二表面上的投影面积小于该第二电性连接垫的面积。
27.一种半导体封装件的制法，其特征为，该制法包括：
于如权利要求18的封装基板上覆晶设置至少一半导体组件；以及
于该封装基板上形成封装胶体，以包覆该半导体组件。
28.如权利要求27所述的半导体封装件的制法，其特征为，该半导体组件覆晶设于该封装基板的第一表面。
29.如权利要求28所述的半导体封装件的制法，其特征为，该半导体组件具有焊料，以藉其包覆该第一金属凸部。
30.如权利要求27所述的半导体封装件的制法，其特征为，该半导体组件覆晶设于该封装基板的第二表面。
31.如权利要求30所述的半导体封装件的制法，其特征为，该封装基板还包括分别对应形成于各该第二电性连接垫上的多个第二金属凸部，且该半导体组件具有焊料，以藉其包覆该第二金属凸部。
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