CN105655352B - The production method of low temperature polycrystalline silicon tft array substrate - Google Patents

Abstract

The invention provides a method for manufacturing a low-temperature polysilicon TFT array substrate, which completely removes the cured photoresist remaining after ion doping through two consecutive photoresist ashing and photoresist removal treatments, effectively solving the problem of photoresist layer Before the first ashing process, some areas may be covered with impurity particles to block the problem of cured photoresist residue caused by the first ashing process, which can improve the cleanliness of the interface between the gate insulating layer and the interlayer insulating layer, and avoid interface problems Resulting in a decline in product yield.

Description

Manufacturing method of low-temperature polysilicon TFT array substrate

technical field

The invention relates to the field of display technology, in particular to a method for manufacturing a low-temperature polysilicon TFT array substrate.

Background technique

Thin Film Transistor (TFT) is the main driving element in current Liquid Crystal Display (LCD) and Active Matrix Organic Light-Emitting Diode (AMOLED). It is related to the display performance of the flat panel display device.

Thin film transistors have various structures, and there are also various materials for preparing thin film transistors with corresponding structures. Low Temperature Polysilicon (LTPS) material is one of the more preferred materials. Due to the regular arrangement of atoms of low temperature polysilicon, the current carrying High sub-mobility. For voltage-driven liquid crystal display devices, low-temperature polysilicon thin-film transistors can use smaller thin-film transistors to drive deflection of liquid crystal molecules due to their high mobility. The volume occupied by thin-film transistors is reduced, the light-transmitting area is increased, and higher brightness and resolution are obtained; for current-driven active matrix-driven organic electroluminescent display devices, low-temperature polysilicon thin-film transistors can be better Meet the drive current requirements.

Both LCD and AMOLED include a TFT array substrate.

The manufacturing process of the existing low-temperature polysilicon TFT array substrate is usually as follows: on the substrate, from bottom to top, a light-shielding layer, an insulating buffer layer, a low-temperature polysilicon semiconductor layer, a gate insulating layer, a gate, an interlayer insulating layer, a source /drain, planarization layer, bottom electrode, protective layer, and top electrode. Wherein, the low-temperature polysilicon semiconductor layer further includes a channel region in the middle corresponding to the gate, and ion-doped regions at both ends corresponding to the source/drain.

The specific process of making the ion-doped region is as follows: first, apply photoresist on the low-temperature polysilicon layer, then expose, develop, and bake the photoresist to obtain a patterned photoresist layer to expose the two ends of the low-temperature polysilicon layer ; Then, using the photoresist layer as a shielding layer, ion doping is performed on both ends of the low-temperature polysilicon layer; followed by photoresist ashing and photoresist removal. During this process, some areas of the photoresist layer may be covered with impurity particles, which prevent the ashing of the photoresist layer, resulting in the inability to completely remove the photoresist layer, resulting in residual cured photoresist, which in turn affects the subsequent gate insulating layer. 1. The interface quality of the interlayer insulating layer will cause problems such as peeling and cracking of the gate insulating layer and the interlayer insulating layer, which will eventually lead to a decline in product quality.

At present, the existing measures to improve the interface between the gate insulating layer and the interlayer insulating layer include: changing the cleaning conditions or performing plasma treatment before film formation, but these measures have limited effects and ignore the photoresist layer used due to ion doping Some areas may be covered with impurity particles before the ashing process, resulting in the problem of cured photoresist residue.

Contents of the invention

The purpose of the present invention is to provide a method for manufacturing a low-temperature polysilicon TFT array substrate, which can completely remove the cured photoresist remaining after ion doping, improve the cleanliness of the interface between the gate insulating layer and the interlayer insulating layer, and avoid interface problems. Product yield drops.

In order to achieve the above object, the present invention provides a method for manufacturing a low-temperature polysilicon TFT array substrate, comprising the following steps:

Step 1. Provide a base substrate, form a patterned light-shielding layer on the base substrate, and deposit a covering insulating buffer layer on the light-shielding layer and the base substrate;

Step 2, forming a patterned low-temperature polysilicon layer corresponding to the light-shielding layer on the insulating buffer layer;

Step 3, coating a photoresist material on the low-temperature polysilicon layer and the buffer layer, patterning the photoresist material to form a photoresist layer, and exposing at least part of both end regions of the low-temperature polysilicon layer;

Step 4, using the photoresist layer as a shielding layer, performing one type of ion doping on both end regions of the corresponding low-temperature polysilicon layer to form a low-temperature polysilicon semiconductor layer;

Step 5, performing the first photoresist ashing and photoresist removal treatment;

Step 6, performing a second photoresist ashing and photoresist removal treatment to completely remove the photoresist layer;

Step 7, sequentially fabricating a gate insulating layer, a gate, an interlayer insulating layer, a source/drain, a flat layer, a bottom electrode, a protective layer, and a top electrode on the low-temperature polysilicon semiconductor layer and the insulating buffer layer.

The step 7 further includes coating and patterning a photoresist material on the gate and the gate insulation layer to form another photoresist layer, using the other photoresist layer as a shielding layer, Perform another type of ion doping to the two end regions of the remaining low-temperature polysilicon layer that has not been ion-doped in step 4 to form a low-temperature polysilicon semiconductor layer, and two consecutive photoresist ashing and photoresist removal processes process, and then fabricate the interlayer insulating layer.

The specific manufacturing process of the patterned low-temperature polysilicon layer in the step 2 is as follows: first deposit a layer of amorphous silicon on the insulating buffer layer, then carry out crystallization treatment on the amorphous silicon to obtain low-temperature polysilicon, and then pass light to A patterned low-temperature polysilicon layer is obtained through the engraving process.

In the step 3, the photoresist material is patterned by exposing and developing processes to obtain the photoresist layer.

One type of ion doping described in step 4 is N-type ion doping of doping phosphorus ions or P-type ion doping of doping boron ions; another type of ion doping described in step 7 is It is different from P-type ion doping or N-type ion doping in step 4.

The source/drain are in contact with both ends of the low temperature polysilicon semiconductor layer through via holes penetrating through the interlayer insulating layer and the gate insulating layer respectively.

The insulating buffer layer, the gate insulating layer, the interlayer insulating layer, the flat layer and the protective layer are all made of one or a combination of silicon oxide and silicon nitride.

The top electrode is in contact with the drain through a via hole penetrating through the protection layer, the bottom electrode, and the planar layer.

The materials of the top electrode and the bottom electrode are both ITO.

Beneficial effects of the present invention: the manufacturing method of a low-temperature polysilicon TFT array substrate provided by the present invention completely removes the cured photoresist remaining after ion doping through two consecutive photoresist ashing and photoresist removal treatments, effectively solving the problem of photoresist Before the first ashing process, some areas of the resist layer may be covered with impurity particles to block the problem of cured photoresist residue caused by the first ashing process, which can improve the cleanliness of the interface between the gate insulating layer and the interlayer insulating layer , to avoid the decline in product yield caused by interface problems.

Description of drawings

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and accompanying drawings of the present invention. However, the accompanying drawings are provided for reference and illustration only, and are not intended to limit the present invention.

In the attached picture,

Fig. 1 is the flowchart of the manufacturing method of the low-temperature polysilicon TFT array substrate of the present invention;

Fig. 2 is the schematic diagram of step 1 of the manufacturing method of the low-temperature polysilicon TFT array substrate of the present invention;

Fig. 3 is the schematic diagram of step 2 of the manufacturing method of the low-temperature polysilicon TFT array substrate of the present invention;

4 is a schematic diagram of step 3 of the manufacturing method of the low-temperature polysilicon TFT array substrate of the present invention;

5 is a schematic diagram of step 4 of the manufacturing method of the low-temperature polysilicon TFT array substrate of the present invention;

6 is a schematic diagram of step 5 of the method for manufacturing a low-temperature polysilicon TFT array substrate of the present invention;

7 is a schematic diagram of step 6 of the method for manufacturing a low-temperature polysilicon TFT array substrate of the present invention;

FIG. 8 is a schematic diagram of step 7 of the manufacturing method of the low-temperature polysilicon TFT array substrate of the present invention.

Detailed ways

In order to further illustrate the technical means adopted by the present invention and its effects, the following describes in detail in conjunction with preferred embodiments of the present invention and accompanying drawings.

Referring to Fig. 1, the present invention provides a method for manufacturing a low-temperature polysilicon TFT array substrate, comprising the following steps:

Step 1. As shown in FIG. 2 , a base substrate 10 is provided, a patterned light-shielding layer 11 is formed on the base substrate 10 , and a covering insulating buffer layer 12 is deposited on the light-shielding layer 11 and the base substrate 10 .

Specifically, the base substrate 10 is preferably a glass substrate; the material of the light-shielding layer 11 is an opaque metal; the material of the insulating buffer layer 12 is silicon oxide (SiOx), silicon nitride (SiNx) Preferably, the insulating buffer layer 12 includes a silicon nitride layer and a silicon oxide layer stacked from bottom to top.

Step 2, as shown in FIG. 3 , forming a patterned low temperature polysilicon layer 20 corresponding to the light shielding layer 11 on the insulating buffer layer 12 .

Specifically, the detailed process of step 2 is: first deposit a layer of amorphous silicon on the insulating buffer layer 12, and then pass Excimer Laser Annealing (ELA) or solid phase crystallization (Solid Phase Crystallization, SPC ) and other methods to crystallize the amorphous silicon to convert the amorphous silicon into low-temperature polysilicon, and then obtain the patterned low-temperature polysilicon layer 20 through a photolithography process.

Step 3, as shown in FIG. 4 , coat a photoresist material on the low-temperature polysilicon layer 20 and the insulating buffer layer 12, and pattern the photoresist material through exposure and development processes to form a photoresist layer 30, exposing at least Two end regions of part of the low temperature polysilicon layer 20 .

It is worth mentioning that if the final low-temperature polysilicon TFT array substrate is designed to only include N-type or P-type single-type TFTs, the patterned photoresist layer 30 in step 3 should expose all of the low-temperature polysilicon layer 20. Regions at both ends; if the final low-temperature polysilicon TFT array substrate is designed to include both N-type TFTs and P-type TFTs, then the patterned photoresist layer 30 in step 3 should expose part of the two-end regions of the low-temperature polysilicon layer 20 .

Step 4, as shown in FIG. 5 , using the photoresist layer 30 as a shielding layer, perform one type of ion doping on the two end regions of the corresponding low-temperature polysilicon layer 20 to form a low-temperature polysilicon semiconductor layer 20 ′, in which the ion doping The doped region becomes the source/drain contact region of the polysilicon semiconductor layer 20 ′, and the region not doped with ions becomes the channel region of the polysilicon semiconductor layer 20 ′.

It is worth mentioning that if the final low-temperature polysilicon TFT array substrate is designed to only include N-type TFTs, one type of ion doping described in step 4 is N-type ion doping with phosphorus (P) ions. impurity; if the low-temperature polysilicon TFT array substrate that finally makes is designed to only include P-type TFTs, then a type of ion doping described in step 4 is P-type ion doping of boron (B) ions; if the design The finally obtained low-temperature polysilicon TFT array substrate includes both N-type TFTs and P-type TFTs, and one type of ion doping described in step 4 is one of N-type ion doping and P-type ion doping. kind.

It can be seen from FIG. 5 that the ion doping process in Step 4 will cause impurity particles to cover certain areas of the photoresist layer 30 .

Step 5, performing the first photoresist ashing and photoresist removal treatment.

As shown in FIG. 6, after the first photoresist ashing and photoresist removal treatment in step 5, the impurity particles generated in the above step 4 and the part of the photoresist layer 30 not covered by the impurity particles will be removed, but The region of the photoresist layer 30 covered by the impurity particles will remain cured photoresist because the impurity particles block the ashing of the photoresist.

Step 6, performing a second photoresist ashing and photoresist removal treatment.

As shown in FIG. 7 , performing photoresist ashing and photoresist removal treatment again in step 6 can remove the cured photoresist remaining after the first photoresist ashing and photoresist removal treatment, thereby completely removing the photoresist layer 30 , It provides a clean interface for the subsequent film formation of the gate insulating layer, and avoids peeling and cracking of the gate insulating layer due to interface problems.

Step 7, as shown in FIG. 8 , sequentially fabricate a gate insulating layer 31 , a gate 41 , an interlayer insulating layer 32 , a source/drain 42 , and a flat layer on the low-temperature polysilicon semiconductor layer 20 ′ and the insulating buffer layer 12 50 , a bottom electrode 60 , a protection layer 70 , and a top electrode 80 .

It is worth mentioning that if the design of the final low-temperature polysilicon TFT array substrate only includes N-type TFTs or P-type TFTs, then step 7 only needs to fabricate the above-mentioned film layers in sequence; if the design of the final low-temperature polysilicon TFT The array substrate includes both N-type TFTs and P-type TFTs. After the gate 41 is fabricated in step 7, coating and patterning a photoresist material on the gate 41 and the gate insulating layer 31 to form another The photoresist layer, using the other photoresist layer as a shielding layer, performs another type of ion doping on the two end regions of the remaining low-temperature polysilicon layer 20 that has not been ion-doped in step 4 to form a low-temperature polysilicon semiconductor Layer, and two consecutive photoresist ashing and photoresist removal processes provide a clean interface for the subsequent film formation of the interlayer insulating layer 32, avoiding interface problems that cause peeling and cracks in the interlayer insulating layer 32, and then The interlayer insulating layer 32 is fabricated again. Further, if the N-type ion doping is carried out in the step 4, then the P-type ion doping is carried out in the step 7; if the P-type ion doping is carried out in the step 4, then in the step 7 Perform N-type ion doping.

Specifically, the source/drain 42 is in contact with both ends of the low temperature polysilicon semiconductor layer 20' through via holes penetrating the interlayer insulating layer 32 and the gate insulating layer 31 respectively.

The top electrode 80 is in contact with the drain through the via hole 81 penetrating through the passivation layer 70 , the bottom electrode 60 , and the planar layer 50 .

The materials of the gate insulating layer 31 , the interlayer insulating layer 32 , the planar layer 50 , and the protection layer 70 are all one of silicon oxide and silicon nitride or a combination of the two.

The materials of the top electrode 80 and the bottom electrode 60 are both Indium Tin Oxide (ITO).

In summary, the manufacturing method of the low-temperature polysilicon TFT array substrate of the present invention completely removes the cured photoresist remaining after ion doping through two consecutive photoresist ashing and photoresist removal treatments, effectively solving the problem of photoresist layer Before the first ashing process, some areas may be covered with impurity particles to block the problem of cured photoresist residue caused by the first ashing process, which can improve the cleanliness of the interface between the gate insulating layer and the interlayer insulating layer, and avoid interface problems Resulting in a decline in product yield.

As mentioned above, for those of ordinary skill in the art, various other corresponding changes and deformations can be made according to the technical scheme and technical concept of the present invention, and all these changes and deformations should belong to the protection scope of the claims of the present invention .

Claims (8)

1. A method for manufacturing a low-temperature polysilicon TFT array substrate, characterized in that, comprising the steps: Step 1. Provide a base substrate (10), form a patterned light-shielding layer (11) on the base substrate (10), and deposit a covering layer on the light-shielding layer (11) and the base substrate (10). Insulating buffer layer (12); Step 2, forming a patterned low-temperature polysilicon layer (20) corresponding to the light shielding layer (11) on the insulating buffer layer (12); Step 3, coating a photoresist material on the low temperature polysilicon layer (20) and the insulating buffer layer (12), patterning the photoresist material to form a photoresist layer (30), exposing at least part of the low temperature polysilicon layer ( 20) both end regions; Step 4, using the photoresist layer (30) as a shielding layer, performing a type of ion doping on the two end regions of the corresponding low-temperature polysilicon layer (20) to form a low-temperature polysilicon semiconductor layer (20'); Step 5, performing the first photoresist ashing and photoresist removal treatment; Step 6, performing a second photoresist ashing and photoresist removal treatment to completely remove the photoresist layer (30); Step 7, sequentially fabricate a gate insulating layer (31), a gate (41), an interlayer insulating layer (32), and a source/drain on the low-temperature polysilicon semiconductor layer (20') and the insulating buffer layer (12) (42), flat layer (50), bottom electrode (60), protective layer (70), and top electrode (80); The insulating buffer layer (12), the gate insulating layer (31), the interlayer insulating layer (32), the flat layer (50), and the protective layer (70) are all made of silicon oxide or silicon nitride. one or a combination of two. 2. the manufacture method of low-temperature polysilicon TFT array substrate as claimed in claim 1, is characterized in that, described step 7 also comprises after gate (41) is made, after gate (41) and gate insulating layer ( 31) Coating and patterning a photoresist material on top to form another photoresist layer, using the other photoresist layer as a shielding layer, for the remaining low-temperature polysilicon layer (20) that has not been ion-doped in step 4 Another type of ion doping is performed on the regions at both ends to form a low-temperature polysilicon semiconductor layer (20'), and two consecutive photoresist ashing and photoresist removal processes are performed, and then the interlayer insulating layer ( 32). 3. the manufacturing method of low-temperature polysilicon TFT array substrate as claimed in claim 1, is characterized in that, the specific manufacturing process of the patterned low-temperature polysilicon layer (20) in the described step 2 is: first in the described insulating buffer layer ( 12) Deposit a layer of amorphous silicon on it, and then crystallize the amorphous silicon to produce low-temperature polysilicon, and then obtain a patterned low-temperature polysilicon layer (20) through a photolithography process. 4. The method for manufacturing a low-temperature polysilicon TFT array substrate according to claim 1, characterized in that, in said step 3, said photoresist layer (30) is obtained by patterning said photoresist material through exposure and development processes. 5. The manufacturing method of low-temperature polysilicon TFT array substrate as claimed in claim 2, is characterized in that, one type of ion doping described in step 4 is N-type ion doping or doping boron doped with phosphorus ions P-type ion doping of ions; another type of ion doping described in step 7 is P-type ion doping or N-type ion doping different from step 4. 6. the manufacture method of low-temperature polysilicon TFT array substrate as claimed in claim 1 is characterized in that, described source/drain (42) passes through interlayer insulating layer (32) and gate insulating layer (31) respectively The via holes are in contact with both ends of the low temperature polysilicon semiconductor layer (20'). 7. The method for manufacturing a low-temperature polysilicon TFT array substrate as claimed in claim 1, wherein the top layer electrode (80) passes through the protection layer (70), the bottom electrode (60), and the flat layer (50). ) via hole (81) is in contact with the drain. 8. The method for manufacturing a low-temperature polysilicon TFT array substrate according to claim 1, characterized in that the materials of the top electrode (80) and the bottom electrode (60) are both ITO.