CN103022145A - Array substrate, display device and preparation method - Google Patents

Abstract

The invention discloses an array substrate, a display device and a preparation method, and relates to the field of display technology. The array substrate includes: a substrate, a polysilicon layer, a gate insulating layer, and a metal layer; the polysilicon layer is disposed above the substrate, and includes: a channel region and ion-doped regions on both sides of the channel region; The gate insulation layer is arranged above the polysilicon layer; the metal layer includes gate electrodes, source electrodes, drain electrodes, gate lines and data lines made of the same metal material. The present invention uses PR glue as the barrier layer instead of the gate electrode as the barrier layer for ion doping, which reduces the short channel effect caused by the diffusion of implanted dopant ions to the channel region, and also reduces the gate-source-drain The coupling capacitance between them improves the working performance of the TFT.

Description

Array substrate, display device and manufacturing method

technical field

The present invention relates to the field of display technology, in particular to an array substrate, a display device and a preparation method.

Background technique

Thin Film Transistor (TFT) can be divided into polysilicon (Poly-Si, P-Si) TFT and amorphous silicon (a-Si) TFT. The difference between the two lies in the characteristics of the transistor. The molecular structure of P-Si is neatly and directionally arranged in a grain (Grain), so the electron mobility is 200-300 times faster than that of disordered amorphous silicon. P-Si products mainly include high temperature polysilicon (HTPS) and low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) two products.

LTPS technology is a new generation of TFT display manufacturing process, mainly through excimer laser annealing (ELA), metal optimized crystallization (MIC) or solid phase crystallization (SPC) process to convert a-Si thin film into P-Si thin film layer. LTPS TFT display has faster response time and higher resolution, so it has better picture quality. Using the LTPS technology when forming the peripheral circuit of the display device can reduce the number of integrated circuits (ICs), simplify the periphery of the display device, and realize narrow frame technology.

As shown in Figure 1, a traditional LTPS TFT array substrate includes: a glass substrate 101, a buffer layer 102, a channel region (channel) 103, a gate insulating layer 105, a gate electrode 106, a source-drain electrode 104, an interlayer insulating layer 107, Passivation layer 108, pixel electrode layer 109, and pixel electrode insulating protection layer (PDL) 110 (this layer is suitable for LTPS AMOLED, if it is LTPS LCD, it may not have this layer). The preparation process of the traditional LTPS TFT array substrate is the 7Mask process, including:

The first Mask (polysilicon (P-Si) Mask): Form TFT source and drain regions and channel region patterns.

First, a buffer layer 102 of SiNx/SiO ₂ is formed on the glass substrate 101, and then a layer of amorphous silicon (a-Si) film is deposited on the buffer layer 102, and crystallized by LTPS (such as ELA, MIC, SPC etc.), transforming the amorphous silicon film into a polysilicon film. Then, coat a layer of PR glue on the polysilicon film, use the first Mask to expose the first TFT active layer pattern, develop after the exposure, etch the polysilicon film and print the PR glue after the development. After stripping, the channel region pattern 103 is formed.

The second Mask (gate metal layer Mask): used to form the gate electrode pattern 106 and the gate line pattern (not shown).

On the basis of the pattern formed by the first Mask, deposit a gate insulating layer film 105 and a gate metal layer film. The gate insulating layer film 105 can be SiO ₂ /SiNx, and then coat PR glue on the gate metal layer film, using the second Two masks are used for exposure, and then development, etching, and stripping complete the formation of the gate electrode pattern 106 and the gate line pattern.

On the basis of forming the pattern in the second mask, the gate electrode pattern on the channel region pattern 103 is used as a barrier layer for ion doping, and ion implantation (Ion Doping) in the source and drain regions is performed, as shown in Figure 2-1. After ion implantation, an ion-doped region 111 is formed in the source and drain regions. After the ion doping is completed, the original regular crystallized polysilicon lattice is destroyed by ion doping. In order to repair the polysilicon lattice, an annealing treatment is required. One is to play the role of polycrystalline silicon lattice reformation, the other is to play the role of dopant ion diffusion, as shown in Figure 2-2, during the annealing process, the dopant ions will diffuse toward the direction of the channel region 103 (as shown by the arrow), as shown in Figure 2-2. As shown in Figure 2-3.

The third Mask (Gate insulating layer via hole (GI Hole) Mask): Form the contact hole between the polysilicon in the source and drain regions and the source and drain electrodes.

A layer of interlayer insulating layer 107 is formed on the pattern after the second Mask is completed, and then a layer of PR glue is coated on the interlayer insulating layer 107, and the third mask is used to expose the source and drain electrode via holes, and the exposure After the development is finished, it is developed, and after the development is finished, it is etched and stripped of the PR glue.

The fourth Mask (source-drain metal layer Mask): used to form source-drain electrode patterns 104 and data lines (not shown).

On the basis of the patterning of the third Mask, deposit the source-drain metal layer film, and then apply PR glue on the metal layer film, and use the fourth Mask to perform exposure, development, etching, and stripping to complete the source-drain electrode pattern 104 and the formation of data lines.

The fifth Mask (PVX Hole Mask): used to form a bridging via hole bridging the source-drain electrode pattern 104

A passivation layer 108 is deposited on the basis of completing the pattern of the fourth mask, and a passivation layer via hole is formed on the passivation layer 108 by using the fifth mask.

The sixth mask (pixel electrode mask): after completing the pattern of the fifth mask, the pixel electrode layer film is deposited, and the sixth mask is used for exposure, development, etching and stripping to form the pixel electrode pattern 109 .

The seventh Mask (pixel electrode edge protection layer Mask): Deposit a layer of protective film on the basis of the sixth Mask pattern, and use the seventh Mask for exposure, development, etching and peeling to form pixel edge protection layer pattern. This Mask is suitable for LTPSAMOLED, if it is LTPS LCD, you can not use this Mask.

In the preparation process of the above-mentioned traditional LTPS TFT array substrate, the gate electrode is used as the barrier layer for ion implantation in the source and drain regions, and the implanted ions are adjacent to the channel region. When the ions are annealed in polysilicon, the dopant ions will partially diffuse to the channel region. The effective channel length (Channel Length) is reduced, the short channel effect of the channel region is obvious, and the coupling capacitance between the gate source and the drain is also increased, thereby reducing the TFT performance. In addition, the fabrication process of the structure in which the gate electrode and the gate line and the source-drain electrode and the data line are respectively located in two layers is complicated.

Contents of the invention

(1) Technical problems to be solved

The technical problem to be solved by the present invention is to provide an array substrate and a display device that can reduce the TFT short channel effect caused by the diffusion of doped implanted ions in the polysilicon layer to the channel region, reduce the number of Masks used, and simplify the process flow and preparation method.

(2) Technical solutions

In order to solve the above problems, the present invention provides an array substrate, comprising: a substrate, a polysilicon layer, a gate insulating layer and a metal layer;

The polysilicon layer is disposed above the substrate, including: a channel region and ion-doped regions on both sides of the channel region;

The gate insulating layer is disposed above the polysilicon layer;

It is characterized in that the metal layer includes gate electrodes, source electrodes, drain electrodes, gate lines and data lines made of the same metal material.

Further, the gate electrode is connected to the gate line;

The source and the drain are respectively connected to the ion-doped region through via holes on the gate insulating layer, and the drain is also connected to the data line.

Further, the gate line is disconnected at the intersection with the data line, and the disconnected gate line is connected through the connection electrode above the metal layer; or,

The data line is disconnected at the intersection with the gate line, and the disconnected data line is connected through the connection electrode above the metal layer.

Further, the array substrate further includes: a passivation layer; the passivation layer is disposed above the metal layer, and the connecting electrodes are connected to the disconnected gate lines or The disconnected data line.

Further, the array substrate further includes: a pixel electrode, and the pixel electrode and the connecting electrode are formed of the same layer of material.

Further, the pixel electrode is connected to the source electrode through a via hole on the passivation layer.

Further, the array substrate further includes: a pixel electrode edge protection layer disposed above the pixel electrode, the connection electrode and the passivation layer.

The present invention also provides a display device, comprising the above-mentioned array substrate.

The present invention also provides a method for preparing an array substrate, the method comprising the steps of:

S1. Forming a polysilicon layer pattern on the substrate, the polysilicon layer pattern including a channel region and ion-doped regions on both sides of the channel region;

S2. Forming a gate insulating layer pattern above the polysilicon layer pattern, and performing ion doping on the ion-doped region by coating PR glue above the channel region as a barrier layer;

S3. Forming a metal layer above the pattern of the gate insulating layer, and forming a pattern including a gate electrode, a source electrode, a drain electrode, a gate line and a data line on the metal layer.

Further, the step S2 also includes:

An annealing process is performed after the ion-doped region is ion-doped by coating PR glue on the channel region as a barrier layer.

Further, the step S3 specifically includes:

A metal layer is formed above the pattern of the gate insulating layer, and a pattern including a gate electrode, a source electrode, a drain electrode, a gate line and a data line is formed on the metal layer; the source electrode passes through the source electrode on the gate insulating layer The ion-doped region is connected to the via hole; the drain is connected to the ion-doped region through the drain via hole on the gate insulating layer; the gate electrode is connected to the gate line; the drain is connected to the The data line; the gate line is disconnected at the intersection with the data line, or, the data line is disconnected at the intersection with the gate line.

Further, the method also includes the steps of:

S4. Form a passivation layer above the metal layer, and form a via hole in the passivation layer, the via hole in the passivation layer is used to connect the pixel electrode and the source electrode, and connect the disconnected gate lines or the disconnected data lines.

Further, the method also includes the steps of:

S5. Form a pattern including a pixel electrode and a connection electrode on the passivation layer; the pixel electrode is connected to the source electrode through the via hole on the passivation layer; The via holes in the passivation layer are used to connect the disconnected gate lines, or the connecting electrodes are connected to the disconnected data lines through the via holes in the passivation layer.

Further, the method also includes the steps of:

S6. Forming a pixel electrode edge protection layer pattern on the pixel electrode, the connecting electrode and the passivation layer.

Further, the step S2 specifically includes the steps of:

S21: forming a gate insulating layer film on the polysilicon layer pattern, and coating PR glue on the gate insulating layer film;

S22: exposing and developing the PR glue above the ion-doped region, and then etching the gate insulating layer film to form source via holes and drain via holes;

S23: Perform ion doping in the ion-doped region by using the PR glue above the channel region as a barrier layer.

Alternatively, the step S2 specifically includes the steps of:

S21': forming a gate insulating layer film above the polysilicon layer pattern, and coating PR glue on the gate insulating layer film;

S22': exposing and developing the PR glue above the ion-doped region;

S23': using the PR glue above the channel region as a barrier layer to carry out ion doping in the ion-doped region;

S24': Etching the gate insulating layer film above the ion-doped region to form source via holes and drain via holes.

(3) Beneficial effects

The present invention uses PR glue as the barrier layer instead of the gate electrode as the barrier layer for ion doping, which reduces the short channel effect caused by the diffusion of implanted dopant ions to the channel region, and also reduces the gate-source-drain The coupling capacitance between them improves the working performance of the TFT. In addition, the use of the same layer electrode metal process reduces the number of Masks used and simplifies the preparation process.

Description of drawings

Figure 1 is a schematic structural diagram of the LTPS TFT array substrate prepared by the traditional 7Mask process;

Figure 2-1-Figure 2-3 is a partial schematic diagram of the traditional LTPS TFT array substrate preparation process;

FIG. 3-1 is a schematic plan view of an array substrate according to an embodiment of the present invention;

Figure 3-2 is a sectional view along the line A-A of Figure 3-1;

FIG. 4-1 to FIG. 4-4 are schematic diagrams of the manufacturing principle of an array substrate according to an embodiment of the present invention.

Detailed ways

The present invention provides an array substrate, including: a substrate, a polysilicon layer, a gate insulating layer and a metal layer. The polysilicon layer is disposed above the substrate and includes: a channel region and ion-doped regions on both sides of the channel region. The gate insulating layer is disposed above the polysilicon layer. The metal layer includes gate electrodes, source electrodes, drain electrodes, gate lines and data lines made of the same metal material.

Specifically, the gate electrode is connected to the gate line; the source and the drain are respectively connected to the ion-doped region through via holes on the gate insulating layer, and the drain is also connected to the data line.

Specifically, the gate line is disconnected at the intersection with the data line, and the disconnected gate line is connected through the connection electrode above the metal layer; or, the data line is disconnected, and the disconnected data line is connected through the connection electrode above the metal layer.

Further, the array substrate further includes: a passivation layer; the passivation layer is disposed above the metal layer, and the connecting electrodes are connected to the disconnected gate lines or The disconnected data line.

Further, the array substrate further includes: a pixel electrode, and the pixel electrode and the connecting electrode are formed of the same layer of material.

Further, the pixel electrode is connected to the source electrode through a via hole on the passivation layer.

Further, the array substrate further includes: a pixel electrode edge protection layer disposed above the pixel electrode, the connection electrode and the passivation layer.

In the array substrate of the embodiment of the present invention, since its metal layer includes gate electrodes, source electrodes, drain electrodes, gate lines and data lines made of the same metal material, the number of Masks used can be reduced, and its manufacturing process can be simplified.

The array substrate of the embodiment of the present invention will be described in detail in conjunction with the accompanying drawings as follows: As shown in Figure 3-1 and Figure 3-2, the array substrate of the embodiment of the present invention includes: a substrate 201, a polysilicon layer, a gate insulating layer 231, a metal Layer, passivation layer 251, pixel electrode 261, connection electrode 262 and pixel electrode edge protection layer 271 (pixel electrode edge protection layer 271 is suitable for LTPSAMOLED, if it is LTPS LCD, this layer may not be included).

Wherein, the polysilicon layer is disposed on the substrate 201 , which includes a channel region 212 and an ion-doped region 211 . A buffer layer (not shown) may also be provided between the polysilicon layer and the substrate 201 .

The gate insulating layer 231 is disposed above the polysilicon layer.

The metal layer includes: a source electrode 241 , a gate electrode 242 , a drain electrode 243 , a gate line 244 and a data line 245 made of the same metal material. The source electrode 241 is connected to the ion-doped region 211 on one side of the channel region 212 through the source via hole on the gate insulating layer 231 . The gate electrode 242 is disposed above the gate insulating layer 231 . The drain 243 is connected to the ion-doped region 211 on the other side of the channel region 212 through the drain via hole on the gate insulating layer 231 . The gate line 244 is connected to the gate electrode 242 , and since the gate line and the data line are formed of the same layer of metal material, the gate line 244 adopts a discontinuous design, that is, it is disconnected at the intersection with the data line 245 . The data line 245 is connected to the drain 243 , and the data line 245 is continuous.

The passivation layer 251 is disposed on the metal layer and can be made of SiNx/SiO ₂ . Vias are disposed on the passivation layer 251 . Specifically, the via holes include a first via hole and a second via hole, the first via hole is used to connect the source electrode 241 and the pixel electrode 261, and the second via hole is used to connect the Disconnected gridline 244.

The pixel electrode 261 and the connection electrode 262 are disposed above the passivation layer 251 . The pixel electrode 261 is electrically connected to the source electrode 241 through the first via hole on the passivation layer 251 . The connection electrode 262 is connected to the disconnected gate line 244 through the second via hole on the passivation layer 251 , that is to say, the connection electrode 262 serves as a connection bridge for the disconnected gate line 244 to realize The intersection design between the gate lines 244 and the data lines 245 on the same layer. The pixel electrode 261 and the connection electrode 262 are formed of the same layer material, which may be transparent electrode materials such as indium tin oxide.

For LTPS AMOLED, the pixel electrode edge protection layer 271 is disposed above the pixel electrode 261, the connection electrode 262 and the passivation layer 251, for protecting the organic layer formed above the pixel electrode.

In addition, at the intersection of the gate line 244 and the data line 245, the data line 245 can also be designed as a discontinuous form, while the gate line 244 can be designed as a continuous form, and then through the passivation The second via hole on the layer enables the connection electrode to connect the disconnected data line, and finally realizes a crossover design between the gate line and the data line on the same layer.

The present invention also provides a display device comprising the above-mentioned array substrate.

The present invention also provides a method for preparing an array substrate, the method comprising the steps of:

S1. Forming a polysilicon layer pattern on the substrate 201, the polysilicon layer pattern including a channel region 212 and ion-doped regions 211 on both sides of the channel region 212. specifically:

A layer of SiNx/ _SiO2 buffer layer is formed on the substrate 201 by chemical vapor deposition, etc., and a layer of amorphous silicon thin film can be formed on the buffer layer by chemical vapor deposition, and crystallized by LTPS (such as ELA, MIC, SPC and other crystallization methods) to convert amorphous silicon film into polysilicon film. Coat a layer of PR glue on the polysilicon film, use polysilicon Mask (the first mask) to expose, develop after exposure, etch and peel off the PR glue after development to form a polysilicon layer pattern.

S2. Form a gate insulating layer pattern 231 on the polysilicon layer pattern, and perform ion doping on the ion-doped region 211 by coating PR glue on the channel region 212 as a barrier layer.

Further, the step S2 may further include: performing an annealing process after ion-doping the ion-doped region by coating PR glue on the channel region as a barrier layer.

specifically:

A gate insulating layer film can be formed on the polysilicon layer pattern by chemical vapor deposition, etc., and the gate insulating layer film can be SiO ₂ /SiNx. After the PR glue is coated on the gate insulating layer film, the gate insulating layer film Layer via Mask (the second mask) exposes the source via hole and drain via hole patterns, and develops after the exposure. After the development, the PR glue on the channel region 212 is used as a barrier layer for ion implantation to perform ion implantation in the ion-doped region 211 . The ion implantation may be performed after developing, or after etching the source via hole and the drain via hole, and the latter is adopted in this embodiment. After the development, etch the pattern of the source via hole and the drain via hole, and perform ion implantation after the etching, as shown in Figure 4-1. After the ion implantation, an ion-doped region 211 is formed in the polysilicon layer, as shown in FIG. 4-2 . After the ion implantation, the PR glue is peeled off. Then an annealing process is carried out. In the annealing process, the dopant ions will also diffuse toward the channel region 212, but since the positions of the source via holes and the drain via holes of the gate insulating layer 231 can be used, the source via holes and the drain via holes can be independently designed. The distance between the pole via hole and the channel region 212 is such that when doping, the source electrode 241 and the drain electrode 243 can select the distance from the channel region 212 according to the design requirements, thereby reducing the The effect of ion diffusion on the length of the TFT effective channel region reduces the contact area between the gate electrode and the source-drain electrode (source and drain), and reduces the coupling capacitance between the gate electrode and the source-drain electrode.

S3. Form a metal layer on the gate insulating layer, and form a gate electrode, a source electrode, a drain electrode, a gate line and a data line on the metal layer.

The step S3 specifically includes: forming a metal layer on the gate insulating layer pattern, forming a gate electrode, a source electrode, a drain electrode, a gate line and a data line on the metal layer; The hole is connected to the ion-doped region below the source; the drain is connected to the ion-doped region below the drain through the drain via hole; the gate electrode is connected to the gate line; the drain is connected to The data line; the gate line is disconnected at the intersection with the data line, as shown in FIG. 4-3 .

Specifically, a metal layer film is formed by sputtering on the basis of the pattern formed by the second Mask, and then PR glue is coated on the metal layer film, exposed by the third Mask, and then developed, etched, The patterns of the gate electrode 242 , the source electrode 241 , the drain electrode 242 , the gate line 244 and the data line 245 are completed by stripping. Since the gate lines and the data lines are formed on the same metal layer, it is necessary to disconnect the lines at the intersections of the gate lines and the data lines. In this embodiment, the method of disconnecting the gate lines is adopted, and the method of disconnecting the data lines may also be adopted. Correspondingly, in the subsequent process of forming the pixel electrode pattern, connection electrodes can be formed to connect disconnected gate lines or data lines.

In addition, the method may also include the following steps:

S4. Form a passivation layer 251 on the metal layer, and form via holes in the passivation layer 251 . The via hole in the passivation layer is used to connect the pixel electrode 261 and the source electrode 241 , and connect the disconnected gate line 244 or the disconnected data line 245 .

Specifically, a passivation layer film can be formed on the metal layer by means of chemical vapor deposition, etc., and the fourth mask is used to form a via hole pattern on the passivation layer film through a patterning process. The patterning process specifically includes the processes of coating PR glue, developing, etching, and stripping, and the formed via holes are used to connect the pixel electrode and the source electrode, and connect the disconnected gate line or the disconnected data. Wire.

S5. Forming a pixel electrode 261 and a connection electrode 262 on the passivation layer 251 . The via hole in the passivation layer includes a first via hole and a second via hole, the pixel electrode 261 is connected to the source electrode 241 through the first via hole in the passivation layer; the connecting electrode 262 is connected to the source electrode 241 through the The second via hole in the passivation layer connects the disconnected gate line 244, as shown in FIG. 4-4.

Specifically, a transparent electrode film, which may be an indium tin oxide film, is formed on the passivation layer by means of sputtering or the like. Using the fifth mask, the transparent electrode film is formed into the pixel electrode and connection electrode pattern through a patterning process. The patterning process specifically includes the processes of applying PR glue, developing, etching, and stripping. The pixel electrode is connected to the source electrode through the first via hole in the passivation layer; the connection electrode is connected to the disconnected gate line through the second via hole in the passivation layer. For LTPS AMOLED, the method also includes step S6. Forming a pixel electrode edge protection layer 271 above the pixel electrode 261, the connection electrode 262 and the passivation layer 251, for protecting the edge protection layer 271 formed on the pixel electrode. The organic layer above, the array substrate formed after this step is shown in Figure 3-2.

Specifically, a protective layer film is formed on the pixel electrode 261, the connection electrode 262 and the passivation layer 251 by means of chemical vapor deposition, etc., and the pixel electrode is formed by a patterning process using the sixth mask. For the pattern of the edge protection layer, the one patterning process specifically includes the processes of coating PR glue, developing, etching and stripping.

In addition, in the step S3, the data line 245 can also be disconnected at the intersection with the gate line 244 to make the gate line 244 continuous; correspondingly, in the step S5, the connection can be made The electrode 262 is connected to the disconnected data line 245 through the second via hole in the passivation layer.

In the array substrate display device and preparation method described in the embodiments of the present invention, ion doping is performed by using PR glue as a barrier layer instead of a gate electrode as a barrier layer, which reduces the risk of implanted dopant ions diffusing to the channel region. The short channel effect also reduces the coupling capacitance between the gate source and the drain, thereby improving the working performance of the TFT. In addition, the use of the same layer electrode metal process reduces the number of Masks used and simplifies the preparation process.

The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all Equivalent technical solutions also belong to the category of the present invention, and the scope of patent protection of the present invention should be defined by the claims.

Claims (16)

1. An array substrate, comprising: the substrate comprises a substrate, a polycrystalline silicon layer, a gate insulating layer and a metal layer;

the polysilicon layer is disposed over the substrate, including: the device comprises a channel region and ion doped regions on two sides of the channel region;

the gate insulating layer is arranged above the polycrystalline silicon layer;

the metal layer comprises a gate electrode, a source electrode, a drain electrode, a grid line and a data line which are made of the same metal material.

2. The array substrate of claim 1, wherein the gate electrode is connected to the gate line;

the source electrode and the drain electrode are respectively connected with the ion doped region through a through hole on the gate insulating layer, and the drain electrode is also connected with the data line.

3. The array substrate of claim 1, wherein the gate line is disconnected at a crossing with the data line, the disconnected gate line being connected through a connection electrode above the metal layer; or,

the data lines are disconnected at the intersections with the gate lines, and the disconnected data lines are connected through the connection electrodes above the metal layer.

4. The array substrate of claim 3, wherein the array substrate further comprises: a passivation layer; the passivation layer is arranged above the metal layer, and the connecting electrode is connected with the disconnected grid line or the disconnected data line through a through hole in the passivation layer.

5. The array substrate of claim 4, wherein the array substrate further comprises: and the pixel electrode and the connecting electrode are formed by the same layer of material.

6. The array substrate of claim 5, wherein the pixel electrode is connected to the source electrode through a via on the passivation layer.

7. The array substrate of claim 5, wherein the array substrate further comprises: and the pixel electrode edge protection layer is arranged above the pixel electrode, the connecting electrode and the passivation layer.

8. A display device comprising the array substrate according to any one of claims 1 to 7.

9. A preparation method of an array substrate is characterized by comprising the following steps:

s1, forming a polysilicon layer graph on a substrate, wherein the polysilicon layer graph comprises a channel region and ion doped regions on two sides of the channel region;

s2, forming a grid insulating layer pattern above the polycrystalline silicon layer pattern, and performing ion doping on the ion doping area in a mode of coating PR glue above the channel area to serve as a barrier layer;

and S3, forming a metal layer above the grid insulation layer pattern, and forming a pattern comprising a grid electrode, a source electrode, a drain electrode, a grid line and a data line on the metal layer.

10. The method of claim 9, wherein the step S2 further comprises:

and carrying out ion doping on the ion doped region in a mode of coating PR glue above the channel region as a barrier layer, and then carrying out an annealing process.

11. The method according to claim 9, wherein the step S3 specifically includes:

forming a metal layer above the gate insulation layer pattern, and forming a pattern comprising a gate electrode, a source electrode, a drain electrode, a gate line and a data line on the metal layer; the source electrode is connected with the ion doped region through a source electrode through hole on the gate insulating layer; the drain electrode is connected with the ion doped region through a drain electrode through hole on the gate insulating layer; the gate electrode is connected with the grid line; the drain electrode is connected with the data line; the gate line is disconnected at a crossing with the data line, or the data line is disconnected at a crossing with the gate line.

12. The method of claim 9, further comprising the step of:

and S4, forming a passivation layer above the metal layer, and forming a via hole in the passivation layer, wherein the via hole of the passivation layer is used for connecting the pixel electrode with the source electrode, and connecting the disconnected grid line or the disconnected data line.

13. The method of claim 12, further comprising the step of:

s5, forming a graph comprising a pixel electrode and a connecting electrode above the passivation layer; the pixel electrode is connected with the source electrode through a through hole on the passivation layer; the connection electrode is connected with the disconnected gate line through a via hole on the passivation layer, or the connection electrode is connected with the disconnected data line through a via hole on the passivation layer.

14. The method of claim 13, further comprising the step of:

and S6, forming a pixel electrode edge protection layer pattern above the pixel electrode, the connecting electrode and the passivation layer.

15. The method according to claim 9, wherein the step S2 specifically includes the steps of:

s21: forming a gate insulating layer film above the polysilicon layer pattern, and coating PR glue on the gate insulating layer film;

s22: exposing and developing the PR glue above the ion doped region, and then etching the gate insulating layer film to form a source electrode through hole and a drain electrode through hole;

s23: and carrying out ion doping in the ion doping area by taking the PR glue above the channel area as a barrier layer.

16. The method of claim 9, wherein the step S2 specifically includes the steps of:

s21': forming a gate insulating layer film above the polysilicon layer pattern, and coating PR glue on the gate insulating layer film;

s22', exposing and developing the PR glue above the ion doping area;

s23', ion doping is carried out in the ion doping area by taking the PR glue above the channel area as a barrier layer;

s24': and etching the gate insulating layer film above the ion doped region to form a source electrode through hole and a drain electrode through hole.

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