CN105633150A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

The invention relates to the technical field of semiconductor chip manufacturing technology, in particular to a semiconductor device and a manufacturing method thereof. First, a second-type epitaxial layer is formed on the upper surface of the first-type semiconductor substrate, and a groove is etched in the second-type epitaxial layer; secondly, a first-type doped layer is formed on the inner wall of the groove. layer; filling the trench with silicon oxide; growing a gate oxide layer and a polysilicon layer in sequence, and the polysilicon layer covers at least the trench; finally, performing second-type ion implantation to form a second-type body region; The first type of ion implantation is performed to form the first type source region in the second type body region; the dielectric layer and the metal layer are grown in sequence, that is, in the process of manufacturing the super junction MOS device, the first type is formed on the inner wall of the trench A type doped layer, and then fill the trench with silicon oxide, without growing P-type epitaxy in the trench, thereby effectively reducing the process cost.

Description

A kind of semiconductor device and its manufacturing method

technical field

The invention relates to the technical field of semiconductor chip manufacturing technology, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

In the prior art, when making a superjunction MOS (Metal-Oxide-Semiconductor, metal-oxide-semiconductor transistor) device, a deep trench is first etched on the N-type epitaxial layer, and then a P-type epitaxial layer is grown in the deep trench. , and then further fabricate a polysilicon gate, and finally grow a dielectric layer and a metal layer in sequence in the etched polysilicon window, thereby forming a super-junction MOS device.

The specific process flow of making super junction MOS devices is as follows:

Step 1. First, make an N-type epitaxial layer on the upper surface of the N-type substrate; secondly, grow an initial oxide layer on the upper surface of the N-type epitaxial layer; finally, etch away part of the initial oxide layer until it is in the N-type epitaxial layer A deep trench is etched, as shown in Figure 1a.

Step 2, growing P-type epitaxy in the etched deep trench until the P-type epitaxy completely covers the entire N-type epitaxial layer and the upper surface of the deep trench, as shown in FIG. 1b.

Step 3: Grinding and polishing the redundant P-type epitaxial layer, so that the upper surfaces of the N-type epitaxial layer and the P-type epitaxial layer are located on the same horizontal plane, as shown in FIG. 1c.

Step 4, growing a gate oxide layer on both the upper surfaces of the N-type epitaxial layer and the P-type epitaxial layer, as shown in FIG. 1d.

Step 5, growing a polysilicon layer on the upper surface of the gate oxide layer, as shown in FIG. 1e.

Step 6, using photoresist to etch away part of the polysilicon layer, and using the remaining polysilicon layer as a mask to perform low-dose P-type ion implantation to form a P-body region, as shown in FIG. 1f.

Step 7: Form a photoresist mask on the upper surface of the trench, and perform high-dose N-type ion implantation to form a source region, as shown in FIG. 1g.

Step 8, growing a dielectric layer on the upper surface of the remaining polysilicon layer, as shown in FIG. 1h.

Step 9, growing a metal layer on the upper surface of the dielectric layer, as shown in FIG. 1i.

However, in the process of manufacturing a superjunction MOS device using the above method, it is necessary to grow P-type epitaxy in the trench, and the process cost is relatively high.

Contents of the invention

Embodiments of the present invention provide a semiconductor device and a manufacturing method thereof, which do not need to grow P-type epitaxy in a trench, thereby saving process costs.

A method for manufacturing a semiconductor device provided by an embodiment of the present invention includes:

forming a second type epitaxial layer on the upper surface of the first type semiconductor substrate, and etching grooves in the second type epitaxial layer;

forming a first type doped layer on the inner wall of the trench;

filling the trench with silicon oxide;

growing a gate oxide layer and a polysilicon layer in sequence, the polysilicon layer covering at least the trench;

Performing second-type ion implantation to form a second-type body region;

performing first-type ion implantation to form a first-type source region in the second-type body region;

A dielectric layer and a metal layer are grown sequentially.

Preferably, the trench has a depth of 30-60um and a width of 2-8um.

Preferably, it also includes: doping with phosphorus oxychloride and driving in at high temperature to form the first type doped region.

Preferably, filling the silicon oxide in the trench specifically includes: growing the silicon oxide in the trench, and removing the redundant silicon oxide if the grown silicon oxide overflows the trench. oxide so that the second type epitaxial layer and the silicon oxide in the trench are on the same level.

Preferably, the first type is N type; the second type is P type; and the silicon oxide is silicon dioxide.

Preferably, the method further includes: the polysilicon layer covers at least the trench and the first type doped region.

In a semiconductor device provided by an embodiment of the present invention, the upper surface of a first-type semiconductor substrate is covered with a second-type epitaxial layer, and the second-type epitaxial layer has a first-type source region, a second-type body region, a trench A groove and a first type doped layer surrounding the groove, the groove is filled with silicon oxide, at least a gate oxide layer, a polysilicon layer, a dielectric layer and a metal layer are sequentially arranged on the groove, and the metal The layer is connected to the epitaxial layer where the first type source region and the second type body region are located.

Preferably, the trench has a depth of 30-60um and a width of 2-8um.

Preferably, the first type is N type; the second type is P type; and the silicon oxide is silicon dioxide.

Preferably, a gate oxide layer, a polysilicon layer, a dielectric layer and a metal layer are sequentially arranged at least on the trench and the first-type doped region, and the metal layer is connected with the first-type source region and the first-type doped region. The epitaxial layers where the second-type body regions are located are connected.

In the method for manufacturing a semiconductor device provided by the above embodiment, firstly, a second-type epitaxial layer is formed on the upper surface of the first-type semiconductor substrate, and grooves are etched in the second-type epitaxial layer; secondly, the forming a first-type doped layer on the inner wall of the trench; filling the trench with silicon oxide; growing a gate oxide layer and a polysilicon layer in sequence, and the polysilicon layer at least covers the trench; finally, performing a second Type ion implantation to form a second type body region; perform first type ion implantation to form a first type source region in the second type body region; grow a dielectric layer and a metal layer in sequence, that is, when making a super junction MOS device During the process, by forming the first type doped layer on the inner wall of the trench, and then filling the trench with silicon oxide, there is no need to grow P-type epitaxy in the trench, thereby effectively reducing the process cost.

The semiconductor device provided by the above embodiment includes: the upper surface of the first type semiconductor substrate is covered with a second type epitaxial layer, and the second type epitaxial layer has a first type source region, a second type body region, a trench and A first-type doped layer surrounding the trench, the trench is filled with silicon oxide, at least on the trench, a gate oxide layer, a polysilicon layer, a dielectric layer and a metal layer are sequentially arranged, and the metal layer and The epitaxial layer where the first-type source region and the second-type body region are located is connected. It is only necessary to form a first-type doped layer in and around the trench, and then fill the trench with silicon oxide. It is necessary to grow P-type epitaxy in the trench, so as to effectively reduce the process cost.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

Figures 1a to 1i are schematic diagrams of the device structure obtained in each step of the conventional manufacturing process of a superjunction MOS semiconductor device;

2 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

3 to 13 are schematic flow charts of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

FIG. 14 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments . Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The method for manufacturing a semiconductor device provided in the embodiment of the present invention can be used to manufacture a super junction MOS (Metal-Oxide-Semiconductor, metal oxide semiconductor transistor) device; and the "first type" in the embodiment of the present invention is relative to the "second type" In terms of "two types", when the first type is N type, the second type is P type; and when the first type is P type, the second type is N type.

Fig. 2 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. As shown in Fig. 2, the method may include steps:

S201 , forming a second type epitaxial layer on the upper surface of the first type semiconductor substrate, etching trenches in the second type epitaxial layer, and turning to step S202 .

S202. Form a first type doped layer on the inner wall of the trench, and go to step S203.

S203. Fill the trench with silicon oxide, and go to step S204.

S204, growing a gate oxide layer and a polysilicon layer in sequence, the polysilicon layer covering at least the trench;

Go to step S205.

S205 , perform second type ion implantation to form a second type body region, and go to step S206 .

S206. Perform first-type ion implantation to form a first-type source region in the second-type body region, and go to step S207.

S207 , growing a dielectric layer and a metal layer in sequence.

Preferably, the first-type semiconductor substrate is an N-type semiconductor substrate; the second-type epitaxial layer is a P-type epitaxial layer; and the silicon oxide is silicon dioxide.

Preferably, the depth of the trench is 30-60um, and the width is 2-8um.

Preferably, phosphorous oxychloride is used for doping and driven in at high temperature to form the first type doped region.

Preferably, in the above step S203, if the grown silicon oxide overflows the trench, remove the excess silicon oxide to oxidize the second type epitaxial layer and the silicon in the trench objects on the same level.

Preferably, the polysilicon layer covers at least the trench and the first type doped region.

Taking "first type" N-type; "second type" P-type; silicon dioxide as an example, the method for manufacturing a semiconductor device provided by this embodiment will be described in detail below.

First, provide an N-type substrate, which can be a wafer doped with N-type ions or a silicon layer prepared on the wafer; grow a P-type epitaxial layer on the upper surface of the N-type substrate, And continue to prepare an initial oxide layer on the P-type epitaxial layer, for example, an oxide layer with a thickness of 0.2-0.8um can be grown on the above-mentioned P-type epitaxial layer in a temperature environment of 900-1100°C to form The above-mentioned initial oxide layer plays a protective role.

Secondly, using photolithography and etching processes, using the initial oxide layer with grooves as a mask, etch the P-type epitaxial layer and stop in the P-type epitaxial layer to form a layer with a depth of 30 in the P-type epitaxial layer. A groove with a width of ～60um and a width of 2～8um, and the distance between the bottom of the groove and the upper surface of the N-type substrate must meet the thickness requirements for the subsequent preparation of the N-type doped layer. The specific structure is shown in the figure 3.

Afterwards, based on the structure shown in Figure 3, continue to perform N-type doping on the trench to form an N-type doped region on the inner wall of the trench, that is, form the structure shown in Figure 4; and continue to drive in process to drive the above-mentioned N-type doped ions to form an N-type doped layer to form the structure shown in FIG. 5 .

Preferably, the above-mentioned N-type doping can be done in a high-temperature furnace tube at a temperature of 800-1000°C, doping phosphorus oxychloride into the P-type epitaxial layer exposed by the trench, and continuing at 900-1200°C. Under the temperature condition of ℃, the above-mentioned doped phosphorus oxychloride is driven into the process for 80-200 minutes (minutes), so as to drive the phosphorus oxychloride into the depth of the P-type epitaxial layer, and then form the N-type doped region; wherein, the thickness of the N-type doped layer can be adjusted according to specific process requirements by adjusting the above-mentioned N-type doped ion concentration and/or process parameters such as the temperature and time of the subsequent drive-in process to achieve its predetermined thickness.

Then, on the basis of the structure shown in Figure 5, continue to deposit a silicon dioxide layer at a temperature of 600-1000 °C to fill the above-mentioned grooves and cover the surface of the initial oxide layer, that is, to form a silicon dioxide layer as shown in Figure 6. Structure. Continue to use etching or grinding to remove excess silicon dioxide and initial oxide layer to the upper surface of the P-type epitaxial layer, that is, at this time, the upper surfaces of the P-type epitaxial layer and the silicon dioxide layer are all on the same level to form 7 shows the structure.

Further, on the basis of the structure shown in Figure 7, a gate oxide layer with a thickness of 0.05-0.20um can be grown to cover the above-mentioned P-type epitaxial layer, N-type doped layer and After oxidizing the upper surface of the silicon dioxide layer, continue to grow a polysilicon layer with a thickness of 0.2-0.8um on the upper surface of the above-mentioned gate oxide layer under the temperature condition of 500-800°C to form the structure shown in Figure 8; Continue to use photolithography and etching processes to remove the polysilicon layer located above the upper surface of the P-type epitaxial layer, and retain the polysilicon layer located above the N-type doped layer and the silicon dioxide layer to form the structure shown in Figure 9, In specific implementation, after removing the polysilicon layer above the upper surface of the P-type epitaxial layer by photolithography and etching, only the polysilicon layer above the silicon dioxide layer may be retained. Continue to use the retained polysilicon layer as a mask to perform P-type ion implantation and drive-in process on the P-type epitaxial layer to form a P-type body region located in the P-type epitaxial layer and N-type doped layer, as shown in Figure 10 structure shown.

Preferably, the ions for the above-mentioned P-type ion implantation may be boron ions, the dose of ion implantation may be 1.0E13-1.0E15/cm ² , and the energy of ion implantation may be 50KEV-150KEV; the temperature for performing the above-mentioned drive-in process may be 1000-1200°C is selected, and the driving time can be 50-200 minutes.

Further, on the basis of the structure shown in Figure 10, continue to use photolithography and etching processes to prepare a photoresist with a source region pattern on the surface of the exposed gate oxide layer, and use the photoresist and the remaining The polysilicon layer is used as a mask to perform N-type ion implantation on the P-type body region. And after continuing to remove the photoresist above, a source region is formed in the P-type body region, and the source region is an N-type source region, so as to form the structure shown in FIG. 11 . For example, the implantation energy of 50KEV-150KEV can be used to form the above-mentioned N-type source region by implanting phosphorus ions at a dose of 1.0E15-1.0E16/cm ² .

Further, on the basis of the structure shown in Figure 11, continue to prepare a dielectric layer covering the exposed surface of the remaining polysilicon layer and the gate oxide layer, and the thickness of the dielectric layer is greater than the thickness of the remaining polysilicon layer; Part of the dielectric layer on the upper surface of the oxide layer is stopped on the upper surface of the N-type source region, and the dielectric layer covering the remaining polysilicon layer is retained to form part of the upper surface of the above-mentioned N-type source region and the adjacent N-type source region. Contact holes are exposed on the upper surface of the P-type body region between the source regions to form the structure shown in FIG. 12 .

Preferably, the above-mentioned dielectric layer may be a two-layer structure, for example, it may include a 0.2um thick undoped silicon dioxide layer and a 0.8um thick phosphosilicate glass layer.

Finally, on the basis of the structure shown in Figure 12, the above-mentioned contact holes are filled with metal materials, and the metal layer is formed after the electroplating process, and the metal layer is sequentially subjected to photolithography and etching processes to remove the redundant metal layer, so as to Metal interconnection lines are formed, that is, the structure shown in FIG. 13 is formed.

Preferably, the material of the above metal layer may be aluminum/silicon/copper alloy, and the thickness of the metal layer may be 2˜5 μm.

In the method for manufacturing a semiconductor device provided by the above embodiment, firstly, a second-type epitaxial layer is formed on the upper surface of the first-type semiconductor substrate, and grooves are etched in the second-type epitaxial layer; secondly, the forming a first-type doped layer on the inner wall of the trench; filling the trench with silicon oxide; growing a gate oxide layer and a polysilicon layer in sequence, and the polysilicon layer at least covers the trench; finally, performing a second Type ion implantation to form a second type body region; perform first type ion implantation to form a first type source region in the second type body region; grow a dielectric layer and a metal layer in sequence, that is, when making a super junction MOS device During the process, by forming the first type doped layer on the inner wall of the trench, and then filling the trench with silicon oxide, there is no need to grow P-type epitaxy in the trench, thereby effectively reducing the process cost.

In the method for manufacturing a semiconductor device provided by the above embodiment, firstly, a second-type epitaxial layer is formed on the upper surface of the first-type semiconductor substrate, and grooves are etched in the second-type epitaxial layer; secondly, the forming a first-type doped layer on the inner wall of the trench; filling the trench with silicon oxide; growing a gate oxide layer and a polysilicon layer in sequence, and the polysilicon layer at least covers the trench; finally, performing a second Type ion implantation to form a second type body region; perform first type ion implantation to form a first type source region in the second type body region; grow a dielectric layer and a metal layer in sequence, that is, when making a super junction MOS device During the process, by forming the first type doped layer on the inner wall of the trench, and then filling the trench with silicon oxide, there is no need to grow P-type epitaxy in the trench, thereby effectively reducing the process cost.

Based on the method for manufacturing a semiconductor device provided in the above embodiments, another embodiment of the present invention further provides a semiconductor device, which can be manufactured by the above method for manufacturing a semiconductor device.

Based on the flow chart of the method for making a semiconductor device described in FIG. 2, FIG. 14 shows a schematic structural view of the semiconductor device. As shown in FIG. 14, the semiconductor device may include: the upper surface of the first type semiconductor substrate is covered with a second type An epitaxial layer, the second type epitaxial layer has a first type source region, a second type body region, a trench and a first type doped layer surrounding the trench, the trench is filled with silicon oxide, at least A gate oxide layer, a polysilicon layer, a dielectric layer and a metal layer are sequentially arranged on the trench, and the metal layer is connected to the epitaxial layer where the first type source region and the second type body region are located.

Preferably, the trench has a depth of 30-60um and a width of 2-8um.

Preferably, the first type is N type; the second type is P type; and the silicon oxide is silicon dioxide.

Preferably, a gate oxide layer, a polysilicon layer, a dielectric layer and a metal layer are sequentially arranged at least on the trench and the first-type doped region, and the metal layer is connected with the first-type source region and the second The epitaxial layers where the type body regions are located are connected.

A semiconductor device provided by an embodiment of the present invention includes: the upper surface of a first type semiconductor substrate is covered with a second type epitaxial layer, and the second type epitaxial layer has a first type source region, a second type body region, a trench A groove and a first type doped layer surrounding the groove, the groove is filled with silicon oxide, at least a gate oxide layer, a polysilicon layer, a dielectric layer and a metal layer are sequentially arranged on the groove, and the metal The layer is connected to the epitaxial layer where the first type source region and the second type body region are located. It is only necessary to form a first type doped layer in and around the trench, and then fill the trench with silicon oxide , there is no need to grow P-type epitaxy in the trench, thereby effectively reducing the process cost.

While preferred embodiments of the invention have been described, additional changes and modifications to these embodiments can be made by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment as well as all changes and modifications which fall within the scope of the invention.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (10)

1. the method making semiconductor device, it is characterised in that including:

Upper surface in first kind Semiconductor substrate forms Second Type epitaxial layer, etches groove in described Second Type epitaxial layer;

The inwall of described groove is formed first kind doped layer;

Fill up Si oxide in the trench;

Growth gate oxide and polysilicon layer successively, described polysilicon layer at least covers described groove;

Carry out Second Type ion implanting, form Second Type body district;

Carry out first kind ion implanting, described Second Type body district is formed first kind source region;

Somatomedin layer and metal level successively.

2. the method for claim 1, it is characterised in that described gash depth is 30��60um, width is 2��8um.

3. the method for claim 1, it is characterised in that also include: adopt phosphorus oxychloride to carry out adulterating and high temperature drives in formation first kind doped region.

4. the method for claim 1, it is characterized in that, fill up Si oxide in the trench to specifically include: grow described Si oxide in the trench, if the described Si oxide of growth overflows groove, then remove described unnecessary Si oxide so that the described Si oxide in described Second Type epitaxial layer and described groove is positioned in same level.

5. the method for claim 1, it is characterised in that the described first kind is N-type; Described Second Type is P type; Described Si oxide is silicon dioxide.

6. the method for claim 1, it is characterised in that also include: described polysilicon layer at least covers described groove and described first kind doped region.

7. a semiconductor device, it is characterized in that, the upper surface of first kind Semiconductor substrate is coated with Second Type epitaxial layer, described Second Type epitaxial layer has first kind source region, Second Type body district, groove and the first kind doped layer around groove, Si oxide is filled up in described groove, at least being disposed with gate oxide, polysilicon layer, dielectric layer and metal level on described groove, described metal level is connected with the epitaxial layer residing for described first kind source region and Second Type body district.

8. semiconductor device as claimed in claim 7, it is characterised in that described gash depth is 30��60um, and width is 2��8um.

9. semiconductor device as claimed in claim 7, it is characterised in that the described first kind is N-type; Described Second Type is P type; Described Si oxide is silicon dioxide.

10. semiconductor device as claimed in claim 7, it is characterized in that, at least being disposed with gate oxide, polysilicon layer, dielectric layer and metal level on described groove and described first kind doped region, described metal level is connected with the epitaxial layer residing for described first kind source region and Second Type body district.