[go: up one dir, main page]

CN105580130A - 用于安装芯片的衬底和芯片封装 - Google Patents

用于安装芯片的衬底和芯片封装 Download PDF

Info

Publication number
CN105580130A
CN105580130A CN201480051090.5A CN201480051090A CN105580130A CN 105580130 A CN105580130 A CN 105580130A CN 201480051090 A CN201480051090 A CN 201480051090A CN 105580130 A CN105580130 A CN 105580130A
Authority
CN
China
Prior art keywords
chip
electrode
protrusion
conductive
mounting substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201480051090.5A
Other languages
English (en)
Inventor
安范模
宋台焕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pu Yinte Engineering Co Ltd
Point Engineering Co Ltd
Original Assignee
Pu Yinte Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pu Yinte Engineering Co Ltd filed Critical Pu Yinte Engineering Co Ltd
Publication of CN105580130A publication Critical patent/CN105580130A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/8506—Containers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/852—Encapsulations
    • H10H20/853—Encapsulations characterised by their shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/08238—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81205—Ultrasonic bonding
    • H01L2224/81207—Thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81417—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81424—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00015—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/858—Means for heat extraction or cooling
    • H10H20/8585—Means for heat extraction or cooling being an interconnection

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Led Device Packages (AREA)

Abstract

本发明涉及用于安装芯片的衬底。根据本发明的用于安装芯片的衬底包括：用于将电极施加到要被安装的芯片的多个导电部分；电隔离导电部分以将电极施加到芯片的电极部分中的每个的至少一个绝缘部分；以及突起，其形成为在由绝缘部分隔离的每个导电部分的表面上具有预定高度并且键合到形成在芯片上的电极部分。在金属衬底包含垂直绝缘层的情形中，芯片的电极部分和衬底的电极部分应当被彼此电键合。因此，本发明通过使用附加地形成在金属衬底上的突起来键合在芯片的电极部分上形成的电镀层，能够使芯片和衬底之间紧密键合。另外，通过将密封材料施加到芯片的键合区域，能够防止由于材料之间膨胀系数差异而导致的破裂的发生，并且能够防止键合区域与外部接触，从而防止键合区域的氧化。这样，能够在没有使用惰性气体填充芯片安装在其中的衬底的内部的情况下执行封装过程。

Description

用于安装芯片的衬底和芯片封装
技术领域
本发明涉及用于安装芯片的衬底，并且更具体地，涉及其上面将会安装紫外芯片的衬底和其上面安装紫外芯片的封装。
背景技术
在大多数情形中，紫外芯片具有倒装芯片的形式，其中电极形成在倒装芯片的下部分中。为了在衬底上安装具有倒装芯片结构的芯片，考虑到电极的位置和衬底的平整度而使用了子底座。
特别地，在相关技术的陶瓷封装中，电极被涂覆在安装有芯片的硅晶片的类型的子底座被键合到形成在陶瓷衬底上的电极部分。形成在硅晶片上的电极被键合到紫外倒装芯片的电极，从而安装芯片。
根据这种方法，需要执行在陶瓷衬底上安装子底座的附加步骤。归因于用于安装子底座的结构特征(环氧粘合剂)，带来这样一个问题：紫外芯片中生成的热量不能被有效地传递到金属衬底，结果降低了紫外可固化粘合剂的寿命。
发明内容
技术问题
鉴于前面提到的问题，本发明的一个目的是提供一种能够在无需使用子底座的情况下安装芯片的金属衬底结构。本发明的另一个目的是提供一种能够防止暴露由于芯片的安装而形成的键合部分的芯片封装结构。
问题的技术方案
根据本发明用于实现上述目的的一个方面，提供了一种芯片安装衬底，包括：配置成将电极电压施加到具有电极部分的被安装芯片的多个导电部分；配置成将导电部分电隔离以便将电极电压施加到芯片的电极部分的至少一个绝缘部分；以及以预定高度形成在导电部分的表面上并键合到芯片的电极部分的多个突起。
在芯片安装衬底中，从导电部分向内下陷并且配置成提供在其中安装芯片的空间的腔可以优选地形成在导电部分中，芯片安装在腔内。
在芯片安装衬底中，突起可以优选地以预定高度形成在具有腔的导电部分的表面上并且可以优选地键合到芯片的电极部分。
在芯片安装衬底中，芯片的电极部分可以优选地形成在芯片的面对具有腔的导电部分的表面的一个表面上，并且突起可以优选地键合到形成在芯片的面对具有腔的导电部分的表面的一个表面上的电极部分。
芯片安装衬底还可以包括：焊料，所述焊料形成在突起的表面上以将突起焊接到芯片的电极部分。
芯片安装衬底还可以包括：标记部分，所述标记部分跨越绝缘部分形成在导电部分的表面上以指示形成突起的位置。
在芯片安装衬底中，具有预定深度的凹陷可以优选地形成在腔内，并且突起可以优选地以预定高度形成在凹陷内导电部分的表面上并且键合到芯片的电极部分。
芯片安装衬底还可以包括：电镀层，所述电镀层以预定高度形成在由绝缘部分隔离的导电部分的表面上并且配置成将导电部分键合到突起。
根据本发明用于实现上述目的的另一个方面，提供了一种芯片封装，包括：芯片；以及芯片安装衬底，所述芯片安装衬底包括配置成将电极电压施加到具有电极部分的芯片的多个导电部分、配置成将导电部分电隔离以便将电极电压施加到芯片的电极部分的至少一个绝缘部分以及以预定高度形成在导电部分的表面上并键合到芯片的电极部分的多个突起。
芯片封装还可以包括：形成在芯片和芯片安装衬底之间的空间中的包封部分，该包封部分通过将突起键合到芯片的电极部分而形成，其中包封部分可以配置成包封芯片的键合区域。
发明的有益效果
根据本发明，在金属衬底包含垂直绝缘层的情形中，芯片的电极部分和衬底的电极部分需要被彼此电连接。因此，通过在金属衬底上附加地形成突起并且将突起键合到芯片的电极部分，就能够在衬底和芯片之间提供可靠的键合。
另外，通过在芯片的键合区域上涂覆包封材料，能够防止破裂的产生，否则由于材料之间热膨胀系数的差异，可能会产生破裂。还能够防止键合区域的氧化，否则环境空气可能会造成键合区域的氧化。这使得能够在无需使用将惰性气体填充到芯片被安装的空间中的附加过程的情况下执行封装过程。
附图说明
图1是示意了陶瓷封装的视图，在所述陶瓷封装中芯片安装在用于保持紫外倒装芯片的陶瓷衬底上。
图2是示意了根据本发明的一个实施方式的芯片安装衬底的结构的视图。
图3-6是示意了根据本发明的一个实施方式的芯片封装的视图，在所述芯片封装中芯片安装到芯片安装衬底。
图7是示意了根据本发明的一个实施方式的芯片安装衬底的视图，所述芯片安装衬底还包括标记部分。
具体实施方式
以下的公开仅仅示意了本发明的原理。尽管在本说明书中没有明确地描述或示意，但是本领域内的技术人能能够创造实现本发明的原理并且落于本发明的精神和范围内的不同的设备。并且，本文公开的所有条件项和实施方式本质上用于促进对本发明的构思的理解。应该理解，本文具体描述的实施方式和形态不是限制性的。
根据结合附图给出的详细描述，上述目的、特征和优点将变得更加明了。因此，本发明所属领域内具有普通知识的人员将能够容易实施本发明的技术构思。
在对本发明的描述中，如果确定与本发明有关的现有技术的详细描述将不必要地使得本发明的精神模糊不清的话，将会省略这些描述。下文中，将参考附图详细描述芯片安装衬底。出于方便，将选取紫外芯片作为芯片的例子来进行描述。
图1是示意了陶瓷封装的视图，在所述陶瓷封装中芯片安装在用于保持紫外倒装芯片20的陶瓷衬底10上。
陶瓷衬底10包括形成在其中并且配置成将电极电压施加到安装在其上的芯片20的电极部分12。芯片20通过引线键合而连接到电极部分12。
归因于不需要绝缘层的陶瓷结构的特征，电极部分12彼此之间被电隔离。考虑到具有形成在其下部分中的电极部分的紫外倒装芯片20的结构特征并且考虑到衬底的平整度，芯片20不直接安装到衬底而是利用子底座14而被安装。
具体地，在陶瓷封装中，通过在硅晶片上涂覆电极而形成的子底座14键合到形成在陶瓷衬底中的电极部分16。形成在硅晶片上的电极部分16和紫外倒装芯片的电极彼此键合，从而安装芯片20。之后，通过引线键合而将子底座14的电极部分16和衬底的电极部分12彼此键合，以使得电极电压能够被施加到芯片。
根据这种方法，需要使用将子底座14安装到陶瓷衬底的附加过程。由于用于安装子底座的结构特征(环氧粘合剂15的使用)，带来这样一个问题：不能将在紫外芯片中生成的热量有效地传递到金属衬底。这导致紫外芯片的寿命变得较短的问题。
为了解决前面提到的问题，本发明提供了一种能够在无需使用子底座的情况下安装芯片的金属衬底结构以及一种能够防止暴露由于芯片的安装而产生的键合区域的芯片封装结构。在下文中，将参考附图具体描述本发明。
图2是示意了根据本发明的一个实施方式的芯片安装衬底200的结构的视图。
参考图2，根据本实施方式的芯片安装衬底200包括导电部分110、绝缘部分120和突起130。
在本实施方式中，导电部分110用于将电极电压施加到安装的芯片200。也就是说，导电部分110由导电的材料制成以便将电极电压施加到芯片200。导电部分110的下部分键合到基板50，电极形成在基板50中，以使得导电部分110能够从外部接收电极电压。在该实施方式中，导电部分110可以由铝板制成。
绝缘部分120电隔离导电部分110以使得电极电压能够施加到芯片200的电极部分210。具体地，绝缘部分120电隔离导电部分110以使得正电压和负电压能够施加到芯片200。这样被隔离的导电部分110从外部接收正电压和负电压。
此外，在本实施方式中，从导电部分110向内下陷的腔140形成在芯片安装衬底中，以提供将芯片200安装在其中的空间。参考图2，芯片200安装在其上的芯片安装衬底的表面从芯片安装衬底的外部分凹陷。也就是说，芯片安装衬底形成为使得外壁形成在芯片200在其中被安装的区域周围。为了反射从芯片200发射的光，腔140可以形成为顶部宽底部窄的形状。换言之，如在图2中示意的，外壁可以相对于芯片安装衬底的中轴线向上且向外倾斜。
在本实施方式中，突起130以预定高度形成在由绝缘部分120隔离的导电部分110的表面上并且被连接到形成在芯片200中的电极部分210。具体地，突起130形成在导电部分110的表面上，即，形成在与如图2中所示的腔140的中央部分对应的导电部分110的表面的区域上。
与腔140的中央部分对应的导电部分110的表面的区域被绝缘部分120隔离。突起130以预定高度形成在由绝缘部分120隔离的导电部分110的表面上。突起130优选由导电材料制成以使得施加到导电部分110的电压能够经由突起130传递到芯片200的电极部分210。突起130可以是由金制成的金突起。
芯片200的电极部分210形成在其面对腔140形成在其中的导电部分110的表面的一个表面上。突起130键合到形成在芯片200的一个表面上的电极部分210。
图3是示意了根据本发明的一个实施方式的芯片封装的视图，在所述芯片封装中芯片200安装到芯片安装衬底。在图3中，芯片200的电极部分210形成在下表面上。当芯片200安装在芯片安装衬底上时，芯片200的电极部分210与形成在芯片安装衬底上的突起130接触。
在本实施方式中，突起形成在由铝制成的芯片安装衬底上的芯片安装位置(电极区域)中。突起130可以利用引线键合设备形成。在另一个实施方式中，突起可以预先形成在芯片的电极部分中。备选地，芯片的电极部分可以形成为是厚的以便用作突起，并且可以键合到铝制的芯片安装衬底。
参考图3，芯片安装衬底200还可以包括形成在突起130的表面上的焊料150，以便将电极部分210和突起130焊接在一起。形成在紫外芯片的电极区域中的电镀层160可以通过热超声方法键合到突起130。备选地，电极部分210可以通过形成在突起130的表面上的焊料150而焊接到突起130的表面。
另外，参考图6，在本实施方式中，芯片安装衬底200包括以预定深度形成在腔140内的凹陷。突起130以预定高度形成在凹陷形成在其中的导电部分110的表面上。突起130连接器可以键合到形成在芯片200中的电极部分210。如图6中示出的，凹陷可以以类似于图2的方式形成为在腔140形成在其中的导电部分110的表面中具有预定深度，并且突起130可以形成在凹陷的底表面上。
由于倒装芯片200的结构，紫外线从芯片200的表面而非其下表面输出。当安装芯片200时，突起130和电极部分210的键合区域与发射出紫外线的区域清楚地区分开。这使得能够增加紫外线的输出。
另外，还可以设置随后将会描述的包封部分400。当形成包封部分400时，能够准确地控制材料的量。关于该点，将在之后进行描述。
参考图5，芯片安装衬底200还可以包括形成在突起130和导电部分110之间的导电部分110的表面上的电镀层160。也就是说，当在导电部分110的表面上键合突起130时，可靠性有可能被降低。通过在导电部分110的表面上有选择地形成电镀层160，能够强力地键合突起130。
参考图7，根据本实施方式的芯片安装衬底200还可以包括标记部分180，其指示用于键合芯片200的突起130的形成位置并且其可以由用于形成突起130的设备识别。在本实施方式中，标记部分180形成为延伸跨越绝缘层。这样，用于形成突起130的设备能够在绝缘层和标记位置180的基础上的识别突起130的形成位置，并且能够在预定位置中形成突起130。
在本实施方式中，可以通过许多不同方法形成标记部分180。可以通过激光器形成标记部分180。激光器的使用使得能够在具有图2和6中示意的复杂形状的芯片安装衬底上轻易形成标记部分180。由于标记部分180在绝缘层的基础上形成，所以优选地是标记部分180与绝缘层关联地形成。
接下来，将对芯片封装200进行描述，在所述芯片封装中芯片200安装在上述的芯片安装衬底200上。参考图3，根据本实施方式的芯片封装200包括芯片200、芯片安装衬底200和密封元件300。
如上所述，在本实施方式中，芯片200可以是紫外芯片200。芯片200可以具有倒装芯片的形状，电极部分210形成在所述倒装芯片200的下表面上。
如上所述，芯片安装衬底200包括用于将电极电压施加到芯片200的多个导电部分110、用于电隔离导电部分110的至少一个绝缘部分120以及以预定高度形成在导电部分110的表面上并键合到芯片200的电极部分210的突起130。由于根据本实施方式的芯片封装的芯片安装衬底与前面提到的芯片安装衬底相同，所以将省略对其的描述。
密封元件300配置成密封安装在腔140内的芯片200并且可以布置在导电部分110的顶表面上以便覆盖腔140。密封元件300可以由玻璃、石英或硅制成。
在本实施方式中，芯片封装还可以包括包封部分400。包封部分400形成在芯片200和芯片安装衬底之间的空间中，所述空间通过将突起130键合到芯片200的电极部分210而形成。包封部分400配置成包封芯片200的键合区域。
如果包封部分400如图4所示的那样通过在芯片200的键合区域上涂覆包封材料而形成，则能够防止破裂的产生，否则，由于芯片200和芯片安装衬底之间热膨胀系数的差异，可能会产生破裂。这能够形成可靠的芯片封装。
由于芯片200的键合区域不与空气接触，因此够防止芯片200的氧化，否则环境空气可能会造成芯片200的氧化。因此，没有必要将芯片200的内部保持于真空状态或者将惰性气体(例如，N2气体)填充到芯片200中以便将芯片200的内部保持于惰性状态。
在根据前面提及的实施方式的芯片封装中，在金属衬底包含垂直绝缘层的情形中，芯片的电极部分和衬底的电极部分需要被彼此电连接。因此，如在本实施方式中的那样，通过附加地在金属衬底上形成突起并且将突起键合到芯片的电极部分210，就能够在衬底和芯片之间提供可靠的键合。另外，通过在芯片的键合区域上涂覆包封材料，能够防止破裂的产生，否则由于材料之间热膨胀系数的差异，可能会产生破裂。还能够防止键合区域的氧化，否则环境空气可能会造成键合区域的氧化。这能够在无需使用将惰性气体填充到芯片安装在其中的空间中的附加过程的情况下执行封装过程。
前面的描述仅仅是对本发明的技术思想的示例性描述。在本发明所属技术领域内具有一般知识的人员将能够在不背离本发明的实质性特征的情况下做出修改、改变和替换。
因此，本文公开的实施方式和附图不打算限制本发明的技术构思，而仅用于描述本发明。本发明的技术构思不应当受实施方式和附图的限制。应当在随附的权利要求的基础上解读本发明的保护范围。与权利要求在范围上等价的所有技术构思应当解读为落于本发明的范围内。

Claims (18)

1.一种芯片安装衬底，包括：
配置成将电极电压施加到具有电极部分的被安装芯片的多个导电部分；
配置成将导电部分电隔离以便将电极电压施加到芯片的电极部分的至少一个绝缘部分；以及
以预定高度形成在导电部分的表面上并键合到芯片的电极部分的多个突起。
2.根据权利要求1所述的芯片安装衬底，其中，从导电部分向内下陷并且配置成提供在其中安装芯片的空间的腔形成在导电部分中，芯片安装在腔内。
3.根据权利要求2所述的芯片安装衬底，其中，突起以预定高度形成在具有腔的导电部分的表面上并且键合到芯片的电极部分。
4.根据权利要求2所述的芯片安装衬底，其中，芯片的电极部分形成在芯片的面对具有腔的导电部分的表面的一个表面上，并且突起键合到形成在芯片的面对具有腔的导电部分的表面的一个表面上的电极部分。
5.根据权利要求1所述的芯片安装衬底，还包括：
焊料，所述焊料形成在突起的表面上以将突起焊接到芯片的电极部分。
6.根据权利要求1所述的芯片安装衬底，还包括：
标记部分，所述标记部分跨越绝缘部分形成在导电部分的表面上以指示形成突起的位置。
7.根据权利要求2所述的芯片安装衬底，其中，具有预定深度的凹陷形成在腔内，并且突起以预定高度形成在凹陷内的导电部分的表面上并且键合到芯片的电极部分。
8.根据权利要求1所述的芯片安装衬底，还包括：
电镀层，所述电镀层以预定高度形成在由绝缘部分隔离的导电部分的表面上并且配置成将导电部分键合到突起。
9.一种芯片封装，包括：
芯片；以及
芯片安装衬底，所述芯片安装衬底包括：配置成将电极电压施加到具有电极部分的芯片的多个导电部分、配置成将导电部分电隔离以便将电极电压施加到芯片的电极部分的至少一个绝缘部分以及以预定高度形成在导电部分的表面上并键合到芯片的电极部分的多个突起。
10.根据权利要求9所述的芯片封装，还包括：
形成在芯片和芯片安装衬底之间的空间中的包封部分，该包封部分通过将突起键合到芯片的电极部分而形成，
其中，包封部分配置成包封芯片的键合区域。
11.根据权利要求9所述的芯片封装，其中，从导电部分向内下陷并且配置成提供在其中安装芯片的空间的腔形成在导电部分中，芯片安装在腔内。
12.根据权利要求11所述的芯片封装，其中，突起以预定高度形成在具有腔的导电部分的表面上并且键合到芯片的电极部分。
13.根据权利要求12所述的芯片封装，其中，芯片的电极部分形成在芯片的面对具有腔的导电部分的表面的一个表面上，并且突起键合到形成在芯片的面对具有腔的导电部分的表面的一个表面上的电极部分。
14.根据权利要求9所述的芯片封装，其中，芯片安装衬底还包括焊料，所述焊料形成在突起的表面上以将突起焊接到芯片的电极部分。
15.根据权利要求9所述的芯片封装，其中，芯片安装衬底还包括跨越绝缘部分形成在导电部分的表面上以指示形成突起的位置的标记部分。
16.根据权利要求11所述的芯片封装，其中，具有预定深度的凹陷形成在腔内，并且突起以预定高度形成在凹陷内导电部分的表面上并且键合到芯片的电极部分。
17.根据权利要求9所述的芯片封装，其中，芯片安装衬底还包括以预定高度形成在由绝缘部分隔离的导电部分的表面上并且配置成将导电部分键合到突起的电镀层。
18.根据权利要求11所述的芯片封装，还包括：
配置成密封安装在腔内的芯片的密封元件。
CN201480051090.5A 2013-09-17 2014-09-17 用于安装芯片的衬底和芯片封装 Pending CN105580130A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR20130111578A KR20150031849A (ko) 2013-09-17 2013-09-17 칩 실장용 기판 및 칩 패키지
KR10-2013-0111578 2013-09-17
PCT/KR2014/008641 WO2015041456A1 (ko) 2013-09-17 2014-09-17 칩 실장용 기판 및 칩 패키지

Publications (1)

Publication Number Publication Date
CN105580130A true CN105580130A (zh) 2016-05-11

Family

ID=52689067

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480051090.5A Pending CN105580130A (zh) 2013-09-17 2014-09-17 用于安装芯片的衬底和芯片封装

Country Status (4)

Country Link
US (1) US9673367B2 (zh)
KR (1) KR20150031849A (zh)
CN (1) CN105580130A (zh)
WO (1) WO2015041456A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111129272A (zh) * 2018-10-31 2020-05-08 台湾爱司帝科技股份有限公司 发光二极管芯片的固接方法及固接装置
CN113644185A (zh) * 2021-07-14 2021-11-12 深圳市定千亿电子有限公司 一种led芯片支架及led灯珠

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7111950B2 (ja) * 2018-04-17 2022-08-03 日亜化学工業株式会社 発光装置及びその製造方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003303999A (ja) * 2002-04-05 2003-10-24 Citizen Electronics Co Ltd 表面実装型発光ダイオード
JP2004119981A (ja) * 2002-09-27 2004-04-15 Kokuren Koden Kagi Kofun Yugenkoshi 高パワー発光ダイオードの平面実装構造、及びその製造方法
US20050242362A1 (en) * 2001-08-09 2005-11-03 Matsushita Electric Industrial Co., Ltd. Card-type LED illumination source
KR100650263B1 (ko) * 2005-11-24 2006-11-27 엘지전자 주식회사 발광 소자 패키지 및 그의 제조 방법
CN101225938A (zh) * 2007-01-18 2008-07-23 优利科技股份有限公司 利用模内转印薄膜射出/挤出成型的发光二极管灯罩
US20090206358A1 (en) * 2008-02-20 2009-08-20 Advanced Optoelectronic Technology Inc. Package structure of compound semiconductor device and fabricating method thereof
CN101567411A (zh) * 2009-05-26 2009-10-28 晶科电子（广州）有限公司 发光二极管倒装焊集成封装结构及制作方法
CN101877382A (zh) * 2009-04-28 2010-11-03 Lg伊诺特有限公司 发光器件封装和包括该发光器件封装的照明系统
US20160247781A1 (en) * 2015-02-24 2016-08-25 SK Hynix Inc. Semiconductor packages

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008172113A (ja) * 2007-01-15 2008-07-24 Ngk Spark Plug Co Ltd 配線基板

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050242362A1 (en) * 2001-08-09 2005-11-03 Matsushita Electric Industrial Co., Ltd. Card-type LED illumination source
JP2003303999A (ja) * 2002-04-05 2003-10-24 Citizen Electronics Co Ltd 表面実装型発光ダイオード
JP2004119981A (ja) * 2002-09-27 2004-04-15 Kokuren Koden Kagi Kofun Yugenkoshi 高パワー発光ダイオードの平面実装構造、及びその製造方法
KR100650263B1 (ko) * 2005-11-24 2006-11-27 엘지전자 주식회사 발광 소자 패키지 및 그의 제조 방법
CN101225938A (zh) * 2007-01-18 2008-07-23 优利科技股份有限公司 利用模内转印薄膜射出/挤出成型的发光二极管灯罩
US20090206358A1 (en) * 2008-02-20 2009-08-20 Advanced Optoelectronic Technology Inc. Package structure of compound semiconductor device and fabricating method thereof
CN101877382A (zh) * 2009-04-28 2010-11-03 Lg伊诺特有限公司 发光器件封装和包括该发光器件封装的照明系统
CN101567411A (zh) * 2009-05-26 2009-10-28 晶科电子（广州）有限公司 发光二极管倒装焊集成封装结构及制作方法
US20160247781A1 (en) * 2015-02-24 2016-08-25 SK Hynix Inc. Semiconductor packages

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111129272A (zh) * 2018-10-31 2020-05-08 台湾爱司帝科技股份有限公司 发光二极管芯片的固接方法及固接装置
CN111129272B (zh) * 2018-10-31 2021-03-16 台湾爱司帝科技股份有限公司 发光二极管芯片的固接方法及固接装置
CN113644185A (zh) * 2021-07-14 2021-11-12 深圳市定千亿电子有限公司 一种led芯片支架及led灯珠
CN113644185B (zh) * 2021-07-14 2023-12-29 深圳市源科光电有限公司 一种led芯片支架及led灯珠

Also Published As

Publication number Publication date
US9673367B2 (en) 2017-06-06
WO2015041456A1 (ko) 2015-03-26
KR20150031849A (ko) 2015-03-25
US20160211428A1 (en) 2016-07-21

Similar Documents

Publication Publication Date Title
US7960820B2 (en) Semiconductor package
CN102473813B (zh) 发光装置及其制造方法
CN104465412B (zh) 芯片封装及其制造方法和芯片组件及其制造方法
JP2019220726A (ja) 波長変換材料の気密シールを有するｌｅｄモジュール
KR101574135B1 (ko) 칩 실장 방법 및 칩 패키지
US20080169480A1 (en) Optoelectronic device package and packaging method thereof
US20170148966A1 (en) Surface-Mountable Semiconductor Component and Method for Producing Same
CN104937733B (zh) 用于制造多个光电子器件的方法和光电子器件
US8710513B2 (en) Light-emitting device package and method of manufacturing the same
US20120286308A1 (en) Led package structure and method of fabricating the same
TW201306194A (zh) 晶圓級封裝結構及其製作方法
TWI555227B (zh) 側向發光二極體及其封裝方法
CN105934834A (zh) 半导体器件和用于制造半导体器件的方法
CN103348498A (zh) 用于制造至少一个光电子半导体器件的方法
JP2005327820A (ja) 発光ダイオード用パッケージおよびそれを用いた発光装置およびその発光装置の製造方法
JP2016535937A (ja) Ｌｅｄを取り囲む全内部反射レイヤを伴うｌｅｄのためのサブストレート
US20180053883A1 (en) Light-emitting device and method of manufacturing the same
US9673367B2 (en) Substrate for mounting chip and chip package
TWI406435B (zh) 發光二極體製造方法
CN107123721A (zh) 一种带透镜式led封装结构及封装方法
CN103855282A (zh) 一种led
JP6105638B2 (ja) 発光装置の製造方法及び発光装置
CN100444357C (zh) 芯片封装结构
TWI400823B (zh) 發光二極體封裝結構及其製造方法
TWI425658B (zh) 發光二極體封裝結構及其製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20160511

WD01 Invention patent application deemed withdrawn after publication