CN105553431A - Control circuit and control method for delayed amplification component - Google Patents
Control circuit and control method for delayed amplification component Download PDFInfo
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Abstract
The invention discloses a control circuit for a delayed amplification component. The control circuit comprises a time sequence control circuit, a switch drive control circuit and a power supply modulation circuit; the time sequence control circuit receives data and a time sequence from a previous-level wave control extension, analyzes and judges the data and the time sequence, and then distributes to a next-level circuit according to an appointed time sequence relationship; the switch drive control circuit receives the data distributed by the time sequence control circuit, and controls and communicates the corresponding delay amount in the delayed amplification component according to the data combination relationship; and the power supply modulation circuit receives the data distributed by the time sequence control circuit, and judges whether power supply power is distributed to a transceiving amplification module in the delayed amplification component or not according to the appointed data relationship. The invention further provides a control method for the delayed amplification component. The control circuit and control method for the delayed amplification component disclosed by the invention have the advantages that: the problems of being low in expandability, single in control time sequence combination, non-flexible in various delay state control and high in static power consumption in the existing control circuit can be solved; free combination of the control time sequence is realized; and the control circuit disclosed by the invention has the advantages of being complementary in control of various delay state single-circuits, low in static power consumption and the like.
Description
Technical field
The present invention relates to a kind of control circuit, in particular a kind of time delay amplifier module control circuit and control method.
Background technology
Along with more and more higher to the identification requirement of target, phased array radar system just towards broadband, the future development of large-angle scanning, wide aperture array.Based on the phased array antenna system that phase shift wave beam controls, in bandwidth of operation, first, along with the increasing of signal frequency shift centre frequency, and the increase of scan angle, what controlling antenna wave beam to point produced departs from the linear increase of meeting; Secondly, when the bore array of phased array antenna increases, its aperture fill time also can become large, loss when causing each cell signal to synthesize.In order to overcome that this phase shift wave beam controls to bring to the restriction of instantaneous bandwidth of operation and the loss of gain, desirable mode be in feeding network the joining day postpone, namely increase time delay amplifier module in an array.
Time delay amplifier module is that the radiofrequency signal for inputting postpones a period of time, then exports after certain amplification.It is not only required in passband radiofrequency characteristicses such as having smooth width Entropy density deviation, and requires that the ripple control extension set self adaptation had upper level is strong, and can control it flexibly, quiescent dissipation requires the features such as little.
Time delay amplifier module is made up of three parts, i.e. control circuit, delay line, transmitting-receiving amplification module.Control circuit mainly receives the time series data of higher level's ripple control extension set to control the conversion of delay line between benchmark state and each time delay state, and control transmitting-receiving amplification module is mutually changed between launching and receiving, and block the power supply of power supply to whole assembly when time delay amplifier module is in and does not need work.
For the time series data receiving the distribution of higher level's ripple control extension set, first data latch by time delay amplifier module control circuit, then select according to the state of a transmitting-receiving control signal TR data exporting data or the reception of launching.The major defect of this circuit is fixing a kind of sequential for the transmitting-receiving sequential of input, do not have selectivity and compatibility.Only have transmitting and receiving two states in sequential, in transmitting-receiving this moment of conversion, owing to having the relation of front and back along time delay in circuit, likely there will be a kind of uncertain state in this moment, cause the confusion of circuit or burn.
For the control that time delay amplifier module is changed between benchmark state and each time delay state, some methods are to make delay line conducting on one side another side disconnect, at circuit while add inverter to facilitate control (Du Jiangkun, Song Qinghui, Zhao Botao, " the miniaturized delayer design based on LTCC technology " radio engineering 2013,43 (8): 62-64).This method can cause the switching of double switch asynchronous, postpones if having time, and increases the complexity of circuit.And in circuit, only there is benchmark state and time delay state two states.Because only have two states, so a kind of state also must be had to be the state being in work when assembly does not work, cause unnecessary quiescent dissipation.
In a word, all there is Control timing sequence in just current time delay amplifier module control circuit single, this just makes circuit in use Existence and uniquenss, in other equipment, change a kind of Control timing sequence, and just again must develop a control circuit, its commonality is not strong.Receive and dispatch between conversion and do not cushion, quiescent dissipation is large, and these disadvantageous factors seem particularly outstanding at airborne, satellite borne equipment in applying.
Summary of the invention
Technical problem to be solved by this invention there are provided a kind ofly freely can adapt to various input control sequential combination, export complementary to control, accurately control assembly amount of delay, send out conversion arrange buffering excessively, time delay amplifier module control circuit that quiescent dissipation is little.
The present invention solves the problems of the technologies described above by the following technical programs: a kind of time delay amplifier module control circuit, for controlling time delay amplifier module, described time delay amplifier module control circuit comprises sequential control circuit, switch drive control circuit, power supply modulator circuit;
Described sequential control circuit receives logical data and the sequential of the distribution of upper level ripple control extension set, comprise: data SD, clock SC, gate CP, refreshing SYN, transmitting T, reception R, according to launching T and receiving the sequential relationship of R, carry out resolving, judge after data are exported the circuit giving next stage; Described switch drive control circuit receives the data of distributing from sequential control circuit, according to the syntagmatic of data, controls and is communicated with corresponding amount of delay in time delay amplifier module; Described power supply modulator circuit receives the data of distributing from sequential control circuit, according to the data relationship of agreement, judges whether to the transmitting-receiving amplification module power distribution power in time delay amplifier module.
Concrete, two sequential are set in described sequential control circuit and select signal PUL1, PUL2, by changing the low and high level that two sequential select signal PUL1, PUL2 to connect, adapting to the transmitting T of combination in any and receiving the sequential logic of R;
Described sequential control circuit, export double switch composite signal SW1, SW2, for controlling the transmitting-receiving conversion of receiving and dispatching amplification module, described time delay amplifier module comprises delay switch and transmitting-receiving amplification module, described transmitting-receiving amplification module comprises transmit-receive switch and is connected to transmitting branch and the receiving branch of transmit-receive switch, transmit-receive switch is connected to delay switch, transmit-receive switch is tri-state switch, control with double switch composite signal SW1, SW2, transmitting-receiving amplification module is operated in respectively and launches state, reception state and load state;
Described power supply modulator circuit is connected respectively to described transmitting branch and receiving branch, described sequential control circuit, export two groups of power modulation signals T-OUT, R-OUT to power supply modulator circuit, when launching work, close the power supply of receiving branch, close the power supply of transmitting branch when the work of reception.
Concrete, described switch drive control circuit, single channel input complementary output, controls the benchmark state of delay line and the complementary duty of time delay state respectively, an enable signal EN is wherein set in switch drive control circuit, the closeall delay line operating state when time delay amplifier module does not work.
Concrete, described sequential control circuit, right+5V ,-5V voltage carry out under-voltage fault and judge, carry out parity check to data SD.
Concrete, its work schedule is: when launching T sequential and receive R sequential simultaneously for high level, make time delay amplifier module be operated in emission state, and control circuit turns off the power supply of receiving branch; When transmitting T sequential and reception R sequential are low level simultaneously, make time delay amplifier module be operated in accepting state, control circuit needs the power of the transmitting branch of turn off delay time amplifier module to supply; During other sequential combination, make time delay amplifier module be operated in load state, control circuit turns off the power supply of whole radio frequency link simultaneously.
Concrete, its work schedule is: sequential selects signal PUL1 to connect high level, makes transmitting T sequential effectively high; Sequential selects signal PUL2 to connect low level, makes reception R sequential effectively low.
Concrete, sequential control circuit receives logical data and the sequential of the distribution of upper level ripple control extension set, comprise: data SD, clock SC, gate CP, refreshing SYN, transmitting T, reception R, and Logic judgment is carried out to the transmitting T received, reception R sequential combination, right+5V ,-5V supply voltage carry out under-voltage fault and judge, parity check is carried out to data SD, time wrong, sends false alarm;
During sequential control circuit self-inspection prompting inerrancy, export delays time to control code according to the condition selecting launching T sequential and give switch drive control circuit, when transmitting T sequential is high level, export emission delay control code, when transmitting T sequential is low level, export reception delay control code;
Switch drive control circuit receives the delays time to control code of sequential control circuit distribution, each delays time to control code is after switch drive control circuit modulation, export+the 5V of a pair complementation respectively, the drive singal of-5V gives delay switch, delay switch carries out the conversion between benchmark state and time delay state according to the logical relation of this pair complementary signal, namely close benchmark state opening time-delaying state or open benchmark state and close time delay state, when time delay amplifier module does not work, the enable signal EN that switch drive control circuit is sent according to sequential control circuit, turn off all delays time to control drive singal,
Sequential control circuit exports double switch composite signal SW1, SW2, control the transmitting-receiving conversion of transmit-receive switch, transmit-receive switch is a tri-state switch, switch combination signal SW1, SW2 obtains by launching T sequential and receiving R sequential combination, when transmitting T sequential and reception R sequential are high level simultaneously, switch combination signal SW1 exports high level, SW2 output low level, now transmit-receive switch is communicated with transmitting branch, when transmitting T sequential and reception R sequential are low level simultaneously, switch combination signal SW1 output low level, SW2 exports high level, now transmit-receive switch is communicated with receiving branch, launch T sequential and receive R sequential for other combine time, switch combination signal SW1 output low level, SW2 output low level, now transmit-receive switch is communicated with load branch,
Sequential control circuit exports two groups of power modulation signals T-OUT, R-OUT and controls power supply modulator circuit, power supply modulator circuit is when time delay amplifier module is operated in transmitting state, close the power supply of receiving branch, close the power supply of transmitting branch when time delay amplifier module is operated in and receives state.
As the embodiment that is optimized, a data from overflow SDout interface is set in described sequential control circuit, in multichannel assembly or when needing the data bit that simultaneously controls many, directly carries out cascade expansion.
The present invention also provides a kind of time delay amplifier module control method, for controlling time delay amplifier module, it is characterized in that, this time delay amplifier module control method uses time delay amplifier module control circuit to control time delay amplifier module, described time delay amplifier module control circuit comprises sequential control circuit, switch drive control circuit, time delay amplifier module, power supply modulator circuit, described sequential control circuit receives logical data and the sequential of the distribution of upper level ripple control extension set, comprise: data SD, clock SC, gate CP, refresh SYN, launch T, receive R, according to the sequential relationship of launching T and reception R, resolve, after judgement, data are exported the circuit giving next stage, described switch drive control circuit receives the data of distributing from sequential control circuit, according to the syntagmatic of data, controls and is communicated with corresponding amount of delay in time delay amplifier module, described power supply modulator circuit receives the data of distributing from sequential control circuit, according to the data relationship of agreement, judges whether to the transmitting-receiving amplification module power distribution power in time delay amplifier module.
As a concrete example, this time delay amplifier module control method comprises the steps:
Sequential control circuit receives logical data and the sequential of the distribution of upper level ripple control extension set, comprise: data SD, clock SC, gate CP, refreshing SYN, transmitting T, reception R, and Logic judgment is carried out to the transmitting T received, reception R sequential combination, right+5V ,-5V supply voltage carry out under-voltage fault and judge, parity check is carried out to data SD, time wrong, sends false alarm;
During sequential control circuit self-inspection prompting inerrancy, export delays time to control code according to the condition selecting launching T sequential and give switch drive control circuit, when transmitting T sequential is high level, export emission delay control code, when transmitting T sequential is low level, export reception delay control code;
Described time delay amplifier module comprises delay switch and transmitting-receiving amplification module, described transmitting-receiving amplification module comprises transmit-receive switch and is connected to transmitting branch and the receiving branch of transmit-receive switch, transmit-receive switch is connected to delay switch, switch drive control circuit receives the delays time to control code of sequential control circuit distribution, each delays time to control code is after switch drive control circuit modulation, export+the 5V of a pair complementation respectively, the drive singal of-5V gives delay switch, delay switch carries out the conversion between benchmark state and time delay state according to the logical relation of this pair complementary signal, namely close benchmark state opening time-delaying state or open benchmark state and close time delay state, when time delay amplifier module does not work, the enable signal EN that switch drive control circuit is sent according to sequential control circuit, turn off all delays time to control drive singal,
Sequential control circuit exports double switch composite signal SW1, SW2, control the transmitting-receiving conversion of transmit-receive switch, transmit-receive switch is a tri-state switch, switch combination signal SW1, SW2 obtains by launching T sequential and receiving R sequential combination, when transmitting T sequential and reception R sequential are high level simultaneously, switch combination signal SW1 exports high level, SW2 output low level, now transmit-receive switch is communicated with transmitting branch, when transmitting T sequential and reception R sequential are low level simultaneously, switch combination signal SW1 output low level, SW2 exports high level, now transmit-receive switch is communicated with receipts receiving branch, launch T sequential and receive R sequential for other combine time, switch combination signal SW1 output low level, SW2 output low level, now transmit-receive switch is communicated with load branch,
Sequential control circuit exports two groups of power modulation signals T-OUT, R-OUT and controls power supply modulator circuit, power supply modulator circuit is when time delay amplifier module is operated in transmitting state, close the power supply of receiving branch, close the power supply of transmitting branch when time delay amplifier module is operated in and receives state.
The present invention has the following advantages compared to existing technology: the commonality considering control circuit fully, arranges sequential and selects signal, can adapt to various different sequential logic in control circuit.In distinct device, when sequential logic is not identical, do not need again to develop new circuit, only need to change the logical combination that sequential selects signal, compare its commonality with other circuit strong, the development cost of novel circuit can be saved.
Owing to being provided with enable EN control port in the switch drive control circuit of delay line, making time delay amplifier module when not working, can cut off the electricity supply to the power supply of delay line part, reducing the quiescent dissipation of assembly relative to other circuit greatly.Transmitting-receiving conversion and control uses two paths of signals to combine control, increase the load state of an intermediate buffering conversion, make the reliability of assembly higher.On power modulation controls, all use complementary output, can according to different user demands, the power of the branch road of modulation transmitting-receiving flexibly.
Because this control circuit is provided with data from overflow SDout interface, in multichannel assembly or when needing the data bit that simultaneously controls many, directly can carry out cascade use, not need to increase extra circuit.
Whole time delay amplifier module control circuit is compared with other control circuits, and structure is simple, and external interface connects freely, and internal control connects flexibly, and reliability is high, is convenient to expansion design.
Accompanying drawing explanation
The general frame figure of the time delay amplifier module control circuit that Fig. 1 embodiment of the present invention 1 provides;
The expansion design framework figure of the time delay amplifier module control circuit that Fig. 2 embodiment of the present invention 2 provides.
Embodiment
Elaborate to embodiments of the invention below, the present embodiment is implemented under premised on technical solution of the present invention, give detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
Embodiment 1:
See Fig. 1, a preferred embodiment is the control circuit of C-band time delay amplifier module, and its assembly needs to realize 5 bit digital time delays.Work schedule is: when launching T sequential and receive R sequential simultaneously for high level, make component operation at emission state, control circuit needs the power supply turning off receiving branch; When transmitting T sequential and reception R sequential are low level simultaneously, make component operation in accepting state, control circuit needs the power supply turning off transmitting branch; During other sequential combination, make component operation in load state, control circuit needs the power supply simultaneously turning off whole radio frequency link.
Described time delay amplifier module control circuit mainly comprises sequential control circuit 1, switch drive control circuit 2, power supply modulator circuit 3.Time delay amplifier module comprises delay switch 6, transmit-receive switch 7 and transmitting branch 8 and receiving branch 9.
In the present embodiment, when transmitting T sequential and reception R sequential are high level simultaneously, make component operation at emission state; When transmitting T sequential and reception R sequential are low level simultaneously, make component operation in accepting state.So sequential selects signal PUL1 to connect high level, make transmitting T sequential effectively high; Sequential selects signal PUL2 to connect low level, makes reception R sequential effectively low.
Sequential control circuit 1 receives logical data and the sequential of the distribution of upper level ripple control extension set, comprising: data SD, clock SC, gate CP, refreshing SYN, transmitting T, reception R.And Logic judgment is carried out to the transmitting T received, reception R sequential combination; Right+5V ,-5V supply voltage carry out under-voltage fault and judge; Parity check is carried out to data SD, time wrong, sends false alarm.
During sequential control circuit 1 self-inspection prompting inerrancy, export delays time to control code according to the condition selecting launching T sequential and give switch drive control circuit 2.When transmitting T sequential is high level, export emission delay control code; When transmitting T sequential is low level, export reception delay control code.
Switch drive control circuit 2 receives the delays time to control code that sequential control circuit 1 is distributed, each delays time to control code is after switch drive control circuit 2 is modulated, export+the 5V of a pair complementation respectively, the drive singal of-5V gives delay switch 6, delay switch 6 carries out the conversion between benchmark state 4 and time delay state 5 according to the logical relation of this pair complementary signal, namely closes benchmark state 4 opening time-delaying state 5 or opens benchmark state 4 and close time delay state 5.When time delay amplifier module does not work, the enable signal EN that switch drive control circuit 2 is sent according to sequential control circuit 1, turns off all delays time to control drive singal.
Sequential control circuit 1 exports double switch composite signal SW1, SW2, and control the transmitting-receiving conversion of transmit-receive switch 7, transmit-receive switch 7 is a tri-state switch.Switch combination signal SW1, SW2 obtain by launching T sequential and receiving R sequential combination.When launching T sequential in the present embodiment and receive R sequential simultaneously for high level, switch combination signal SW1 exports high level, SW2 output low level, and now transmit-receive switch 7 is communicated with the transmitting branch 8 in transmitting-receiving amplification module; When transmitting T sequential and reception R sequential are low level simultaneously, switch combination signal SW1 output low level, SW2 exports high level, and now transmit-receive switch 7 is communicated with the receiving branch 9 in transmitting-receiving amplification module; Launch T sequential and receive R sequential for other combine time, switch combination signal SW1 output low level, SW2 output low level, the load branch in amplification module is received and dispatched in now transmit-receive switch 7 connection.
Sequential control circuit 1 exports two groups of power modulation signals T-OUT, R-OUT and controls power supply modulator circuit 3.Power supply modulator circuit 3, when time delay amplifier module is operated in transmitting state, closes the power supply of receiving branch 9; The power supply of transmitting branch 8 is closed when time delay amplifier module is operated in and receives state.Each group power modulation signal has the two paths of signals of a pair complementation to export, and can select according to the need of work of reality.
Embodiment 2:
See Fig. 2, another preferred embodiment of the present invention is a binary channels time delay amplifier module control circuit.By two sequential control circuits, in inside, direct cascade forms this control circuit, and the data from overflow port of first sequential control circuit directly links the data input port of second sequential control circuit.This circuit shares a sequential and FPDP, when multichannel connects, can save external interface and the quantity of transmission cable greatly, reduces the volume of device.
Above content elaborated to the present invention in conjunction with concrete preferred implementation, can not assert that the present invention specifically implements to be only limitted to these explanations.For the technical staff of technical field that the present invention belongs to; without departing from the inventive concept of the premise; some simple deductions and replacement can also being made, as increased the control figure place etc. of delay line, all should be considered as belonging to the invention protection range that the present invention is determined by submitted to claims.
Claims (10)
1. a time delay amplifier module control circuit, for controlling time delay amplifier module, is characterized in that, described time delay amplifier module control circuit comprises sequential control circuit, switch drive control circuit, power supply modulator circuit;
Described sequential control circuit receives logical data and the sequential of the distribution of upper level ripple control extension set, comprise: data SD, clock SC, gate CP, refreshing SYN, transmitting T, reception R, according to launching T and receiving the sequential relationship of R, carry out resolving, judge after data are exported the circuit giving next stage; Described switch drive control circuit receives the data of distributing from sequential control circuit, according to the syntagmatic of data, controls and is communicated with corresponding amount of delay in time delay amplifier module; Described power supply modulator circuit receives the data of distributing from sequential control circuit, according to the data relationship of agreement, judges whether to the transmitting-receiving amplification module power distribution power in time delay amplifier module.
2. a kind of time delay amplifier module control circuit according to claim 1, it is characterized in that, two sequential are set in described sequential control circuit and select signal PUL1, PUL2, by changing the low and high level that two sequential select signal PUL1, PUL2 to connect, adapting to the transmitting T of combination in any and receiving the sequential logic of R;
Described sequential control circuit, export double switch composite signal SW1, SW2, for controlling the transmitting-receiving conversion of receiving and dispatching amplification module, described time delay amplifier module comprises delay switch and transmitting-receiving amplification module, described transmitting-receiving amplification module comprises transmit-receive switch and is connected to transmitting branch and the receiving branch of transmit-receive switch, transmit-receive switch is connected to delay switch, transmit-receive switch is tri-state switch, control with double switch composite signal SW1, SW2, transmitting-receiving amplification module is operated in respectively and launches state, reception state and load state;
Described power supply modulator circuit is connected respectively to described transmitting branch and receiving branch, described sequential control circuit, export two groups of power modulation signals T-OUT, R-OUT to power supply modulator circuit, when launching work, close the power supply of receiving branch, close the power supply of transmitting branch when the work of reception.
3. a kind of time delay amplifier module control circuit according to claim 2, it is characterized in that, described switch drive control circuit, single channel input complementary output, control the benchmark state of delay line and the complementary duty of time delay state respectively, an enable signal EN is wherein set in switch drive control circuit, the closeall delay line operating state when time delay amplifier module does not work.
4. a kind of time delay amplifier module control circuit according to claim 2, it is characterized in that, described sequential control circuit, right+5V ,-5V voltage carry out under-voltage fault and judge, carry out parity check to data SD.
5. a kind of time delay amplifier module control circuit according to claim 2, it is characterized in that, its work schedule is: when launching T sequential and receive R sequential simultaneously for high level, make time delay amplifier module be operated in emission state, and control circuit turns off the power supply of receiving branch; When transmitting T sequential and reception R sequential are low level simultaneously, make time delay amplifier module be operated in accepting state, control circuit needs the power of the transmitting branch of turn off delay time amplifier module to supply; During other sequential combination, make time delay amplifier module be operated in load state, control circuit turns off the power supply of whole radio frequency link simultaneously.
6. a kind of time delay amplifier module control circuit according to claim 5, it is characterized in that, its work schedule is: sequential selects signal PUL1 to connect high level, makes transmitting T sequential effectively high; Sequential selects signal PUL2 to connect low level, makes reception R sequential effectively low.
7. a kind of time delay amplifier module control circuit according to claim 5, it is characterized in that, sequential control circuit receives logical data and the sequential of the distribution of upper level ripple control extension set, comprise: data SD, clock SC, gate CP, refreshing SYN, transmitting T, reception R, and Logic judgment is carried out to the transmitting T received, reception R sequential combination, right+5V ,-5V supply voltage carry out under-voltage fault and judge, carry out parity check, send false alarm time wrong to data SD;
During sequential control circuit self-inspection prompting inerrancy, export delays time to control code according to the condition selecting launching T sequential and give switch drive control circuit, when transmitting T sequential is high level, export emission delay control code, when transmitting T sequential is low level, export reception delay control code;
Switch drive control circuit receives the delays time to control code of sequential control circuit distribution, each delays time to control code is after switch drive control circuit modulation, export+the 5V of a pair complementation respectively, the drive singal of-5V gives delay switch, delay switch carries out the conversion between benchmark state and time delay state according to the logical relation of this pair complementary signal, namely close benchmark state opening time-delaying state or open benchmark state and close time delay state, when time delay amplifier module does not work, the enable signal EN that switch drive control circuit is sent according to sequential control circuit, turn off all delays time to control drive singal,
Sequential control circuit exports double switch composite signal SW1, SW2, control the transmitting-receiving conversion of transmit-receive switch, transmit-receive switch is a tri-state switch, switch combination signal SW1, SW2 obtains by launching T sequential and receiving R sequential combination, when transmitting T sequential and reception R sequential are high level simultaneously, switch combination signal SW1 exports high level, SW2 output low level, now transmit-receive switch is communicated with transmitting branch, when transmitting T sequential and reception R sequential are low level simultaneously, switch combination signal SW1 output low level, SW2 exports high level, now transmit-receive switch is communicated with receiving branch, launch T sequential and receive R sequential for other combine time, switch combination signal SW1 output low level, SW2 output low level, now transmit-receive switch is communicated with load branch,
Sequential control circuit exports two groups of power modulation signals T-OUT, R-OUT and controls power supply modulator circuit, power supply modulator circuit is when time delay amplifier module is operated in transmitting state, close the power supply of receiving branch, close the power supply of transmitting branch when time delay amplifier module is operated in and receives state.
8. a kind of time delay amplifier module control circuit according to claim 1, it is characterized in that, a data from overflow SDout interface is set in described sequential control circuit, in multichannel assembly or when needing the data bit that simultaneously controls many, directly carries out cascade expansion.
9. a time delay amplifier module control method, for controlling time delay amplifier module, it is characterized in that, this time delay amplifier module control method uses time delay amplifier module control circuit to control time delay amplifier module, described time delay amplifier module control circuit comprises sequential control circuit, switch drive control circuit, time delay amplifier module, power supply modulator circuit, described sequential control circuit receives logical data and the sequential of the distribution of upper level ripple control extension set, comprise: data SD, clock SC, gate CP, refresh SYN, launch T, receive R, according to the sequential relationship of launching T and reception R, resolve, after judgement, data are exported the circuit giving next stage, described switch drive control circuit receives the data of distributing from sequential control circuit, according to the syntagmatic of data, controls and is communicated with corresponding amount of delay in time delay amplifier module, described power supply modulator circuit receives the data of distributing from sequential control circuit, according to the data relationship of agreement, judges whether to the transmitting-receiving amplification module power distribution power in time delay amplifier module.
10. a kind of time delay amplifier module control method according to claim 9, is characterized in that, specifically comprise the steps:
Sequential control circuit receives logical data and the sequential of the distribution of upper level ripple control extension set, comprise: data SD, clock SC, gate CP, refreshing SYN, transmitting T, reception R, and Logic judgment is carried out to the transmitting T received, reception R sequential combination, right+5V ,-5V supply voltage carry out under-voltage fault and judge, parity check is carried out to data SD, time wrong, sends false alarm;
During sequential control circuit self-inspection prompting inerrancy, export delays time to control code according to the condition selecting launching T sequential and give switch drive control circuit, when transmitting T sequential is high level, export emission delay control code, when transmitting T sequential is low level, export reception delay control code;
Described time delay amplifier module comprises delay switch and transmitting-receiving amplification module, described transmitting-receiving amplification module comprises transmit-receive switch and is connected to transmitting branch and the receiving branch of transmit-receive switch, transmit-receive switch is connected to delay switch, switch drive control circuit receives the delays time to control code of sequential control circuit distribution, each delays time to control code is after switch drive control circuit modulation, export+the 5V of a pair complementation respectively, the drive singal of-5V gives delay switch, delay switch carries out the conversion between benchmark state and time delay state according to the logical relation of this pair complementary signal, namely close benchmark state opening time-delaying state or open benchmark state and close time delay state, when time delay amplifier module does not work, the enable signal EN that switch drive control circuit is sent according to sequential control circuit, turn off all delays time to control drive singal,
Sequential control circuit exports double switch composite signal SW1, SW2, control the transmitting-receiving conversion of transmit-receive switch, transmit-receive switch is a tri-state switch, switch combination signal SW1, SW2 obtains by launching T sequential and receiving R sequential combination, when transmitting T sequential and reception R sequential are high level simultaneously, switch combination signal SW1 exports high level, SW2 output low level, now transmit-receive switch is communicated with transmitting branch, when transmitting T sequential and reception R sequential are low level simultaneously, switch combination signal SW1 output low level, SW2 exports high level, now transmit-receive switch is communicated with receipts receiving branch, launch T sequential and receive R sequential for other combine time, switch combination signal SW1 output low level, SW2 output low level, now transmit-receive switch is communicated with load branch,
Sequential control circuit exports two groups of power modulation signals T-OUT, R-OUT and controls power supply modulator circuit, power supply modulator circuit is when time delay amplifier module is operated in transmitting state, close the power supply of receiving branch, close the power supply of transmitting branch when time delay amplifier module is operated in and receives state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610082895.7A CN105553431B (en) | 2016-02-03 | 2016-02-03 | A kind of delay amplifier module control circuit and control method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610082895.7A CN105553431B (en) | 2016-02-03 | 2016-02-03 | A kind of delay amplifier module control circuit and control method |
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| CN105553431A true CN105553431A (en) | 2016-05-04 |
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| CN109901125A (en) * | 2019-03-11 | 2019-06-18 | 中国电子科技集团公司第三十八研究所 | A kind of airborne two-dimentional Connectors for Active Phased Array Radar antenna calibration device and method |
| CN111193524A (en) * | 2018-11-14 | 2020-05-22 | 广东新岸线计算机系统芯片有限公司 | Portable analyzer for ultra-high-speed wireless local area network |
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| CN111193524A (en) * | 2018-11-14 | 2020-05-22 | 广东新岸线计算机系统芯片有限公司 | Portable analyzer for ultra-high-speed wireless local area network |
| CN109901125A (en) * | 2019-03-11 | 2019-06-18 | 中国电子科技集团公司第三十八研究所 | A kind of airborne two-dimentional Connectors for Active Phased Array Radar antenna calibration device and method |
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