CN105552126A - Finned-type field effect transistor and fabrication method thereof - Google Patents

Abstract

The invention provides a fin field effect transistor structure and a preparation method thereof, comprising: a silicon substrate, a fin structure on the silicon substrate, a gate insulating layer and a gate electrode on the fin structure; The middle part of the fin structure is a double-layer structure, which forms a double-layer channel structure; the upper layer of the double-layer structure is the upper channel, and the lower layer is the lower channel; the two ends of the fin structure are single-layer structures, And there is an insulating medium between the single-layer structure and the silicon substrate; the single-layer structure constitutes the source-drain extension region. In the present invention, by isolating the source-drain extension region and the silicon substrate through an insulating medium, the leakage channel between the source and drain of the device and between the device and the device is effectively blocked, the leakage current is reduced, and the latch-up effect is effectively avoided; on the other hand, , the upper channel and the substrate are connected through the semiconductor material of the lower channel, the heat dissipation performance is good, and the self-heating effect is avoided. Moreover, the method of the present invention has low cost and simple and controllable process.

Description

Fin field effect transistor and its manufacturing method

technical field

The invention relates to the technical field of semiconductors, in particular to a fin field effect transistor and a preparation method thereof.

Background technique

For more than half a century, the rapid development of the integrated circuit industry has provided hardware guarantee for the information age. MOS devices are important components in the field of integrated circuits. In 1925, J. Lilienfield proposed the basic principles behind field effect transistors. In 1948, the first field effect transistor was born in the laboratory. Scaling down of devices has been going on throughout the history of integrated circuits because of the benefits of higher on-state current, higher speed, and smaller area that smaller-sized devices can bring.

However, when the feature size of traditional MOS devices is reduced to the nanometer scale, various negative effects begin to emerge. Among them, since the equivalent gate oxide thickness cannot be reduced in proportion to the device size, the coupling effect between the gate and the channel decreases. It causes many problems including short channel effect and DIBL effect, and causes the degradation of device performance. Therefore, how to suppress the short channel effect and improve the gate control ability of the device is an important issue.

From the perspective of device architecture, it is an effective solution to improve the gate control capability by changing the structure of the gate stack, and it is also the development direction of future devices. Therefore, the characteristics and future development prospects of various multi-gate device structures have been studied, such as the fin field effect transistor (FinFET) structure that has been applied in the mass production of advanced products. Since the gates are covered on both sides of the fin-shaped silicon structure, the number of gates increases, and the gate control capability is correspondingly enhanced, so that the short channel effect can be effectively suppressed, and the performance of the device can be greatly improved.

Referring to the existing fin field effect transistors that have been developed and mass-produced, as shown in FIG. An insulating layer 104 and a gate electrode 105; as shown in FIG. 1b, a fin field effect transistor based on an SOI substrate includes: an underlying silicon substrate 201, an interlayer dielectric 202, a source-drain region 203 in an upper silicon substrate, and a channel 204 , the gate insulating layer 205 and the gate electrode 206 . Generally, compared with the bulk silicon substrate, the SOI substrate completely isolates the source and drain of the device and the leakage channel between the device and the device, which can effectively avoid the latch-up effect, and the process preparation method is relatively simpler. But the disadvantages are also obvious: the cost of the silicon wafer of the SOI substrate is much higher than that of the single crystal silicon substrate, and the thermal conductivity of the buried oxide layer of the SOI substrate is poor, which is prone to self-heating effect. Therefore, if the advantages of the two can be combined to propose a more optimized device structure, it is bound to further optimize the device performance.

Contents of the invention

In order to overcome the above problems, the present invention provides a Fin Field Effect Transistor and its preparation method. The performance of the transistor is improved by setting insulating dielectric isolation between the bottom of the source-drain region extension region and the silicon substrate.

In order to achieve the above object, the present invention provides a fin field effect transistor, comprising a silicon substrate, a fin structure on the silicon substrate, and a gate insulating layer and a gate electrode on the fin structure; wherein, the The middle part of the fin structure below the gate electrode is a double-layer structure, and the double-layer structure forms a double-layer channel structure; the upper layer of the double-layer structure is an upper channel, and the lower layer is a lower channel;

Both ends of the fin structure are single-layer structures, and there is an insulating medium between the single-layer structure and the silicon substrate; the single-layer structure constitutes a source-drain extension region.

Preferably, the material of the upper channel is silicon, germanium, silicon germanium or gallium arsenide; the material of the lower channel is germanium, silicon germanium or gallium arsenide.

Preferably, the insulating medium is silicon dioxide.

Preferably, the upper channel and the single-layer structure are located in the same layer.

Preferably, an insulating dielectric layer covers the gate electrode, the gate insulating layer and the source-drain extension region.

In order to achieve the above object, the present invention also provides a method for preparing the above-mentioned fin field effect transistor, which includes:

Step 01: providing a silicon substrate;

Step 02: sequentially depositing a first semiconductor material and a second semiconductor material on the surface of the silicon substrate;

Step 03: Etching the second semiconductor material and the first semiconductor material in sequence through photolithography and etching processes, and the etching stops on the surface of the silicon substrate, thereby forming a fin structure;

Step 04: sequentially forming a gate insulating layer and a gate electrode on the fin structure; the gate insulating layer and the part of the double-layer fin structure below the gate electrode form a double-layer channel structure;

Step 05: Etching and removing the first semiconductor material at both ends of the fin structure, so that the second semiconductor material at both ends of the fin structure forms a source-drain extension region, and between the source-drain extension region and gaps are formed between the silicon substrates;

Step 06: depositing an insulating medium on the source-drain extension region and the gate electrode at both ends of the fin structure, the insulating medium covers the source-drain extension region and the gate electrode, and fills the gap;

Step 07: Executing an electrode extraction process of the gate electrode, the source-drain extension region, and the silicon substrate, thereby forming the FinFET.

Preferably, in the step 03, the etching process is a plasma dry etching process.

Preferably, the first semiconductor material is silicon germanium, and the second semiconductor material is silicon. In the step 05, the etching is wet etching, and the etching solution used is a mixed solution of hydrofluoric acid, nitric acid and acetic acid.

Preferably, the ratio of the mixed liquid is 18% hydrofluoric acid, 42% nitric acid and 80% acetic acid in a ratio of 1:2:5.

Preferably, the step 06 specifically includes: depositing an insulating medium on the silicon substrate after the step 05 is completed; and removing the insulating medium located on the surface of the silicon substrate.

Compared with the existing fin field effect transistor structure prepared based on bulk silicon and SOI substrate, the invention combines the advantages of both. On the one hand, by isolating the source-drain extension region and the silicon substrate through an insulating medium, the leakage channel between the source and drain of the device and between the device and the device is effectively blocked, the leakage current is reduced, and the latch-up effect is effectively avoided; the other is On the one hand, the upper channel and the substrate are connected through the semiconductor material of the lower channel, which has good heat dissipation performance and avoids self-heating effect. At the same time, the preparation method of the present invention is based on the realization of the bulk silicon substrate, which controls the cost of raw materials; through high selectivity etching and backfilling insulating medium to form mutually isolated source and drain extension regions and silicon substrate technology, The method is very simple and controllable.

Description of drawings

Figure 1a is a schematic diagram of the cross-sectional structure of a fin field effect transistor on an existing bulk silicon substrate

Figure 1b is a schematic cross-sectional structure diagram of a fin field effect transistor on an existing SOI substrate

Fig. 2 is a schematic cross-sectional structure diagram of a fin field effect transistor according to a preferred embodiment of the present invention

Fig. 3 is the schematic flow sheet of the preparation method of the fin field effect transistor of a preferred embodiment of the present invention

4a to 4f are schematic diagrams of each preparation step of the method for manufacturing a fin field effect transistor according to a preferred embodiment of the present invention

detailed description

In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

The fin field effect transistor of the present invention includes a silicon substrate, a fin structure on the silicon substrate, a gate insulating layer and a gate electrode on the fin structure; wherein, the middle part of the fin structure below the gate electrode It is a double-layer structure, which constitutes a double-layer channel structure; the double-layer channel structure includes an upper channel and a lower channel; both ends of the fin structure are single-layer structures, and the single-layer structure and the silicon substrate There is an insulating medium between them; the single-layer structure constitutes the source-drain extension region.

The fin field effect transistor and its manufacturing method of the present invention will be further described in detail below with reference to the accompanying drawings 2 to 4f and specific embodiments. It should be noted that the drawings are all in a very simplified form, using imprecise scales, and are only used to facilitate and clearly achieve the purpose of assisting in describing the present embodiment.

Please refer to FIG. 2. In this embodiment, the fin field effect transistor includes a silicon substrate 301, a fin structure on the silicon substrate 301, and a gate insulating layer 306 and a gate electrode 307 on the fin structure; The middle part of the fin structure is a double-layer structure, and both ends are single-layer structures; the double-layer structure corresponds to the gate electrode 307 and the gate insulating layer 306 below, as a double-layer channel structure, and the double-layer channel structure includes an upper channel 305 and the lower channel 303, the single-layer structure is used as the source-drain extension region 304; a gap is formed between the single source-drain extension region 304 and the silicon substrate 301, and the insulating medium 302 is filled in the gap, preferably, in order to protect the gate The electrode 307 and the source-drain extension region 304 are covered by an insulating dielectric layer to cover the gate electrode 307, the gate insulating layer 306 and the source-drain extension region 304;

Please refer to FIG. 3 to FIG. 4f. In this embodiment, the method for preparing the above-mentioned fin field effect transistor includes:

Step 01: Please refer to FIG. 4a, providing a silicon substrate 1;

Specifically, the material of the silicon substrate 1 is single crystal silicon.

Step 02: Please refer to FIG. 4b, sequentially depositing a first semiconductor material 2 and a second semiconductor material 3 on the surface of the silicon substrate 1;

Specifically, the first semiconductor material 2 is used as the material of the lower channel, which may be a group IV semiconductor material such as germanium, silicon germanium, or carbon silicon, or a group III and five compound semiconductor material such as gallium arsenide. The second semiconductor material 3 is used as the material of the upper channel, and the material of the upper channel is a group IV semiconductor material such as silicon, germanium, silicon germanium, or silicon carbon, or a group III and five compound semiconductor material such as gallium arsenide. The first semiconductor material 2 and the second semiconductor material 3 may be deposited by chemical vapor deposition, but not limited thereto. Preferably, the first semiconductor material 2 is silicon germanium, and the second semiconductor material 3 is silicon.

Step 03: Please refer to FIG. 4c. After photolithography and etching processes, the second semiconductor material 3 and the first semiconductor material 2 are sequentially etched, and the etching stops on the surface of the silicon substrate 1, thereby forming a fin structure;

Specifically, the etching process adopted here is a plasma dry etching process. First, apply photoresist, define the position of the fin structure by photolithography, and transfer the pattern of the mask plate to the photoresist. Then, the second semiconductor material 3 and the first semiconductor material 2 are sequentially etched using the photoresist as a mask, and the etching stops at the single crystal silicon substrate 1, thereby forming a double-layer fin structure;

Step 04: Referring to FIG. 4d, a gate insulating layer 4 and a gate electrode 5 are sequentially formed on the fin structure;

Specifically, firstly, the gate insulating layer 4 and the gate electrode 5 may be sequentially deposited by chemical vapor deposition; then, the pattern of the gate insulating layer and the gate electrode are defined by photolithography and etching. The material of the gate insulating layer 4 can be silicon dioxide, silicon oxynitride, silicon nitride, hafnium dioxide or other dielectric materials. The material of the gate electrode 5 may be polysilicon; the gate insulating layer 4 and the part of the double-layer fin structure under the gate electrode 5 form a double-layer channel structure.

Step 05: Please refer to FIG. 4e, etch and remove the first semiconductor material 2 at both ends of the fin structure, so that the second semiconductor material 3 at both ends of the fin structure forms the source and drain extension regions, and the source and drain extension regions and the silicon substrate 1 to form a gap;

Specifically, the first semiconductor material 2 in the source-drain extension region is removed by using a wet etching solution with a high selectivity ratio, and other parts are retained. For the case where the first semiconductor material 2 is silicon germanium and the second semiconductor material 3 is silicon, the wet etching solution is a mixture of hydrofluoric acid, nitric acid and acetic acid, preferably 1:2:5 of 18% A mixture of hydrofluoric acid, 42% nitric acid and 80% acetic acid. In this way, the double-layer channel structure of the formed fin structure is a double-layer semiconductor structure placed on the silicon substrate 1, and has good thermal conductivity; while the source and drain extension regions of the fin structure only have a single layer of second semiconductor material 3, suspended above the single crystal silicon substrate 1 .

Step 06: Referring to FIG. 4f, an insulating medium is deposited on the source-drain extension region and the gate electrode 5 at both ends of the fin structure, and the insulating medium covers the source-drain extension region and the gate electrode and fills the gap;

Specifically, at first, the insulating medium 6 is deposited on the silicon substrate that has completed step 05; then, the insulating medium 6 located on the surface of the silicon substrate 1 is removed; preferably, silicon dioxide can be selected as the insulating medium 6, and the chemical vapor phase The deposition method fills the gap between the silicon substrate 1 and the second semiconductor material 3 . In this way, the second semiconductor material 3 in the source and drain extension regions of the fin structure is isolated from the single crystal silicon substrate 1 by the insulating medium 6, effectively blocking the current leakage channels between the source and drain of the device and between devices. .

Step 07: Execute the extraction process of the gate electrode 5 , the source-drain extension region and the silicon substrate 1 , so as to form a fin field effect transistor.

Specifically, the gate electrode 5 , the source-drain extension region, and the electrode extraction of the silicon substrate 1 are completed according to the conventional manufacturing process of the fin field effect transistor, and the fin field effect transistor is formed.

In the present invention, the double-layer channel of the formed fin structure is connected to the silicon substrate, and the source-drain extension region electrically isolated from the silicon substrate. Compared with the existing fin field effect transistor structure prepared based on bulk silicon and SOI substrate, the invention combines the advantages of both. On the one hand, by isolating the source-drain extension region and the silicon substrate through an insulating medium, the leakage channel between the source and drain of the device and between the device and the device is effectively blocked, the leakage current is reduced, and the latch-up effect is effectively avoided; the other is On the one hand, the upper channel and the substrate are connected through the semiconductor material of the lower channel, which has good heat dissipation performance and avoids self-heating effect. At the same time, the preparation method of the present invention is based on the realization of the bulk silicon substrate, which controls the cost of raw materials; through high selectivity etching and backfilling insulating medium to form mutually isolated source and drain extension regions and silicon substrate technology, The method is very simple and controllable.

Although the present invention has been disclosed above with preferred embodiments, the embodiments are only examples for convenience of description, and are not intended to limit the present invention. Those skilled in the art can make For several changes and modifications, the scope of protection claimed by the present invention should be based on the claims.

Claims (10)

1. A fin field effect transistor comprising a silicon substrate, a fin structure on the silicon substrate and a gate insulating layer and a gate electrode positioned on the fin structure; it is characterized in that, The middle part of the fin structure below the gate electrode is a double-layer structure, and the double-layer structure forms a double-layer channel structure; the upper layer of the double-layer structure is an upper channel, and the lower layer is a lower channel; Both ends of the fin structure are single-layer structures, and there is an insulating medium between the single-layer structure and the silicon substrate; the single-layer structure constitutes a source-drain extension region. 2. The fin field effect transistor according to claim 1, wherein the material of the upper channel is silicon, germanium, silicon germanium or gallium arsenide; the material of the lower channel is germanium, silicon germanium or gallium arsenide. 3. The FinFET according to claim 1, wherein the insulating medium is silicon dioxide. 4 . The FinFET according to claim 1 , wherein the upper channel and the single-layer structure are located in the same layer. 5 . The FinFET according to claim 1 , wherein an insulating dielectric layer covers the gate electrode, the gate insulating layer and the source-drain extension region. 6. the preparation method of fin field effect transistor according to claim 1, is characterized in that, comprises: Step 01: providing a silicon substrate; Step 02: sequentially depositing a first semiconductor material and a second semiconductor material on the surface of the silicon substrate; Step 03: Etching the second semiconductor material and the first semiconductor material in sequence through photolithography and etching processes, and the etching stops on the surface of the silicon substrate, thereby forming a fin structure; Step 04: sequentially forming a gate insulating layer and a gate electrode on the fin structure; the gate insulating layer and the part of the double-layer fin structure below the gate electrode form a double-layer channel structure; Step 05: Etching and removing the first semiconductor material at both ends of the fin structure, so that the second semiconductor material at both ends of the fin structure forms a source-drain extension region, and between the source-drain extension region and gaps are formed between the silicon substrates; Step 06: depositing an insulating medium on the source-drain extension region and the gate electrode at both ends of the fin structure, the insulating medium covers the source-drain extension region and the gate electrode, and fills the gap; Step 07: Executing an electrode extraction process of the gate electrode, the source-drain extension region, and the silicon substrate, thereby forming the FinFET. 7 . The method for manufacturing a fin field effect transistor according to claim 6 , wherein, in the step 03 , the etching process is a plasma dry etching process. 8 . 8. The method for preparing a fin field effect transistor according to claim 6, wherein the first semiconductor material is silicon germanium, and the second semiconductor material is silicon, and in the step 05, the etching adopts a wet method For corrosion, the corrosion solution used is a mixture of hydrofluoric acid, nitric acid and acetic acid. 9 . The method for preparing a fin field effect transistor according to claim 8 , wherein the ratio of the mixed liquid is 18% hydrofluoric acid, 42% nitric acid and 80% acetic acid in a ratio of 1:2:5. 10. The method for manufacturing a fin field effect transistor according to claim 6, characterized in that, in the step 06, it specifically comprises: depositing an insulating medium on the silicon substrate that has completed the step 05; Insulating medium on the surface of silicon substrate.