CN105529263B

CN105529263B - The forming method and ldmos transistor of ldmos transistor

Info

Publication number: CN105529263B
Application number: CN201410521972.5A
Authority: CN
Inventors: 李勇
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2014-09-30
Filing date: 2014-09-30
Publication date: 2019-01-25
Anticipated expiration: 2034-09-30
Also published as: CN105529263A

Abstract

A kind of ldmos transistor forming method and ldmos transistor.Wherein, a kind of ldmos transistor, comprising: semiconductor substrate, the gate structure in the semiconductor substrate, the source electrode and drain electrode in the semiconductor substrate of the gate structure two sides；Further include: drift region, the drift region are located in the semiconductor substrate, and the gate structure part covers the drift region, and the drain electrode is located in the drift region.The performance of ldmos transistor provided by the invention is good.

Description

The forming method and ldmos transistor of ldmos transistor

Technical field

The present invention relates to semiconductor field more particularly to the forming methods and ldmos transistor of ldmos transistor.

Background technique

LDMOS transistor (lateral diffusion MOS, LDMOS), due to having High-breakdown-voltage, the characteristic compatible with CMOS technology, is widely used in power device.Compared with Conventional MOS transistors, LDMOS device at least one isolation structure between drain region and grid.When LDMOS connects high pressure, held by the isolation structure By higher voltage drop, the purpose of high-breakdown-voltage is obtained.

Prior art discloses a kind of fin ldmos transistor, the forming method of above-mentioned fin ldmos transistor is as follows:

With reference to Fig. 1 and Fig. 2, semiconductor substrate 10 is provided, the semiconductor substrate has the first fin 111, the second fin 112 and the third fin 113 between the first fin 111 and the second fin 112.The length of third fin 113 is less than first Fin 111 and the second fin 112.

The first fleet plough groove isolation structure 121,112 He of the second fin are formed between the first fin 111 and third fin 113 The second fleet plough groove isolation structure 122 is formed between third fin 113.First fleet plough groove isolation structure 121 and the second shallow trench every Height from structure 122 is lower than the height of the first fin 111 to third fin 113.

It is developed across the first grid structure 131 of the first fin 111, the first grid structure 131 covers the first fin 111 top and side wall.Also the first fleet plough groove isolation structure of covering part 121 of first grid structure 131.Wherein, first grid Structure 131 be polysilicon gate construction, including the first silicon oxide layer (not shown) and be located at the first silicon oxide layer on the first polycrystalline Silicon layer.

It is developed across the second grid structure 132 of the second fin 112, the second grid structure 132 covers the second fin 112 top and side wall.Also the second fleet plough groove isolation structure of covering part 122 of second grid structure 132.Second grid structure 132 also be polysilicon gate construction, including the second silicon oxide layer (not shown) and be located at the second silicon oxide layer on the second polysilicon Layer.

With reference to Fig. 3, the first source electrode groove 141a is formed in the first fin 111 of 131 side of first grid structure, The second source electrode groove 142a is formed in second fin 112 of two gate structures, 132 side.Drain electrode is formed in third fin 113 Groove 15a.

With reference to Fig. 4, germanium silicon layer is formed in the first source electrode groove 141a, the second source electrode groove 142a, then to the germanium silicon Layer carries out ion implanting, respectively corresponds to form the first source electrode 141 and the second source electrode 142.Germanium silicon is formed in drain recesses 15a Layer carries out ion implanting to the germanium silicon layer of drain recesses, forms drain electrode 15.Wherein germanium silicon layer is all higher than each fin, is correspondingly formed Source electrode and drain electrode also all be higher than each fin.

Then, with reference to Fig. 5, dielectric layer 16 is formed, covers the first fin 111, the first source electrode 141, first grid structure 131, the first fleet plough groove isolation structure 121, drain electrode 15, third fin 113, the second fleet plough groove isolation structure 122, second grid knot Structure 132, the second source electrode 142 and the second fin 112.

Then, with reference to Fig. 6, first grid structure 131 is removed, forms first grid texture grooves 171a in dielectric layer, Expose the first fin 111 and the first fleet plough groove isolation structure of part 121 in the bottom first grid texture grooves 171a.Removal the Two gate structures 132 form second grid texture grooves 172a, the bottom second grid texture grooves 172a in dielectric layer Expose the second fin 112 and the second fleet plough groove isolation structure of part 122.

Referring next to Fig. 7, the first aluminum gate structure material layer is filled in first grid texture grooves 171a, forms first Aluminum gate structure 171.Wherein, the first aluminum gate structure 171 includes the first grid oxide layer (not shown) and is located on the first grid oxide layer The first aluminium layer.The second aluminum gate structure material layer is filled in second grid texture grooves 172a, forms the second aluminium gate knot Structure 172.Wherein, the second aluminum gate structure 172 includes the second grid oxide layer (not shown) and the second aluminium on the second grid oxide layer Layer.

When ldmos transistor is opened, apply voltage in drain electrode 15 and the first source electrode 141, electric current can be by the first source electrode 141 During flowing to drain electrode 15, due to the presence of the first fleet plough groove isolation structure 121, the field distribution of ldmos transistor is changed Become, the first fleet plough groove isolation structure 121 bears biggish electric field.Apply voltage in drain electrode 15 and the second source electrode 142, electric current can During flowing to drain electrode 15 by the second source electrode 142, due to the presence of the second fleet plough groove isolation structure 122, the second shallow trench every It is changed from the field distribution around structure 122, the second fleet plough groove isolation structure 122 bears biggish electric field.

However, the performance of the fin ldmos transistor of the prior art is bad.

Summary of the invention

Problems solved by the invention is that the performance of the fin ldmos transistor of the prior art is bad.

To solve the above problems, the present invention provides a kind of forming method of ldmos transistor, comprising:

Semiconductor substrate is provided；

Drift region is formed in the semiconductor substrate；

Gate structure is formed on the semiconductor substrate, and the gate structure part covers the drift region；

Source electrode material layer and drain material layer, the drain electrode material are formed in the semiconductor substrate of the gate structure two sides The bed of material is in the drift region；

Ion implanting is carried out to the source electrode material layer and drain material layer, forms source electrode and drain electrode.

Optionally, the semiconductor substrate also has well region, and the well region surrounds the drift region.

Optionally, the injection type of the drift region and the injection type of the well region are opposite.

Optionally, the gate structure is polysilicon gate construction.

Optionally, it is formed after the source electrode and the drain electrode, further includes the following steps:

Interlayer dielectric layer is formed in the semiconductor substrate, source electrode, polysilicon gate construction and drain electrode；

The partial polysilicon gate structure far from drift region side is removed, it is recessed to form gate structure in interlayer dielectric layer Slot；

Metal gate structure is formed in the gate structure groove, the metal gate structure part covers the drift Area, the remaining polysilicon gate construction are the first barrier layer, first barrier layer is for defining on the drift region The position of the drain electrode and width.

Optionally, source electrode material layer and drain material are formed in the semiconductor substrate of the polysilicon gate construction two sides Before the step of layer, further includes: form side wall around the polysilicon gate construction.

Optionally, it is formed before source electrode material layer and drain material layer, further includes: in the gate structure far from the drift The side for moving area forms the second barrier layer, and the thickness on second barrier layer is equal to the thickness of the gate structure, and described second Barrier layer is used to define position and the width of the source electrode.

Optionally, second barrier layer defines position and the width of the source electrode in the two sides of the source electrode, alternatively, Second barrier layer defines the source electrode in the side opposite with the gate structure of the source electrode, with the gate structure Position and width.

Optionally, second barrier layer is polysilicon gate construction.

Optionally, further includes: formed before source electrode material layer and drain material layer, formed around second barrier layer Side wall.

Optionally, source electrode material layer and drain material layer, packet are formed in the semiconductor substrate of the gate structure two sides It includes:

Using the gate structure as exposure mask, to performing etching to form source electrode in the semiconductor substrate of the gate structure two sides Groove and drain recesses；

Source electrode material layer is formed in the source electrode groove；

Drain material layer is formed in the drain recesses.

Optionally, when the ldmos transistor is PMOS transistor, the source electrode material layer and the drain material layer are Germanium silicon layer；When the ldmos transistor is NMOS transistor, the source electrode material layer and the drain material layer are silicon carbide Layer.

Optionally, before forming source electrode material layer and drain material layer, in the gate structure far from the drift region Side formed the second barrier material layer, alternatively, on the drift region of the other side of the gate structure formed first stop material The bed of material；

Semiconductor substrate under first barrier material layer and first barrier material layer is performed etching, described first First through hole is formed in barrier material layer, and drain recesses are formed in the semiconductor substrate, remaining first barrier material Layer is the first barrier layer, alternatively,

Semiconductor substrate under second barrier material layer and second barrier material layer is performed etching, described second The second through-hole is formed in barrier material layer, and forms source electrode groove in semiconductor substrate, and remaining second barrier material layer is Second barrier layer；

Side wall is formed in the first through hole side wall or forms side wall in second through-hole side wall；

Drain material layer is formed in the drain recesses or source electrode material layer is formed in the source electrode groove.

Optionally, before forming source electrode material layer and drain material layer, in the gate structure far from the drift region Side form the second barrier material layer and form the first barrier material layer on the drift region of the other side of the gate structure；

To the first barrier material layer and its under semiconductor substrate perform etching, formed in first barrier material layer First through hole, and drain recesses are formed in semiconductor substrate, remaining first barrier material layer is the first barrier layer；

To the second barrier material layer and its under semiconductor substrate perform etching, formed in second barrier material layer Second through-hole, and source electrode groove is formed in semiconductor substrate, remaining second barrier material layer is the second barrier layer；

Side wall is formed in the first through hole side wall and forms side wall in second through-hole side wall；

Drain material layer is formed in the drain recesses and source electrode material layer is formed in source electrode groove.

Optionally, first barrier layer and second barrier layer are polysilicon gate construction.

Optionally, two adjacent ldmos transistor common drains or it is respectively provided with drain electrode.

The present invention also provides a kind of ldmos transistors, comprising:

Semiconductor substrate, the gate structure in the semiconductor substrate, positioned at partly leading for the gate structure two sides Source electrode and drain electrode in body substrate；

The ldmos transistor further include:

Drift region, the drift region are located in the semiconductor substrate, and the gate structure part covers the drift region, And the drain electrode is located in the drift region.

Ldmos transistor further include:

First barrier layer, on the drift region of the gate structure side, for define the drain electrode position and Width；

Second barrier layer, in side of the gate structure far from the drift region, for defining the position of the source electrode And width.

Compared with prior art, technical solution of the present invention has the advantage that

Drift region is formd in semiconductor substrate instead of fleet plough groove isolation structure in the prior art, around drift region Field distribution be changed, larger electric field can be born.In addition, the ingredient of fleet plough groove isolation structure is usually silica, source electrode It can not be formed on silicon oxide layer with drain material layer.Just because of there is the presence of drift region in semiconductor substrate, do not have Fleet plough groove isolation structure.Therefore, when forming drain material layer in semiconductor substrate, oxygen in fleet plough groove isolation structure can be prevented SiClx layer has an impact the formation of drain material layer, so as to improve the performance of drain material layer, and then improves subsequent The performance of the LDMOS of formation.

Detailed description of the invention

Fig. 1 is semiconductor substrate and the first grid in semiconductor substrate in the fin ldmos transistor of the prior art The overlooking structure diagram of pole structure, second grid structure and third gate structure；

Fig. 2 is the schematic diagram of the section structure along the direction AA of Fig. 1；

Fig. 3~Fig. 7 is the section of each forming step after Fig. 2 step of the fin ldmos transistor of the prior art Structural schematic diagram；

Fig. 8 is the overlooking structure diagram of a forming step of the ldmos transistor of the embodiment of the present invention one；

Fig. 9 is the schematic diagram of the section structure of the Fig. 8 along the direction BB；

Each forming step after the step of Figure 10~Figure 13 is the ldmos transistor junction diagram 9 of the embodiment of the present invention one The schematic diagram of the section structure；

Figure 14 is the schematic diagram of the section structure of the ldmos transistor of the embodiment of the present invention four；

Figure 15 is the schematic diagram of the section structure of the ldmos transistor of the embodiment of the present invention six；

Figure 16 is the schematic diagram of the section structure of the ldmos transistor of the embodiment of the present invention eight.

Specific embodiment

By finding and analyzing, the reason that the performance of the fin ldmos transistor of the prior art is bad is as follows:

(1) method for forming drain recesses 15a in third fin 113 referring to figs. 2 and 3 is combined to be photoetching, etch, It since the length of third fin 113 is smaller, is influenced by lithographic accuracy, is difficult to be just aligned and is performed etching in third fin 113 Operation.Part drain recesses 15a will form on the first adjacent fleet plough groove isolation structure 121 or/and the second shallow trench isolation In structure 122.Therefore, the partial sidewall of drain recesses 15a be the first fleet plough groove isolation structure 121 or/and the second shallow trench every From structure 122.

When growth forms germanium silicon layer in drain recesses 15a, in the first fleet plough groove isolation structure 121 or/and the second shallow ridges The performance of the germanium silicon layer formed at recess isolating structure 122 is bad, or even can not form germanium silicon layer.Especially in the first shallow trench isolation The performance of the germanium silicon layer of the formation of the corner of structure 121 or/and the second fleet plough groove isolation structure 122 is more bad.Reason is such as Under: the performance that germanium silicon layer is grown on the third fin 113 that material is silicon is good.And the material of the first and second fleet plough groove isolation structures Material is silica.Therefore, the performance that germanium silicon layer is grown on silica is poor, or even can not grow.

Therefore, the performance for the drain electrode being subsequently formed is poor, to influence the performance for the ldmos transistor being subsequently formed.

(2) it combines and refers to Fig. 5 to Fig. 7, the first fleet plough groove isolation structure 121 of 131 part of first grid structure covering, second 132 part of gate structure covers the second fleet plough groove isolation structure 122, therefore, first grid structure 131 and second grid structure 132 is longer.Forming the first aluminum gate structure 171 and during the second aluminum gate structure 172, the first aluminium layer it is more soft compared with It is long, when chemical mechanical grinding operates to form the first aluminium layer, it is easy to appear recess (dishing) phenomenon.Therefore, using existing side The performance for the first aluminum gate structure 171 that method is formed is bad.In addition, the second aluminium layer is more soft longer, chemical mechanical grinding operation When forming the second aluminium layer, it is also easy to appear depressed phenomenon.Therefore, the second aluminum gate structure 172 formed using existing method Performance it is also bad.

Germanium silicon layer at (3) first source electrodes 141 needs to be higher than the first fin 111, and the germanium silicon layer at the second source electrode 142 needs Higher than the second fin 112, the germanium silicon layer at drain electrode 15 needs to be higher than third fin 113.At such first source electrode 141 and drain electrode 15 The germanium silicon layer at place can apply optimum stress to the channel under first grid structure 131, maximumlly to improve the migration of carrier Rate.Similarly, the germanium silicon layer at the second source electrode 142 and at drain electrode 15 can apply the channel under second grid structure 132 and most preferably answer Power maximumlly improves the mobility of carrier.

However, the growing height of germanium silicon layer is directly proportional to the size of the growing space of germanium silicon layer.For fin LDMOS crystal For pipe, the size of the first source electrode groove 141a, the second source electrode groove 142a and drain recesses 15a are too small, how accurately to control The growing height of above-mentioned germanium silicon layer everywhere, existing technique are difficult to accomplish.Following situations can occur:

1. to form germanium silicon layer in drain recesses 15a, which carries out for being higher than the first fin or the second fin Explanation.

With reference to Fig. 4, the growing height and first of the germanium silicon layer higher than the first, second fleet plough groove isolation structure at drain electrode The distance between gate structure 131, second grid structure 132 are directly proportional.In the prior art, first grid structure 131 and second The distance between gate structure 132 is larger, and therefore, the height that germanium silicon layer is grown in drain recesses not only can be more than first, The height of two fleet plough groove isolation structures, and may also exceed the height of first grid structure 131, second grid structure 132.First The germanium silicon layer formed between gate structure 131 and second grid structure 132 is sufficiently bulky, is spherical.

2. to form germanium silicon layer in the first source electrode groove, which is said for being higher than the first fin or the second fin It is bright.

With reference to Fig. 4, the germanium silicon layer higher than the first fin 111 positioned at the first source electrode groove only has first grid structure The growing height of germanium silicon layer at 131 pair of first source electrode is restricted.Therefore, because the growth work of the germanium silicon layer at the first source electrode Skill is difficult accurately to control the growing height of germanium silicon layer, also can be very higher than the germanium silicon layer volume at the first source electrode of the first fin 111 Greatly, it is spherical, and is higher than first grid structure 131.

3. the case where the case where forming germanium silicon layer in the second source electrode groove in the first source electrode groove with germanium silicon layer is formed Identical, volume also can be very big, is in spherical and is higher than second grid structure 132.

Therefore, the height for the germanium silicon layer that the method for the prior art is formed all can be more than first grid structure 131, second grid Structure 132.During forming the first aluminium layer and the second aluminium layer using chemical mechanical grinding, chemical mechanical grinding can be in germanium silicon Stop on layer, can't stop at first grid structure 131 and second grid structure 132, so that the first aluminium layer and the The thickness of two aluminium layers increases, the further performance for influencing the first aluminum gate structure 171 and the second aluminum gate structure 172.

Therefore, in order to solve the above technical problem, the present invention provides a kind of forming methods of ldmos transistor, using this The forming method of the ldmos transistor of invention can be improved the performance for the ldmos transistor being subsequently formed.With reference to the accompanying drawing Specific embodiments of the present invention are described in detail.

Embodiment one

The present embodiment is illustrated with two adjacent ldmos transistor common drains.

In conjunction with reference Fig. 8 and Fig. 9, semiconductor substrate 20 is provided.

In the present embodiment, semiconductor substrate 20 is silicon substrate.Semiconductor substrate 20 has at least one fin 201.Each fin There is the insulating layer 202 lower than fin 201 between portion 201.The material of insulating layer 202 is silica.Specific forming method is as follows:

Patterned first mask layer (not shown), patterned first mask layer are formed in semiconductor substrate 20 Define fin position to be formed；It is formed at least by mask etching semiconductor substrate 20 of patterned first mask layer Then one bulge-structure forms insulating layer 202 that is highly identical and being lower than bulge-structure, insulating layer between bulge-structure 202 play the insulating effect between semiconductor devices.The projective structure higher than insulating layer 202 is fin 201.

In other embodiments, semiconductor substrate is silicon-on-insulator (SOI).Silicon-on-insulator includes bottom silicon layer, is located at Insulating layer on bottom silicon layer, the top silicon layer on insulating layer.The top silicon layer is used to form at least one fin It belongs to the scope of protection of the present invention.

Continuing with reference Fig. 8 and Fig. 9, drift region 203 is formed in semiconductor substrate.

In the present embodiment, after forming fin 201, fin 201 and its lower semiconductor substrate progress ion implanting are formed Well region (not shown).

After forming well region, ion implanting is carried out to fin 201, forms drift region 203.Drift region 203 is surrounded by well region. The injection depth of drift region 203 is greater than the depth of insulating layer 202.The injection type phase of the injection type of drift region 203 and well region Instead.The two adjacent ldmos transistors being subsequently formed can share a drift region 203.

Then, with reference to Figure 13, first grid structure 21, second grid structure 22, the first barrier layer are formed on fin 201 With the second barrier layer.

In the present embodiment, first grid structure 21 and second grid structure 22 are polysilicon gate construction or metal gates knot Structure.First barrier layer and the second barrier layer are polysilicon gate construction.

First grid structure 21 and second grid structure 22 are effective grid in the ldmos transistor being subsequently formed.The One gate structure 21 and second grid structure 22 partially cover the drift region 203 respectively.

First barrier layer and the second barrier layer are non-effective grid, do not play the role of grid.Wherein, first stops Layer prevents the drain material layer overgrowth in subsequent step.Second barrier layer prevents the source electrode material layer in subsequent step from growing It is excessive.In the present embodiment, the setting on the first barrier layer and the second barrier layer is specific as follows:

First barrier layer includes the first barrier layer 231 and the first barrier layer 232, is set to first grid structure 21 and second On drift region 203 between gate structure 22.First grid structure 21 is adjacent with the first barrier layer 231, second grid structure 22 It is adjacent with the first barrier layer 232.Between first barrier layer 231 and the first barrier layer 232 have first distance H1, described first away from From position and the width that H1 is used to define the drain electrode being subsequently formed.

Second barrier layer includes the second barrier layer 241 and the second barrier layer 242.Second barrier layer 241 is in first grid knot On fin 201 of the structure 21 far from 203 side of drift region.Between first grid structure 21 and the second barrier layer 241 have second away from From H2, the second distance H2 is used to define position and the width for the first source electrode being subsequently formed.Second barrier layer 242 is second On fin 201 of the gate structure 22 far from 203 side of drift region.And have between second grid structure 22 and the second barrier layer 242 There are third distance H3, the third distance H3 to be used to define position and the width for the second source electrode being subsequently formed.

In other embodiments, one second resistance can also be formed between first grid structure 21 and the second barrier layer 241 Barrier, second barrier layer are adjacent with first grid structure.Second barrier layer and the second barrier layer 241 are in first source electrode Two sides define position and the width of the first source electrode together.

In other embodiments, one second resistance can also be formed between second grid structure 22 and the second barrier layer 242 Barrier, second barrier layer are adjacent with second grid structure.Second barrier layer and the second barrier layer 242 are in second source electrode Two sides define position and the width of the second source electrode together.

In the present embodiment, first grid structure 21 and second grid structure 22 are metal gate structure.First barrier layer and Second barrier layer is polysilicon gate construction.With reference to Fig. 8, Fig. 9 to Figure 12, first grid structure 21, second grid structure 22, The forming method on one barrier layer and the second barrier layer is as follows:

In conjunction with reference Fig. 8 and Fig. 9, it is developed across the gate dielectric material layer of fin 201 on fin 201, in subsequent technique, It is used to form the gate dielectric layer of each dummy gate structure.It forms polysilicon layer on gate dielectric material layer, in subsequent technique, is used for shape At the polysilicon gate of each dummy gate structure.Then, patterned second mask layer (not shown) is formed on the polysilicon layer, with Patterned second mask layer is exposure mask, is performed etching to gate dielectric material layer and polysilicon layer, from one end of fin 201 The pseudo- grid of the first dummy gate structure A1, the second dummy gate structure A2, third dummy gate structure A3 and the 4th are sequentially formed to the other end Pole structure A4.First dummy gate structure A1 to the 4th dummy gate structure A4 is respectively across on fin 201, and corresponding covering fin The top in portion 201 and side wall.

Second dummy gate structure A2 and third dummy gate structure A3 is covered with drift region respectively.Second dummy gate structure A2 is used In formation first grid structure 21 and the first barrier layer 231.Third dummy gate structure A3 is used to form 22 He of second grid structure First barrier layer 232.First dummy gate structure A1 is the second barrier layer 241.4th dummy gate structure A4 is the second barrier layer 242。

With reference to Fig. 9, the first dummy gate structure A1 includes the gate dielectric layer A11 being located on fin 201, is located at gate dielectric layer Polysilicon gate A12 on A11.Second dummy gate structure A2 includes the gate dielectric layer A21 being located on fin 201, is located at grid Jie Polysilicon gate A22 on matter layer A21.Third dummy gate structure A3 includes the gate dielectric layer A31 being located on fin 201, is located at Polysilicon gate A32 on gate dielectric layer A31.4th dummy gate structure A4 include gate dielectric layer A41 on the fin 201, Polysilicon gate A42 on gate dielectric layer A41.

In the present embodiment, the first side wall is formed around the first dummy gate structure A1, around the second dummy gate structure A2 The second side wall is formed, forms third side wall around third dummy gate structure A3, forms the around the 4th dummy gate structure A4 Four side walls.First side wall to the 4th side wall is formed simultaneously, and forming method is the known technology of those skilled in the art.

The reason of forming the first side wall to four side walls is as follows:

Between the second side wall around (1) second dummy gate structure A2 and the third side wall around third dummy gate structure A3 With first distance H1, the first distance H1 is used to define position and the width for the drain electrode being subsequently formed.

Between the second side wall around the first side wall and the second dummy gate structure A2 around (2) first dummy gate structure A1 With second distance H2, the second distance H2 is used to define position and the width for the first source electrode being subsequently formed.

(3) between the 4th side wall around the third side wall and the 4th dummy gate structure A4 around third dummy gate structure A3 With third distance H3, the third distance H3 is used to define position and the width for the second source electrode being subsequently formed.

(4) around each gate structure if without side wall, subsequent source electrode material layer and drain material layer in formation In the process, source electrode material layer and drain material layer can also be grown on corresponding polysilicon gate in each dummy gate structure.After in this way, The volume of the continuous source electrode material layer formed and drain material layer can be bigger, the source electrode material layer of formation and the height of drain material layer Degree can be relatively high.But the volume of the source electrode material layer of formation and drain material layer and height are smaller than the prior art.

In other embodiments, if not forming the first side wall to the 4th side wall, the scope of protection of the invention is also belonged to.

Then, it with reference to Figure 10, is formed in the fin 201 between the first dummy gate structure A1 and the second dummy gate structure A2 First source electrode groove.Drain recesses are formed in fin 201 between the second dummy gate structure A2 and third dummy gate structure A3. The second drain recesses are formed in fin 201 between third dummy gate structure A3 and the 4th dummy gate structure A4.

In the present embodiment, the forming method for forming the first source electrode groove, the second source electrode groove and drain recesses is etching, and It is formed simultaneously.Specific forming method is the known technology of those skilled in the art, and details are not described herein.

Then, the first source electrode material layer 251 is formed in the first source electrode groove, forms the second source in the second source electrode groove Pole material layer 252 forms drain material layer 26 in drain recesses.

In the present embodiment, when the ldmos transistor that is subsequently formed is PMOS transistor, then the first source electrode material layer 251, the Two source electrode material layers 252 and drain material layer 26 are germanium silicon layer.

The method for forming germanium silicon layer is selective epitaxial growth.First source electrode material layer 251, the second source electrode material layer 252 All it is higher than fin 201 with drain material layer 26.

In ldmos transistor in the prior art, the first source electrode material layer, the second source electrode material layer, drain material are formed The space of layer is larger, however, the first source electrode material layer, the second source electrode material layer and drain material layer only need in the transistor To exceed a little height of fin, optimum stress otherwise can not be applied to the channel under corresponding grid.But control first It is very in practical growth technique that source electrode material layer, the second source electrode material layer and drain material layer, which only exceed a little height of fin, It is rambunctious.

Therefore, the present embodiment leads to according to the principle of " growing height of germanium silicon layer is directly proportional to the growing space of germanium silicon layer " The growing space of control germanium silicon layer is crossed, to control the growing height of germanium silicon layer.Compared with the existing technology, by reducing germanium silicon layer Growing space, to reduce the growing height of germanium silicon layer.

Specifically, the growing space for defining drain material layer in the present embodiment is first distance H1.First distance is less than existing There are the distance between first grid structure and the second grid structure in technology, therefore, the drain material formed in the present embodiment The height of layer can reduce, this is highly not less than fin 201, not higher than the second dummy gate structure A2's and third dummy gate structure A3 Highly.In this way, in the step of being subsequently formed metal gate structure, using the metal gate in chemical mechanical grinding metal gate structure When pole, chemical mechanical grinding operation will not stop on drain material layer in advance, and then make the metal gate structure being subsequently formed In the thickness of metal gate layers meet the requirements, improve the performance for the LDMOS being subsequently formed.

The growing space that the first source electrode material layer is defined in the present embodiment is second distance H2.And second distance is much smaller than existing There is the growing space of the first source electrode material layer in technology.Therefore, the height meeting of the first source electrode material layer formed in the present embodiment It reduces, this is highly not less than fin 201, not higher than the height of the first dummy gate structure A1 and the second dummy gate structure A2.In this way, In the step of being subsequently formed metal gate structure, when using metal gates in chemical mechanical grinding metal gate structure, chemistry Mechanical abrading action will not be stopped in advance on the first source electrode material layer.Make the gold in the metal gate structure being subsequently formed in turn The thickness for belonging to grid layer meets the requirements, and improves the performance for the LDMOS being subsequently formed.

The growing space that the second source electrode material layer is defined in the present embodiment is third distance H3.And third distance is much smaller than existing There is the growing space of the second source electrode material layer in technology.Therefore, the height meeting of the second source electrode material layer formed in the present embodiment It reduces, this is highly not less than fin 201, not higher than the height of the first dummy gate structure A1 and the second dummy gate structure A2.In this way, In the step of being subsequently formed metal gate structure, when using metal gates in chemical mechanical grinding metal gate structure, chemistry Mechanical abrading action will not be stopped in advance on the second source electrode material layer.Make the gold in the metal gate structure being subsequently formed in turn The thickness for belonging to grid layer meets the requirements, and improves the performance for the LDMOS being subsequently formed.

Further, the first distance H1 in the present embodiment, second distance H2 and third distance H3 are respectively and are greater than In 0.01 micron and it is less than or equal to 0.2 micron.If first distance H1, second distance H2 and third distance H3 are too big, will produce Raw problems of the prior art (3).If first distance H1, second distance H2 and third distance H3 are too small, it is not easy to Form the germanium silicon layer for being higher than fin 201.

After forming above-mentioned germanium silicon layer, silicon cap layer (not shown) is formed on above-mentioned germanium silicon layer respectively.Form the work of silicon cap layer With are as follows: in subsequent step, need to form metal silicide layer on germanium silicon layer.Germanium silicon layer is germanic too many, is formed on germanium silicon layer The performance of metal silicide is bad.And the better performances of metal silicide layer are formed on silicon.So needing be subsequently formed Silicon cap layer is formed between metal silicide layer and above-mentioned germanium silicon layer.

Then, ion implanting is carried out to the first source electrode material layer 251, the second source electrode material layer 252 and drain material layer 26, Corresponding formation the first source electrode, the second source electrode and drain electrode.Wherein drain electrode is the common drain of two adjacent ldmos transistors.

In other embodiments, the ldmos transistor being subsequently formed is NMOS transistor.Then the first source electrode material layer, second Source electrode material layer and drain material layer are silicon carbide layer.

Then, with reference to Figure 11, in semiconductor substrate 20, fin 201, the first dummy gate structure A1, the first source electrode, the second puppet Gate structure A2, drain electrode, third dummy gate structure A3, the second source electrode, interlayer dielectric layer 27 is formed on the 4th dummy gate structure A4.

The material of interlayer dielectric layer 27 is silica, silicon carbide or silicon oxynitride.Interlayer dielectric layer 27 or low k material The dielectric constant of material or ultralow-k material film, the low-k materials is less than or equal to 3, and the dielectric constant of the ultralow-k material film is less than or equal to 2.7.The forming method of interlayer dielectric layer 27 is deposition.It is specifically as follows high-density plasma (High Density Plasma, HDP) chemical vapor deposition either high depth ratio fill out ditch technique (High Aspect Ratio Process, HARP) Or flowing chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD).Using above-mentioned three kinds of sides Method filling capacity is stronger, and 27 consistency of interlayer dielectric layer of formation is relatively high.Certainly, interlayer dielectric layer 27 is also possible to this field Other depositing operations known to technical staff, also belong to protection scope of the present invention.

In the present embodiment, interlayer dielectric layer 27 is equal to the 4th dummy gate structure A4 with the first dummy gate structure A1.

Then, with reference to Figure 12, after forming interlayer dielectric layer 27, the pseudo- grid in part second far from 203 side of drift region are removed Pole structure A2, the part third dummy gate structure A3 far from 203 side of drift region, are respectively formed the first grid in interlayer dielectric layer Fin 201 and part drift region are exposed in pole texture grooves and second grid texture grooves, first grid texture grooves bottom 203, fin 201 and part drift region 203 are exposed in second grid texture grooves bottom.

Wherein, first grid texture grooves, the forming method of second grid texture grooves are as follows: on interlayer dielectric layer 27 Patterned third mask layer (not shown) is formed, using the patterned third mask layer as exposure mask, etches the second dummy grid Structure A2 and third dummy gate structure A3.So that part the second dummy gate structure A2 and part third dummy gate structure A3 removal, It is respectively formed first grid texture grooves and second grid texture grooves.

It should be noted that the covering with drift region 203 respectively of first grid texture grooves and second grid texture grooves Width H4 is 3~100nm.If above-mentioned cover width H4 is too small, the first grid knot formed in first grid texture grooves Structure 21 can not control well region and drift region simultaneously.The second grid structure 22 formed in second grid texture grooves can not be simultaneously The transmission path in control well region and drift region, electronics or hole is easy to be blocked.Above-mentioned cover width H4 is the bigger the better, still, The cover width H4 is bigger, and the length dimension for the first metal gate layers in first grid structure being subsequently formed is bigger, adopts When grinding the first metal gate layers with the method for chemical mechanical grinding, it is more easy to appear depression defect.Similarly, the cover width H4 is bigger, and the length dimension for the second metal gate layers in second grid structure being subsequently formed is bigger, is ground using chemical machinery When the method for mill grinds the second metal gate layers, it is more easy to appear depression defect.

After forming first grid texture grooves and second grid texture grooves, remaining second dummy gate structure is the first resistance Barrier 231.Remaining third dummy gate structure is the first barrier layer 232.

Then, with reference to Figure 13, shape is distinguished in the bottom and side wall of first grid texture grooves and second grid texture grooves At the first high-k gate dielectric layer and the second high-k gate dielectric layer, later, respectively in the first high-k gate dielectric layer and the second high-k gate dielectric The first metal layer and second metal layer are formed on layer, the first metal layer and second metal layer are higher than the first dummy grid knot Structure A1, the 4th dummy gate structure A4 and interlayer dielectric layer 27 will be above the first pseudo- grid using the method for chemical mechanical grinding later The metal layer of pole structure A1, the 4th dummy gate structure A4 and interlayer dielectric layer 27 removal, be respectively formed the first metal gate layers and Second metal gate layers.Such first metal gate layers and the first high-k gate dielectric layer form first grid structure 21.Second gold medal Belong to grid layer and the second high-k gate dielectric layer forms second grid structure 22.

It should be noted that being high-k gate dielectric layer between first grid structure 21 and the first barrier layer 231.Second grid It is also high-k gate dielectric layer between structure 22 and the first barrier layer 232.

At this moment, first grid structure 21, second grid structure 22, the first barrier layer 231, the resistance of the first barrier layer 232, second Barrier 241, the second barrier layer 242 are formed.

First distance H1 is the distance between the first barrier layer 231 and the first barrier layer 232.

Second distance H2 is the distance between the second barrier layer 241 and first grid structure 21.

Third distance H3 is the distance between the second barrier layer 232 and second grid structure 22.

In the present embodiment, position and width of first barrier layer in addition to drain electrode can be defined.There are one first barrier layers Effect: the first metal gate layers and second grid in the first grid structure formed using the method for chemical mechanical grinding are prevented There is depressed phenomenon during the second metal gates in structure.The reason is as follows that: the first metal gate layers and the second metal gate The material of pole layer is aluminium or copper, and for polycrystalline silicon gate layer, the material is soft, above-mentioned if not forming the first barrier layer During chemical mechanical grinding the first metal layer and second metal layer, without the branch of polysilicon layer harder in the first barrier layer Support will appear depressed phenomenon when grinding so long metal layer certainly.

It should be noted that the fin 201 in the present embodiment is an overall structure, the first source electrode, drain electrode and the second source Pole is formed on the fin 201.Not such to the prior art, the first source electrode is formed on the first fin, the second source electrode shape At on the second fin, drain electrode is formed on third fin.There is the first shallow trench isolation between first fin and the second fin Structure.There is the second fleet plough groove isolation structure between second fin and third fin.And the present embodiment is just because of form drift Area 203, drift region 203 is instead of fleet plough groove isolation structure in the prior art.Drift region 203 and the well region for surrounding the drift region Depletion layer is formed, the field distribution around such drift region 203 is changed, and can bear larger electric field.Therefore, drift region 203 It is identical as the effect of the first fleet plough groove isolation structure in the prior art and the second fleet plough groove isolation structure.

Exactly because the first fleet plough groove isolation structure is not had around drain recesses in addition, there is the presence of drift region 203 And/or second fleet plough groove isolation structure therefore, will not in drain recesses when growing drain material layer in drain recesses Occur that the place of drain material layer can not be grown, drain material layer all can be especially recessed in drain electrode in the solid of drain recesses The drain material layer of the corner of slot can also be grown fine, to improve the performance of drain material layer, and then after improving The performance of the continuous LDMOS formed.

In other embodiments, first grid structure 21 and second grid structure 22 can be polysilicon gate construction.Also belong to In protection scope of the present invention.If first grid structure 21 and second grid structure 22 are polysilicon gate construction, above-mentioned Form first grid texture grooves and the step of second grid texture grooves and in first grid texture grooves and second grid knot The first and second high-k gate dielectric layers, corresponding first be located on the first and second high-k gate dielectric layers are respectively formed in structure groove It can be omitted with the forming step of the second metal gate layers.

In other embodiments, the forming method of first grid structure, second grid structure and the first barrier layer is as follows, also belongs to In protection scope of the present invention.

While forming the first dummy gate structure, four dummy gate structures, the second dummy gate structure is not formed, but shape At the 5th dummy gate structure and first barrier layer adjacent with the 5th dummy gate structure.Forming the first dummy gate structure, the 4th While dummy gate structure, do not form third dummy gate structure yet, but formed the 6th dummy gate structure and with the 6th dummy grid The first adjacent barrier layer of structure.The first adjacent barrier layer of 5th dummy gate structure and adjacent with the 6th dummy gate structure One barrier layer is located at the two sides for the drain electrode being subsequently formed, and defines position and the width of drain electrode.5th dummy gate structure and with the 5th The length on the first adjacent barrier layer of dummy gate structure and length equal to the second dummy gate structure in upper one embodiment.The The length on six dummy gate structures and first barrier layer adjacent with the 6th dummy gate structure and equal in upper one embodiment The length of three dummy gate structures.The position of 5th dummy gate structure and the 6th dummy gate structure respectively with the first grid that is subsequently formed Pole structure, the position of second grid structure are identical.5th dummy gate structure, adjacent with the 5th dummy gate structure first stop Layer, the 6th dummy gate structure, first barrier layer adjacent with the 6th dummy gate structure are all polysilicon gate construction.

Then, interlayer dielectric layer, covering semiconductor substrate, fin, the first dummy grid, the first source electrode, the 5th pseudo- grid are formed Pole structure, first barrier layer adjacent with the 5th dummy gate structure, first barrier layer adjacent with the 6th dummy gate structure, leakage Pole, the 6th dummy gate structure, the 4th dummy gate structure.The interlayer dielectric layer is equal with each dummy gate structure.

Then, the 5th dummy gate structure and the 6th dummy gate structure are removed, is formed in interlayer dielectric layer and is respectively formed the One gate structure groove and second grid texture grooves.

Later, the first high-k gate dielectric layer is formed in the bottom and side wall of first grid texture grooves and be located at the first high k grid The first metal gate layers on dielectric layer form first grid structure.It is formed in the bottom and side wall of second grid texture grooves Second high-k gate dielectric layer and the second metal gate layers on the second high-k gate dielectric layer form second grid structure.At this point, First grid structure and second grid structure are respectively the first metal gate structure and the second metal gate structure.

In other embodiments, the second barrier layer is not formed on fin and also belongs to protection scope of the present invention.Only, subsequent The height and width of the first source electrode material layer and the second source electrode material layer that are formed in step will increase, it may appear that in the prior art The problem of (3).

In other embodiments, does not form the first barrier layer on fin, also belong to protection scope of the present invention.Only formed Drain material layer height and width dimensions it is very big, also will appear the problems of the prior art (3).

In other embodiments, first grid structure, the first barrier layer, second grid structure and the second barrier layer formation side Method is as follows, also belongs to protection scope of the present invention.

The 5th dummy gate structure and the 6th dummy gate structure are initially formed on fin.

Then, the first barrier material layer and the second barrier material layer are formed in the two sides of the 5th dummy gate structure, The two sides of 6th dummy gate structure form the first barrier material layer and the second barrier material layer.The of 5th dummy gate structure side First barrier material layer of the side of one barrier material layer and the 6th dummy gate structure is same barrier material layer, and is shared, because This, positioned at the centre of the 5th dummy gate structure and the 6th dummy gate structure.At this point, the first barrier material layer and the second barrier material Layer is polysilicon gate construction.

Then, interlayer dielectric layer is formed, semiconductor substrate, fin, the second barrier material layer, the 5th dummy grid knot are covered Structure, the first barrier material layer, the 6th dummy gate structure.Interlayer dielectric layer and the 5th dummy gate structure, the 6th dummy gate structure phase It is flat.

Then, the 5th dummy gate structure and the 6th dummy gate structure are removed, forms first grid knot in interlayer dielectric layer Structure groove and second grid texture grooves form the first metal gate structure, second later in first grid texture grooves The second metal gate structure is formed in gate structure groove.In this way, first grid structure and second grid structure are formed.

Certainly, in other embodiments, the first metal gate structure and the second metal gate structure, first grid knot are not formed Structure and second grid structure are all that polysilicon gate construction also belongs to protection scope of the present invention.

Then, patterned 4th mask layer is formed on interlayer dielectric layer, using patterned 4th mask layer as exposure mask To the first barrier material layer and its under fin perform etching, form first through hole in first barrier material layer, and Drain recesses are formed in fin.At this moment, remaining first barrier material layer is positioned at the first barrier layer of drain recesses two sides.It is right Second barrier material layer of the first grid structure far from drift region side and its under semiconductor substrate perform etching, described One gate structure forms the first source electrode far from forming the second through-hole in the second barrier material layer of drift region side in fin Groove.The second through-hole is also formed in second barrier material layer of the second grid structure far from drift region side, and in fin The second source electrode groove is formed in portion.At this moment, positioned at the second barrier layer of the first source electrode groove two sides and positioned at the second source electrode groove Second barrier layer of two sides is also formed.

Then, side wall is respectively formed in the first through hole side wall, the second through-hole side wall.

Then, drain material layer is formed in the drain recesses.The first source electrode material is formed in the first source electrode groove Layer.The second source electrode material layer is formed in the second source electrode groove, and drain material layer is formed in drain recesses.

Certainly, in other embodiments, the second barrier material layer for not forming the 5th dummy gate structure side also belongs to this hair Bright protection scope.

Certainly, in other embodiments, the second barrier material layer for not forming the 6th dummy gate structure side also belongs to this hair Bright protection scope.

Certainly, in other embodiments, the second barrier material layer is not formed and also belongs to protection scope of the present invention.

Certainly, in other embodiments, the first barrier material layer is not formed and also belongs to protection scope of the present invention.

Embodiment two

With reference to Figure 13, the present invention also provides a kind of LDMOS transistor structure, which is two adjacent Ldmos transistor share a drain electrode the case where.It specifically includes:

Semiconductor lining 20, the semiconductor substrate 20 have fin 201, have in the fin 20 well region (not shown) and The drift region 203 surrounded by well region, the well region are opposite with the injection type of the drift region；

Across the fin 201 and it is covered each by the first grid structure 21 and second at the top of the fin 201 with side wall Gate structure 22, the first grid structure 21 and second grid structure 22 partially cover the drift region 203 respectively；

Across the fin 201 and it is covered each by 201 top of fin and the first barrier layer 231 of side wall and the first resistance Barrier 232, the first barrier layer 231 and the second barrier layer 232 are all located between first grid structure 21 and second grid structure 22 Drift region on；

Across the fin 201 and it is covered each by 201 top of fin and the second barrier layer 241 of side wall and the second resistance Barrier 242, the second barrier layer 241 is on fin 201 of the first grid structure 21 far from 203 side of drift region, and Two barrier layers 242 are on fin of the second grid structure 22 far from 203 side of drift region.

The drain electrode in fin between the first barrier layer 231 and the first barrier layer 232；

The first source electrode in fin between first grid structure 21 and second barrier layer 241；

The second source electrode in fin between second grid structure 22 and second barrier layer 242.

Wherein, first grid structure 21 and second grid structure 22 are polysilicon gate construction or metal gate structure.

The distance between first barrier layer 231 and the first barrier layer 232 are first distance H1, first grid structure 21 and the The distance between two barrier layers 242 are second distance H2, and the distance between second grid structure 22 and the second barrier layer 242 are the Three distance H3.The first distance H1, second distance H2 and third distance H3 are more than or equal to 0.01 micron and to be less than or equal to 0.2 Micron.

Specifically please refer to embodiment one.

Embodiment three

With reference to Figure 14, the present embodiment provides a kind of forming method of ldmos transistor, the areas of the present embodiment and embodiment one Not are as follows: the drain electrode not instead of common drain in ldmos transistor that the present embodiment is formed, an individually drain electrode 36, each The corresponding source electrode 35 of drain electrode 36.Only one gate structure 31 between the source electrode 35 and drain electrode 36.It covers 31 part of gate structure It covers on drift region 303.

The first barrier layer 321 and the first barrier layer 322 are formed on drift region, for defining position and the width of drain electrode 36 Degree.The distance between first barrier layer 321 and the first barrier layer 322 are first distance H1.

The second barrier layer 34 is formed in semiconductor substrate of the gate structure far from 303 side of drift region, with gate structure 31 define the position of source electrode and width together.The distance between second barrier layer 34 and gate structure 31 are second distance H2.

First distance H1 and second distance H2 is more than or equal to 0.01 micron and to be less than or equal to 0.2 micron.

Specific forming method please refers to embodiment one.

Example IV

With reference to Figure 14, the present invention also provides a kind of ldmos transistors, comprising:

Semiconductor substrate 30, the semiconductor substrate 30 have fin 301, and the fin 301 has well region (not shown) With the drift region 303 surrounded by the well region；

Across the fin 301 and it is covered each by the gate structure 31 at the top of the fin with side wall, the gate structure The 31 covering drift regions 303；

Across the fin and it is covered each by the second barrier layer 34 at the top of the fin with side wall, second barrier layer 34 on fin 301 of the gate structure far from 303 side of drift region；

Across the fin 301 and it is covered each by the top of the fin and the first barrier layer 331 of side wall and the first blocking Layer 332, the first barrier layer 331 and the first barrier layer 332 are all located on the drift region 303；

The drain electrode 36 in fin between the first barrier layer 331 and the first barrier layer 332；

The source electrode 35 in fin between gate structure 31 and second barrier layer 34.

Above-described embodiment can specifically be referred to.

Embodiment five

With reference to Figure 15, the present embodiment provides a kind of forming method of ldmos transistor, the areas of the present embodiment and embodiment one It is not that the semiconductor substrate 40 of the present embodiment does not have fin.The transistor being subsequently formed is planar transistor.First grid knot Structure 41, second grid structure 42, the first barrier layer 431 and the first barrier layer 432, the second barrier layer 441 and the second barrier layer 442 It is not across fin yet.First grid structure 41, second grid structure 42, the first barrier layer 431 and the first barrier layer 432, Second barrier layer 441 and the second barrier layer 442 are formed directly into semiconductor substrate 40.

The position and width of first barrier layer 431 and the first barrier layer 432 definition drain electrode 46.Drain electrode 46 is two phase vincial faces The common drain of body pipe.

Second barrier layer 441 and first grid structure 41 define position and the width of the first source electrode 451.

Second barrier layer 442 and second grid structure 42 define position and the width of the second source electrode 452.

Specific forming method please refers to embodiment one.

Embodiment six

With reference to Figure 15, the present invention provides a kind of ldmos transistor, comprising:

Semiconductor substrate 40, the drift region that the semiconductor substrate 40 has well region (not shown) and surrounded by the well region 403；

First grid structure 41 and second grid structure 42 in semiconductor substrate, 41 He of first grid structure Second grid structure 42 partially covers the drift region 403 respectively；

The first barrier layer 431 and the first barrier layer 432 in semiconductor substrate, the first barrier layer 431 and the first resistance Barrier 432 is all located on the drift region 403 between first grid structure 41 and second grid structure 42；

The second barrier layer 441 and the second barrier layer 442 in semiconductor substrate, the second barrier layer 441 is described In semiconductor substrate of one gate structure 41 far from 403 side of drift region, the second barrier layer 442 is in the second grid knot In semiconductor substrate of the structure 42 far from 403 side of drift region.

The drain electrode 46 in semiconductor substrate between the first barrier layer 431 and the first barrier layer 432；

The first source electrode 451 in semiconductor substrate between first grid structure 41 and second barrier layer 441；

The second source electrode 452 in semiconductor substrate between second grid structure 42 and second barrier layer 442.

Above-described embodiment one and embodiment two can specifically be referred to.

Embodiment seven

With reference to Figure 16, the present embodiment provides a kind of forming method of ldmos transistor, the areas of the present embodiment and embodiment six Not are as follows: the drain electrode 56 in ldmos transistor that the present embodiment is formed is not common drain, and each ldmos transistor only has one A drain electrode 56.It is corresponding with source electrode 55.Only one gate structure 51 between the source electrode 55 and drain electrode 56.51 part of gate structure It is covered on drift region 503.

It specifically can be with reference implementation example five and embodiment six.

Embodiment eight

With reference to Figure 16, the present invention also provides a kind of ldmos transistors, comprising:

Semiconductor substrate 50, the semiconductor substrate have drift region 503；

The gate structure 51 in semiconductor substrate 50, the gate structure 51 cover the drift region 503；

The second barrier layer 54 in semiconductor substrate 50, second barrier layer 54 are separate in the gate structure 51 In the semiconductor substrate 50 of 503 side of drift region；

Positioned at the first barrier layer 531 and the first barrier layer 532 of semiconductor substrate, the first barrier layer 531 and first stops Layer 53 is all located on the drift region 503；

The drain electrode 56 in semiconductor substrate between the first barrier layer 531 and the first barrier layer 532；

The source electrode 55 in semiconductor substrate between gate structure 51 and second barrier layer 54.

Above-described embodiment five, embodiment six and embodiment seven can specifically be referred to.

Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims

1. a kind of forming method of ldmos transistor characterized by comprising

Semiconductor substrate is provided；

Drift region is formed in the semiconductor substrate；

Source electrode material layer and drain material layer, the drain material layer are formed in the semiconductor substrate of the gate structure two sides In the drift region；

Ion implanting is carried out to the source electrode material layer and drain material layer, forms source electrode and drain electrode；

It is formed before source electrode material layer and drain material layer, further includes: in side of the gate structure far from the drift region The second barrier layer is formed, the thickness on second barrier layer is equal to the thickness of the gate structure, and second barrier layer is used for Define position and the width of the source electrode.

2. forming method as described in claim 1, which is characterized in that the semiconductor substrate also has well region, the well region Surround the drift region.

3. forming method as claimed in claim 2, which is characterized in that the injection type of the drift region and the note of the well region It is opposite to enter type.

4. forming method as described in claim 1, which is characterized in that the gate structure is polysilicon gate construction.

5. forming method as claimed in claim 4, which is characterized in that formed after the source electrode and the drain electrode, further include The following steps:

The partial polysilicon gate structure far from drift region side is removed, forms gate structure groove in interlayer dielectric layer；

Metal gate structure is formed in the gate structure groove, the metal gate structure part covers the drift region, The remaining polysilicon gate construction is the first barrier layer, first barrier layer is for defining institute on the drift region State position and the width of drain electrode.

6. forming method as claimed in claim 5, which is characterized in that the semiconductor in the polysilicon gate construction two sides serves as a contrast Before the step of forming source electrode material layer and drain material layer in bottom, further includes: the shape around the polysilicon gate construction At side wall.

7. forming method as described in claim 1, which is characterized in that determine in the two sides of the source electrode on second barrier layer The position of the justice source electrode and width, alternatively, with the gate structure opposite one of second barrier layer in the source electrode Side defines position and the width of the source electrode with the gate structure.

8. forming method as described in claim 1, which is characterized in that second barrier layer is polysilicon gate construction.

9. forming method as described in claim 1, which is characterized in that further include: form source electrode material layer and drain material layer Before, side wall is formed around second barrier layer.

10. forming method as described in claim 1, which is characterized in that in the semiconductor substrate of the gate structure two sides Form source electrode material layer and drain material layer, comprising:

Using the gate structure as exposure mask, to performing etching to form source electrode groove in the semiconductor substrate of the gate structure two sides And drain recesses；

Source electrode material layer is formed in the source electrode groove；

Drain material layer is formed in the drain recesses.

11. forming method as described in claim 1, which is characterized in that when the ldmos transistor is PMOS transistor, institute It states source electrode material layer and the drain material layer is germanium silicon layer；When the ldmos transistor is NMOS transistor, the source electrode material The bed of material and the drain material layer are silicon carbide layer.

12. forming method as described in claim 1, which is characterized in that before forming source electrode material layer and drain material layer, The second barrier material layer is formed far from the side of the drift region in the gate structure, alternatively, in the another of the gate structure The first barrier material layer is formed on the drift region of side；

Semiconductor substrate under first barrier material layer and first barrier material layer is performed etching, is stopped described first First through hole is formed in material layer, and forms drain recesses in the semiconductor substrate, and remaining first barrier material layer is First barrier layer, alternatively,

Semiconductor substrate under second barrier material layer and second barrier material layer is performed etching, is stopped described second The second through-hole is formed in material layer, and forms source electrode groove in semiconductor substrate, and remaining second barrier material layer is second Barrier layer；

13. forming method as described in claim 1, which is characterized in that before forming source electrode material layer and drain material layer, The second barrier material layer and in the other side of the gate structure is formed far from the side of the drift region in the gate structure Drift region on form the first barrier material layer；

To the first barrier material layer and its under semiconductor substrate perform etching, form first in first barrier material layer Through-hole, and drain recesses are formed in semiconductor substrate, remaining first barrier material layer is the first barrier layer；

To the second barrier material layer and its under semiconductor substrate perform etching, form second in second barrier material layer Through-hole, and source electrode groove is formed in semiconductor substrate, remaining second barrier material layer is the second barrier layer；

14. forming method as described in claim 12 or 13, which is characterized in that first barrier layer and described second stops Layer is polysilicon gate construction.

15. forming method as described in claim 1, which is characterized in that two adjacent ldmos transistor common drains or Person is respectively provided with drain electrode.

16. a kind of ldmos transistor, comprising: semiconductor substrate, the gate structure in the semiconductor substrate are located at institute State the source electrode and drain electrode in the semiconductor substrate of gate structure two sides；

It is characterized by further comprising:

Drift region, the drift region are located in the semiconductor substrate, and the gate structure part covers the drift region, and institute Drain electrode is stated to be located in the drift region；

First barrier layer, on the drift region of the gate structure side, for defining position and the width of the drain electrode；

Second barrier layer, in side of the gate structure far from the drift region, for defining position and the width of the source electrode Degree.

17. ldmos transistor as claimed in claim 16, which is characterized in that first barrier layer and described second stops Layer is polysilicon gate construction.

18. ldmos transistor as claimed in claim 16, which is characterized in that two adjacent ldmos transistors leak altogether Pole is respectively provided with drain electrode.