CN105512071B - High speed interface host-side controller - Google Patents

Abstract

The host-side controller of low data dithering, low speed data is provided with logical network layer, transfers to electronic physical layer to be converted to high speed data delivery to external device (ED) via across time domain data transport module.The clock signal of the electronic physical layer operation is also transferred to the logical network layer, the logical network layer is provided first low speed data according to this.It is the low speed data that the external device (ED) provides that across the time domain data transport module reads in the logical network layer according to logical network layer end clock, and exports first low speed data to the electronic physical layer according to electronic physical layer end clock.

Description

High-speed data interface host-side controller

technical field

The invention relates to a high-speed data interface host controller, in particular to a high-speed data interface host controller for high-speed transmission with external devices.

Background technique

High-speed data interfaces, such as: Serial Advanced Technology Attachment (SATA), Peripheral Interconnect Express (PCIE), Secure Digital Input/Output Card (SDIO), Universal Serial Bus (USB), etc., are easily delayed by clock signals , and data jitter occurs; it obviously affects high-speed data transmission.

Contents of the invention

The present invention provides a low data jitter host controller (host controller), which can also be realized by the south bridge of the chipset.

A high-speed data interface host controller implemented according to an embodiment of the present invention includes a logical physical layer, an electronic physical layer, and a cross-time domain data transmission module. The logical physical layer provides the first low-speed data, which is then converted into the first high-speed data by the electronic physical layer and transmitted to the first external device. The clock signal used for the operation of the electronic physical layer is also transmitted to the logical physical layer, so that the logical physical layer provides the first low-speed data accordingly. The cross-time domain data transmission module is coupled between the logical physical layer and the electronic physical layer, reads in the first low-speed data provided by the logical physical layer for the first external device according to the logical physical layer terminal clock , and output the first low-speed data to the electronic physical layer according to the electronic physical layer terminal clock.

The cross-time domain data transmission module of the invention effectively solves the asynchronous problem of the operation clock at the electronic physical layer end and the logical physical layer end.

Hereinafter, specific embodiments are cited, and the contents of the present invention are described in detail in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a block diagram illustrating a high-speed data interface host controller 100 implemented according to an embodiment of the present invention;

2A and 2B illustrate the cross-time domain data transmission module TXCDC according to an embodiment of the present invention;

FIG. 3 illustrates the operation of the buffer R_A1 with a waveform diagram, wherein the buffers numbered 0-7 of the buffer R_A1 are respectively named R_A1_0-R_A1_7; and

FIG. 4 is a block diagram illustrating a host-side controller 400 implemented according to an embodiment of the present invention, which connects at least one external device with a single electronic physical layer EPHY.

Detailed ways

The following description lists various embodiments of the present invention. The following description introduces the basic concept of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the claims.

FIG. 1 is a block diagram illustrating a high-speed data interface host-side controller 100 implemented according to an embodiment of the present invention. The high-speed data interface host-side controller 100 includes a logical physical layer LPHY (the number is the same as the logical physical layer (logical physical layer) abbreviated LPHY), a plurality of electronic physical layers (electrical physical layer, abbreviated EPHY) EPHYA and EPHYB, a multiplexer ECLKMUX, and Cross-time domain data transmission module TXCDC. Only two electronic physical layers are shown in FIG. 1 , but the present invention is not limited thereto.

The electronic physical layers EPHYA and EPHYB are connected to external devices; the electronic physical layer EPHYA is connected to the hard disks HDA1 and HDA2, and the electronic physical layer EPHYB is connected to the hard disks HDB1 and HDB2. The electronic physical layers EPHYA and EPHYB operate according to the clock signals MPLLCLK_A and MPLLCLK_B respectively; the clock signal MPLLCLK_A can be internally generated by the electronic physical layer EPHYA, and the clock signal MPLLCLK_B can be internally generated by the electronic physical layer EPHYB. It should be noted that the electronic physical layers EPHYA and EPHYB in FIG. 1 are only connected to two hard disks, but the present invention does not limit the type and quantity of external devices connected to each electronic physical layer.

The multiplexer ECLKMUX receives the clock signals MPLLCLK_A and MPLLCLK_B corresponding to the electronic physical layers EPHYA and EPHYB, and outputs a common clock signal MPLLCLK_COM. The common clock signal MPLLCLK_COM will be introduced into the logical physical layer LPHY and the cross-time domain data transmission module TXCDC.

For hard disks HDA1, HDA2, HDB1 and HDB2, circuit modules PHYA1, PHYA2, PHYB1 and PHYB2 in the logical physical layer LPHY provide low-speed data DA1_COM, DA2_COM, DB1_COM, DB2_COM based on the common clock signal MPLLCLK_COM and transmit them to the cross-time domain data transmission Module TXCDC.

The cross-time domain data transmission module TXCDC is coupled between the logical physical layer LPHY and the electronic physical layers EPHYA and EPHYB, and operates based on clock domain crossing. The cross-time domain data transmission module TXCDC reads in the above-mentioned low-speed data DA1_COM, DA2_COM, DB1_COM, DB2_COM provided by the logical physical layer LPHY according to the common clock signal MPLLCLK_COM. In one embodiment, the cross-time domain data transmission module TXCDC provides each of the external devices HDA1 , HDA2 , HDB1 and HDB2 with a buffer (shown in FIG. 2A , FIG. 2B ) to buffer low-speed data corresponding to different external devices. The cross-time domain data transmission module TXCDC also fetches the low-speed data from the above buffer according to the clock signals corresponding to the corresponding electronic physical layer EPHYA and EPHYB (the electronic physical layer EPHYA corresponds to the clock signal MPLLCLK_A, and the electronic physical layer EPHYB corresponds to the clock signal MPLLCLK_B). Referring to the figure, the low-speed data DA1_A extracted according to the clock signal MPLLCLK_A is converted into high-speed data by the electronic physical layer EPHYA and then sent to the hard disk HDA1, and the low-speed data DA2_A extracted according to the clock signal MPLLCLK_A is converted into high-speed data by the electronic physical layer EPHYA and sent to the hard disk HDA2, the data DB1_B taken out according to the clock signal MPLLCLK_B is converted into high-speed data by the electronic physical layer EPHYB and sent to the hard disk HDB1, and the data DB2_B taken out according to the clock signal MPLLCLK_B is converted into high-speed data by the electronic physical layer EPHYB and sent to the hard disk HDB2. In particular, each cache has a multi-layer cache depth, so that low-speed data read-in cache and data read-out cache can be implemented across time domains.

As shown in Figure 1, the logical physical layer LPHY operated solely according to the common clock signal MPLLCLK_COM will lower the design threshold. Different circuit modules (such as PHYA1, PHYA2 and PHYB1, PHYA2) corresponding to different electronic physical layers (such as EPHYA and EPHYB) of the logical physical layer LPHY of the conventional technology operate according to clock signals (such as MPLLCLK_A and MPLLCLK_B) of different electronic physical layers, Since the clock signals of each electronic physical layer (such as MPLLCLK_A and MPLLCLK_B) are asynchronous clock signals, the clock tree (Clock Tree) will be complicated, and the logical physical layer LPHY operated solely according to the common clock signal MPLLCLK_COM in the present invention will greatly simplify the clock tree. In addition, the cross-time domain data transmission module TXCDC arranged between the logical physical layer LPHY and the electronic physical layers EPHYA and EPHYB will effectively suppress the wiring delay problem. Compared with the traditional technology that directly couples the logical physical layer to the long trace of the electronic physical layer, the cross-time domain data transmission module TXCDC cuts the data trace in half and corrects the trace delay in time.

In one embodiment, the routing distance of the clock signals MPLLCLK_A and MPLLCLK_B is used to determine which of the electronic physical layers EPHYA and EPHYB is closest to the logical physical layer LPHY. Figure 1 is the electron physical layer EPHYA is the closest electron physical layer. The multiplexer ECLKMUX uses the clock signal MPLLCLK_A of the nearest electronic physical layer EPHYA as the common clock signal MPLLCLK_COM, so that the clock signal MPLLCLK_A with less wiring delay is used by the logical physical layer LPHY. It is worth noting that, in one embodiment, the wiring distance here refers to the wiring distance of the clock signals MPLLCLK_A and MPLLCLK_B from the electronic physical layer EPHYA and EPHYB to the multiplexer ECLKMUX in an ASIC (Application Specific Integrated Circuits, ASIC) . In the aforementioned embodiments, the selection of the common clock signal MPLLCLK_COM according to the routing distance of the clock signal is based on the premise that the clock signals MPLLCLK_A and MPLLCLK_B are asynchronous clocks with the same frequency. If the frequencies of the clock signals MPLLCLK_A and MPLLCLK_B are different, other The mode selects the common clock signal MPLLCLK_COM, which will be described later.

In one embodiment, the distance from the cross-time domain data transmission module TXCDC to the logical physical layer LPHY (transmitting DA1_COM, DA2_COM, DB1_COM, DB2_COM) is designed to be shorter than the distance from the nearest electronic physical layer EPHYA to the logical physical layer LPHY, or even The routing distance (transmitting DA1_A, DA2_A, DB1_B, DB2_B) from the cross-time domain data transmission module TXCDC to the closest electronic physical layer EPHYA is also designed to be shorter than the distance from the closest electronic physical layer EPHYA to the logical physical layer LPHY. Such design tips will make the correction of the data routing delay by the cross-time domain data transmission module TXCDC more accurate.

In one embodiment, the logical physical layer LPHY provides low-speed data DA1_COM, DA2_COM, DB1_COM, DB2_COM to the cross-time domain data transmission module TXCDC in parallel, and the cross-time domain data transmission module TXCDC sends low-speed data DA1_A, DA2_A, DB1_B in parallel , DB2_B to the electronic physical layer EPHYA and EPHYB, and the electronic physical layer EPHYA and EPHYB include converting data DA1_A, DA2_A, DB1_B, DB2_B from parallel low-speed data to serial high-speed data (such as differential signals) before transferring to hard disk HDA1, HDA2 , HDB1 and HDB2. This design makes the low-speed logical physical layer LPHY combined with the high-speed electronic physical layer EPHYA and EPHYB, which is conducive to the realization of high-speed data interfaces, such as: Serial Advanced Technology Attachment (SATA), Express Peripheral Interconnect Standard (PCIE), secure digital input/ Output card (SDIO), Universal Serial Bus (USB), etc.

In one embodiment, the clock signals MPLLCLK_A and MPLLCLK_B and the common clock signal MPLLCLK_COM have the same frequency, which is 300 MHz. The logical physical layer LPHY and the cross-time domain data transmission module TXCDC are 20-bit parallel transmission, and the electronic physical layer EPHYA can realize 6Gbps high-speed serial transmission.

The embodiment in FIG. 1 is not intended to limit the number of electronic physical layers, the number of external devices connected to the electronic physical layers, and the relative layout of the electronic physical layers and logical physical layers. Furthermore, the clock signals of multiple electronic physical layers are allowed to be of different frequencies. It is assumed that the frequency of the clock signal MPLLCLK_A of the electronic physical layer EPHYA is 300 MHz, and the frequency of the clock signal MPLLCLK_B of the electronic physical layer EPHYB is 150 MHz. In this embodiment, the multiplexer ECLKMUX will not consider the wiring distance of the clock signals MPLLCLK_A and MPLLCLK_B, but uses the clock signal MPLLCLK_A with the highest frequency as the common clock signal MPLLCLK_COM. The logical physical layer LPHY includes a frequency divider to divide the 300Mz common clock signal MPLLCLK_COM to obtain multiple frequency-divided common clock signals (not shown), for example, to obtain a 150Mz clock signal. The circuit modules PHYA1 and PHYA2 in the logical physical layer LPHY operate according to the common clock signal MPLLCLK_COM of 300MHz (such as providing low-speed data DA1_COM and DA2_COM), while the circuit modules PHYB1 and PHYB2 operate according to the 150MHz clock signal obtained by frequency division (such as providing low-speed data DB1_COM and DB2_COM). Among them, each circuit module in the logical physical layer LPHY operates the clock signal corresponding to the electronic physical layer (EPHYA and EPHYB) connected to the external device (HDA1 and HDA2, HDB1 and HDB2) corresponding to each circuit module according to which frequency-division common clock signal (MPLLCLK_A and MPLLCLK_B) depends on the clock frequency, that is, the clock frequency of the frequency-divided common clock signal of each circuit module is the same as the clock frequency of the clock signal corresponding to the electronic physical layer connected to the external device corresponding to each circuit module. In another embodiment, the cross-time-domain data transmission module TXCDC further includes a frequency divider to divide the common clock signal MPLLCLK_COM of 300MHz to obtain multiple frequency-divided common clock signals (not shown), for example, to obtain a 150MHz clock signal The data DA1_COM, DA2_COM are read in by the frequency division common clock signal (frequency is 300MHz) of the clock frequency 300MHz of the clock signal MPLLCLK_A of the clock signal MPLLCLK_A of the electronic physical layer EPHYA that the corresponding hard disk HDA1 and HDA2 are connected, and the data DA1_COM, DA2_COM are read in by the cross-time domain data transmission module TXCDC The data DB1_COM and DB2_COM are read into the corresponding cache by the frequency-divided common clock signal (frequency 150MHz) corresponding to the clock signal MPLLCLK_B of the electronic physical layer EPHYB connected to the hard disks HDB1 and HDB2 with a clock frequency of 150MHz. It is worth noting that the cross-time domain data transmission module TXCDC reads the data DA1_A and DA2_A according to the clock signal MPLLCLK_A of the electronic physical layer EPHYA connected to the corresponding hard disk HDA1 and HDA2, and reads the data DB1_B and DB2_B according to the corresponding hard disk The clock signal MPLLCLK_B of the electronic physical layer EPHYB connected to HDB1 and HDB2.

FIG. 2A and FIG. 2B illustrate a cross-time domain data transmission module TXCDC according to an embodiment of the present invention. The cross-time domain data transmission module TXCDC provides buffers R_A1, R_A2, R_B1 and R_B2 corresponding to the hard disks HDA1, HDA2, HDB1 and HDB2 respectively, and each includes, for example, 8 buffers numbered 0 to 7 (the size of each buffer is the same as the parallel low-speed data size) , that is, the cache depth includes 0 to 7. The low-speed data DA1_COM, DA2_COM, DB1_COM, and DB2_COM provided by the logical physical layer LPHY are first read into the buffer W_Buf according to the common clock signal MPLLCLK_COM, and then written into the index generator WPTR++ and written into the distributor W_DMUX according to the common clock signal MPLLCLK_COM to transfer the corresponding The low-speed data DA1_COM, DA2_COM, DB1_COM, DB2_COM are then pushed into the registers in the buffers R_A1, R_A2, R_B1 and R_B2. The contents of the buffers in R_A1, R_A2, R_B1 and R_B2 can also be read in the index generator RPTR++ according to the corresponding clock signals MPLLCLK_A and MPLLCLK_B to operate the read selector R_MUX to read the corresponding low-speed data to the buffer R_Buf, Then output as data DA1_A, DA2_A, DB1_B, DB2_B through the buffer R_Buf according to the corresponding clock signal MPLLCLK_A/MPLLCLK_B.

FIG. 3 uses a waveform diagram to illustrate the operation of the buffer R_A1, wherein the registers numbered 0-7 of the buffer R_A1 are respectively named R_A1_0-R_A1_7. The parallel data D0-D7 pushed into the buffer R_A1 of the registers R_A1_0-R_A1_7 with different buffer depths according to the common clock signal MPLLCLK_COM will be successfully fetched through the clock signal MPLLCLK_A and reflected on the data DA1_A. The data D8-D15 pushed into the buffer R_A1 according to the common clock signal MPLLCLK_COM will update the registers R_A1_0-R_A1_7 one by one. The data D8-D15 of the registers R_A1_0-R_A1_7 with different buffer depths will also be fetched smoothly through the clock signal MPLLCLK_A, and reflected on the data DA1_A.

FIG. 4 is a block diagram, describing a high-speed data interface host-side controller 400 implemented according to an embodiment of the present invention, for connecting at least one external device with a single electronic physical layer EPHY. The illustration includes hard disks HD1 and HD2, correspondingly, across time The domain data transmission module TXCDC includes two sets of cache designs. The logical physical layer LPHY and the cross-time domain data transmission module TXCDC can transmit data in parallel. The electronic physical layer EPHY may include parallel-to-serial conversion.

Compared with the high-speed data interface host-side controller 100 in FIG. 1 is also designed with a multiplexer ECLKMUX, the clock signal of the single electronic physical layer EPHY on the host-side controller 400 in FIG. The layer LPHY is referenced by the circuit modules PHY_1 and PHY_2 to output the first and second low-speed data respectively. In Fig. 4, the cross-time domain data transmission module TXCDC receives the logical physical layer end clock (hereinafter also referred to as MPLLCLK_L) from the logical physical layer end node MPLLCLK_L on the clock signal line CLK_trace, and transmits the clock signal from the electronic circuit of the clock signal line CLK_trace. The physical layer end node MPLLCLK_E receives the electronic physical layer end clock (hereinafter also referred to as MPLLCLK_E). The logical physical layer end node MPLLCLK_L is the node that is input to the cross-time domain data transmission module TXCDC on the same side as the logical physical layer LPHY on the clock signal line CLK_trace, and the electronic physical layer end node MPLLCLK_E is the node connected to the clock signal line CLK_trace. The same side of the electronic physical layer EPHY is input to the node of the cross-time domain data transmission module TXCDC. The logical physical layer end node MPLLCLK_L is closer to the logical physical layer LPHY on the clock signal trace CLK_trace than the electronic physical layer end node MPLLCLK_E. The cross-time domain data transmission module TXCDC in Figure 4 can still effectively solve the problem of clock signal routing delay. In one embodiment, the wiring distance from the cross-time domain data transmission module TXCDC to the logical physical layer LPHY is designed to be shorter than the clock signal wiring CLK_trace, and the cross-time domain data transmission module TXCDC to the electronic physical layer EPHY The trace distance is shorter than the clock signal trace CLK_trace. Compared with the traditional technology that directly couples the logical physical layer to the long trace of the electronic physical layer, the cross-time domain data transmission module TXCDC cuts the data trace in half and corrects the trace delay in time.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (9)

1. A kind of 1. high speed interface host-side controller, it is characterised in that including：

   Logical network layer and electronic physical layer, wherein, the logical network layer provides the first low speed data, then by the electronics physics Layer is converted to the first high-speed data, and is transferred to the first external device (ED), and the clock signal of the electronic physical layer operation also passes The logical network layer is handed to, the logical network layer is provided first low speed data according to this；And

   Across time domain data transport module, it is coupled between the logical network layer and the electronic physical layer, according to logical physical It is first low speed data that first external device (ED) provides that layer end clock, which reads in the logical network layer, and according to electronics physics Layer end clock exports first low speed data to the electronic physical layer.
2. 2. high speed interface host-side controller according to claim 1, it is characterised in that：

   It is somebody's turn to do across time domain data transport module and also provides the first caching for first external device (ED), caches according to the logical physical First low speed data that layer end clock is read in.
3. 3. high speed interface host-side controller according to claim 1, it is characterised in that also include：

   Clock signal cabling, the clock signal is transferred to the logical network layer from the electronic physical layer,

   Wherein, across time domain data transport module is somebody's turn to do from the logic thing of the logical network layer end node reception on the clock signal cabling Manage layer end clock, and from the electronic physical layer end node reception of the clock signal cabling electronic physical layer end clock.
4. 4. high speed interface host-side controller according to claim 3, it is characterised in that the logical network layer end segment Point close logical network layer on the clock signal cabling compared with the electronic physical layer end node.
5. 5. high speed interface host-side controller according to claim 3, it is characterised in that：

   The cable run distance of across time domain data transport module to the logical network layer is shorter than the clock signal cabling；And

   Across the time domain data transport module to the cable run distance of the electronic physical layer is shorter than the clock signal cabling.
6. 6. high speed interface host-side controller according to claim 1, it is characterised in that：

   The logical network layer provides first low speed data in a parallel fashion extremely should across time domain data transport module；

   It is somebody's turn to do across time domain data transport module and sends first low speed data in a parallel fashion to the electronic physical layer；And

   The electronic physical layer just transmitted after first low speed data is converted into serial high speed from parallel low speed data to First external device (ED).
7. 7. high speed interface host-side controller according to claim 1, it is characterised in that：

   The logical network layer also provides the second low speed data and is converted to the second high-speed data by the electronic physical layer, and is transferred to Two external device (ED)s；

   Should across time domain data transport module always according to the logical network layer end clock read in the logical network layer for this outside second Second low speed data that device provides, and second low speed data is exported to the electricity according to the electronic physical layer end clock Muon physics layer.
8. 8. high speed interface host-side controller according to claim 7, it is characterised in that：

   It is somebody's turn to do across time domain data transport module and also provides the second caching for the electronic physical layer, caches according to the logical network layer Second low speed data for holding clock to read in.
9. 9. high speed interface host-side controller according to claim 1, it is characterised in that：

   The clock signal, the logical network layer end clock and the electronic physical layer end clock are same clock source.