CN105453450B - A kind of time delay correction method and device - Google Patents

Abstract

The invention discloses a kind of time delay adjustment method and devices, are related to field of signal processing, can be realized the high-precision time-delay adjustment function that is input to output of the analog signal from time delay adjustment device.Concrete implementation method includes: the decimal time delay and time delay correction parameter between the feedback channel and transmission channel of time delay adjustment device acquisition wireless base system；Wherein, time delay adjustment parameter includes over-sampling multiple L；The data-interface cycle T that decimal time delay is a times ', 0 < a < 1；According to over-sampling multiple L and decimal time delay, it determines the sampling clock cycle T for needing to adjust Y time delay adjustment device in the sample clock frequency F data field of time delay adjustment device, the delay requirement in the data-interface rate F' data field of time delay adjustment device of decimal time delay can be met；Wherein, Y is the natural number greater than 1, and the Y is the rounding acquisition that is multiplied by a with L, T'=L*T；Y T is adjusted in F data field, and F is dropped to by F' by multistage pumping value.The present invention is applied to time delay adjustment.

Description

A kind of time delay correction method and device

technical field

The present invention relates to the field of signal processing, and in particular, to a time delay correction method and device.

Background technique

In the wireless base station system, in order to obtain a better transmitted signal, it is usually necessary to sample, model and digitally pre-correct the analog signal output by the antenna feedback. The requirements for the versatility and flexibility of the wireless base station are getting higher and higher, which makes the wireless base station system more sensitive to the loop fractional delay between the transmission channel and the feedback channel in the system, which affects the digital predistortion (Digital predistortion).

The limit correction capability of Pre-Distortion (DPD for short) also makes it impossible for the wireless base station system to obtain high-quality transmitted signals.

Specifically, in an ideal state, after a transmission signal passes Δt time on the transmission channel, the feedback signal of the transmission signal is sampled in the feedback channel. The minimum step delay is corrected, so that the wireless base station system often has a fractional delay that cannot be compensated for the sampled signal and the original transmitted signal after compensating for the integer delay. This fractional delay is is the loop fractional delay. The wireless base station system cannot complete signal alignment when the delay is less than one minimum step, resulting in inaccurate mathematical modeling and inaccurate correction results, thus affecting the limit correction capability of DPD. Today, although some schemes can theoretically compensate the fractional delay as much as possible, the compensation accuracy in practical applications is not high, which not only costs too much to implement, but also reduces the performance of the wireless base station system.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a time delay correction method and device, which can realize a high-precision time delay adjustment function of an analog signal from the input to the output of the time delay correction device.

To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

In a first aspect, a time delay correction device is provided, which is applied to a wireless base station system. The device includes: a data acquisition module, a data processing module connected to the data acquisition module, and X series connected to the data processing module. A delay module, a selection module connected to each serially connected delay module, and N series-connected extraction modules connected to the selection module, the extraction levels of the N extraction modules are set to N levels, Each draw module corresponds to one level, where:

The data acquisition module is used to acquire the fractional delay and delay correction parameters between the feedback channel and the transmission channel of the wireless base station system; wherein the delay correction parameters include the oversampling multiple L of the delay correction device ; The data interface period T' of the time delay correction device whose fractional time delay is a times, 0<a<1;

The data processing module is configured to determine, according to the oversampling multiple L and the fractional delay, that the sampling clock frequency F of the delay correction device needs to be adjusted in the data domain of Y samples of the delay correction device The clock period T is to meet the time delay requirement of the fractional time delay in the data interface rate F' data domain of the time delay correction device; wherein, the Y is a natural number greater than 1, and the Y is determined by a Multiply and round up with L, T'=L*T, F=1/T, F'=1/T';

the selection module, after connecting the Y delay modules in series according to the Y after the X delay modules, each delay module is reconnected to the selection module;

The Y serial delay modules are used to adjust Y T in the F data domain; each delay module adjusts one T; X is greater than or equal to Y;

The N series-connected extraction modules are used to reduce the F to the F' through N-level extraction.

In a first possible implementation manner of the first aspect, the decimation multiple of the decimation module is M, and L=M ^N :

The rth level extraction module in the N number of extraction modules is used to reduce the first data rate Fr before the _rth level extraction module extraction to the value after the rth extraction module extraction. the second data rate _Fr '; the said 1≤r≤N;

Wherein, the above-mentioned r-th level extraction module is any level extraction module among the N extraction modules.

In a second aspect, a time delay correction device is provided, which is applied to a wireless base station system. The device includes: a data acquisition module, a data processing module connected to the data acquisition module, and N time delays connected to the data processing module. Delay correction module; each delay correction module in the N delay correction modules corresponds to a drawing level, wherein:

The data acquisition module is used to acquire the fractional delay and delay correction parameters between the feedback channel and the transmission channel of the wireless base station system; wherein, the delay correction parameters include the decimation multiple M of the delay correction device and the oversampling multiple L; the data interface period T' of the time delay correction device whose fractional time delay is a times, 0<a<1;

The data processing module is configured to decompose the fractional delay into N pieces of delays to be corrected based on the extraction level of each delay correction module; wherein, each level of delay correction module corresponds to one piece of delay to be corrected; The N delays to be corrected are a ₁ , a ₂ , ..., a _N ; the delay to be corrected corresponding to the r-th stage delay correction module is a _r times T'; r∈(1,2,. ....., N);

The data processing module is further configured to determine, according to the decimation multiple M of the delay correction module, that each level of delay correction module needs to perform delay correction at this level when it meets the delay requirement of _ar times T'. The number Y _r of the clock period Tr adjusted in the data rate _Fr data domain of the module _; wherein, the _Fr and Tr are the data rate and data period before the decimation of the _r -th stage delay correction module, respectively, And satisfy T _r =1/F _r ; the Y _r is obtained by multiplying a _r and the decimation multiple M _{; r} '=M*Tr _;

The N time delay correction modules are used to sequentially adjust the time delay ar times T' to be corrected corresponding to the _r -th stage delay correction module according to Y _r .

In a first possible implementation manner of the second aspect, each delay correction module includes a decimation unit, a delay unit and a selection unit, the delay unit includes X delay subunits, and X is greater than 1 and X is greater than Yr, after the X delay subunits are connected in series, each delay subunit is connected to the selection unit, and the selection unit is also connected to the extraction unit;

The selection unit in the r-th stage delay correction module in the N delay correction modules is configured to connect Y _r delay subunits in series in the r-th stage delay correction module according to the Y _r , each delay subunit is connected to the selection unit in the r-level delay correction module;

The Y _r serial delay subunits are used to adjust Y _r Tr in the _Fr data domain _; each delay subunit adjusts one Tr _;

The decimation unit in the r-th stage delay correction module is used to reduce the Fr to the Fr'; wherein, the said 1≤r≤N;

Wherein, the above-mentioned r-th stage delay correction module is any level of delay correction module among the N delay correction modules.

In combination with the second aspect or the first possible implementation manner of the second aspect, in the second possible implementation manner of the second aspect, the data processing module determines the needs according to equation (1) and equation (2) The number Yr of clock cycles Tr adjusted under the data rate Fr data domain of the delay correction modules at all levels;

a*T'=(Y ₁ *M ⁰ +Y ₂ *M ¹ +...+Y _r *M ^r-1 +...+Y _N *M ^N-1 )*T (1)

a*T' ⁼ MN*T(2).

In a third aspect, a time delay correction method is provided, which is applied to a time delay correction device, and the time delay correction device is applied to a wireless base station system, including:

Acquire the fractional delay and delay correction parameters between the feedback channel and the transmission channel of the wireless base station system; wherein the delay correction parameters include the decimation multiple M and the oversampling multiple L of the delay correction device; the The data interface period T' whose fractional delay is a times, 0<a<1;

According to the oversampling multiple L and the fractional delay, it is determined that Y sampling clock periods T of the delay correction device need to be adjusted in the data domain of the sampling clock frequency F of the delay correction device, so as to satisfy all the requirements. The delay requirement of the fractional delay in the data interface rate F' data field of the delay correction device; wherein, the Y is a natural number greater than 1, and the Y is obtained by multiplying a and L to an integer , T'=L*T;

Y Ts are adjusted in the F data field, and the F is reduced to the F' by N-level decimation.

In a first possible implementation manner of the third aspect, the step of reducing the F to the F' through multi-stage decimation specifically includes: according to the decimation multiple M of the delay correction device, through N-stage decimation The decimation value reduces the F to the F'; wherein, L=M ^N ; the rth-level decimation value in the N-level decimation value is to reduce the first data rate Fr before the _rth -level decimation value to the second data rate Fr ' after the _r -th decimation; the said 1≤r≤N

In a fourth aspect, a time delay correction method is provided, which is applied to a time delay correction apparatus, and the time delay correction apparatus is applied to a wireless base station system, including:

Acquire the fractional delay and delay correction parameters between the feedback channel and the transmission channel of the wireless base station system; wherein, the delay correction parameters include the decimation multiple M of the delay correction device; the fractional delay is a times the data interface period T' of the time delay correction device, 0<a<1;

Based on the extraction level of each delay correction module, the fractional delay is decomposed into N delays to be corrected; wherein, the extraction levels of the N delay correction modules are set to N levels, and each time delay The delay correction module corresponds to one extraction level, and each level of the delay correction module corresponds to one copy of the delay to be corrected; the N copies of the delay to be corrected are a ₁ , a ₂ , ..., a _N ; the rth level of delay correction The delay to be corrected corresponding to the module is a _r times T';r∈(1,2,...,N);

According to the decimation multiple M of the delay correction module, it is determined that when each level of delay correction module meets the delay requirement of _{ar times T', it needs to be in the data rate Fr data} domain of the level of delay correction module The number Y _r of the adjusted clock periods Tr _; wherein, the _Fr and Tr are the data rate and data period before the decimation of the _r - _th stage delay correction module respectively, and satisfy Tr =1/ _Fr ; Described Y _r is obtained by multiplying a _r and the decimation multiple M and rounding up; The data period after the decimation by the _r -th stage delay correction module is Tr ', _Tr '=M*Tr _;

According to Y _r , T′ corresponding to the delay correction module at the r-th stage corresponding to the delay to be corrected a _r times is adjusted in sequence.

In a first possible implementation manner of the fourth aspect, according to Y _r , sequentially adjusting T' of the delay to be corrected a _r times corresponding to the delay correction module at the r-th stage specifically includes:

Selecting any delay to be corrected, and determining that the extraction level of the delay correction module corresponding to any correction delay is the rth level, the number Y _r of Tr that needs to be adjusted in the _Fr data domain _;

Adjust Y _r Tr in the _Fr data domain _;

reducing the _Fr to the _Fr '; wherein the said 1≤r≤N;

Wherein, the any delay to be corrected is one of the N delays to be corrected, and the N delays to be corrected constitute the fractional delay.

In combination with the fourth aspect or the first possible implementation manner of the fourth aspect, in the second possible implementation manner of the fourth aspect, according to the decimation multiple M of the delay correction module, determine the time of each stage. When the delay correction module meets the delay requirement of _ar times _{T', the number Y r of} clock cycles Tr that needs to be adjusted under the data rate _Fr data domain of the delay correction module of this stage specifically includes:

According to the decimation multiple M of the delay correction module and equations (1) and (2), it is determined that when the delay correction module of each stage meets the delay requirement of _ar times T', it needs to be The number Y _r of clock cycles Tr adjusted in the data rate _Fr data domain of the delay correction module _;

a*T'=(Y ₁ *M ⁰ +Y ₂ *M ¹ +...+Y _r *M ^r-1 +...+Y _N *M ^N-1 )*T (1)

a*T' ⁼ MN*T(2).

The delay correction method and device provided by the embodiments of the present invention adjust a corresponding number of data periods in the high-speed data domain according to the fractional delay between the feedback channel and the transmission channel and the oversampling multiple L of the delay correction device, that is, When the delay correction device reduces the rate of high-multiple data through multi-stage decimation, it can meet the delay requirement of fractional delay in the low-multiple digital domain, so as to achieve high analog signal from the input to the output of the delay correction device. Accurate time delay adjustment function and low implementation cost can reduce cost and improve the performance of wireless base station system.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a time delay correction apparatus provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of another time delay correction apparatus provided by an embodiment of the present invention;

3 is a sequence diagram provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another time delay correction apparatus provided by an embodiment of the present invention;

5 is a schematic structural diagram of still another time delay correction apparatus provided by an embodiment of the present invention;

FIG. 6 is a schematic block diagram of the r-th stage delay correction module in a delay correction device provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of another time delay correction apparatus provided by an embodiment of the present invention;

FIG. 8 is another sequence diagram provided by an embodiment of the present invention;

FIG. 9 is a schematic flowchart of a time delay correction method provided by an embodiment of the present invention;

FIG. 10 is a schematic flowchart of another time delay correction method provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a delay correction device, which is applied to a wireless base station system. In this embodiment, after the high-speed data sampling is completed, the delay correction device adjusts a corresponding number of data in a high-speed digital domain period, and then reduce the data rate through multi-stage decimation, thereby compensating for the loop fractional delay between the transmission channel and the feedback channel in the wireless base station system. Specifically, as shown in FIG. 1 , the delay correction device 1 includes: a data acquisition module 11 , a data processing module 12 connected to the data acquisition module 11 , and X serial delay modules connected to the data processing module 12 13. The selection module 14 connected with each of the serially connected delay modules 13 in the X serially connected delay modules 13 and the N serially connected extraction modules 15 connected with the selection module 14, the above-mentioned N extraction modules 15 Each drawing module 15 in the corresponding drawing level, wherein:

The data acquisition module 11 is used for acquiring the fractional delay and delay correction parameters between the feedback channel and the transmission channel of the wireless base station system.

The above-mentioned fractional delay is equal to a times the data interface period T' of the delay correction device. Specifically, the value range of the above-mentioned parameter a is a decimal less than 1, that is, 0<a<1. The above-mentioned time delay correction parameter includes the oversampling multiple L of the time delay correction device. The oversampling factor L is a multiple of the difference between the sampling clock frequency F of the delay correction device and the data interface rate F' of the delay correction device, that is, L=F/F'. In addition, because the delay correction device in the embodiment of the present invention reduces the sampling clock frequency F of the high speed to the data interface rate F' of the low speed through N decimation modules 15, and the delay correction device in the delay correction device The decimation multiple of each decimation module 15 is ^M , and the oversampling multiple between the sampling clock frequency F and the data interface rate F' is L, therefore, L=MN can be obtained.

Exemplarily, taking an oversampling analog-to-digital converter (Analog-to-Digital Converter, ADC for short) system as an example, under normal circumstances, the data rate (that is, the sampling clock frequency F) after the ADC sampling is completed is usually very high, generally within 3 ~6GHz (Gigahertz) and above, this kind of high-speed data is usually unable to be received correctly by Field-Programmable GateArray (FPGA) or Application Specific Integrated Circuits (ASIC). At the same time, for the application of the oversampling system, all these data are not necessarily used, as long as the bandwidth of the useful signal can be covered. Therefore, nowadays, the high-speed data is usually reduced by multi-stage decimation, so that the reduced data interface The rate F' is generally 100MHz to 500MHz (megahertz), which is convenient for the receiving end to receive. In this process, the sampling clock frequency F is reduced to a multiple of the data interface rate F' to be reduced, that is, the oversampling multiple L.

The data processing module 12 is configured to determine, according to the oversampling multiple L and the fractional delay, that Y sampling clock periods T need to be adjusted in the data domain of the sampling clock frequency F of the delay correction device to satisfy the on-time delay correction of the fractional delay The delay requirement in the data field of the device's data interface rate F'.

Wherein, the above-mentioned number Y of sampling clock periods T is a natural number greater than 1. In an embodiment, the number Y of the sampling clock periods T is equal to the multiplication of a and L to an integer. Specifically, the derivation process of the formula Y=a*L is as follows.

First of all, it can be seen from the above process that the time delay correction device adjusts Y sampling clock cycles T in the data domain of the sampling clock frequency F, so as to compensate the data interface cycle T' with a fractional time delay a times, that is, a*T'=Y* T (formula 1); secondly, since the oversampling multiple L is the multiple of the difference between the sampling clock frequency F of the delay correction device and the data interface rate F' of the delay correction device, that is, L=F/F', therefore, The relationship between the sampling clock period T corresponding to the sampling clock frequency F and the data interface rate F' and the data interface period T' and the oversampling multiple L can be T'=L*T (Formula 2); finally, according to F=1/ T, F'=1/T', and formula 1 and formula 2, Y=a*L is calculated, and then based on the above formula Y=a*L, it is directly derived that the delay correction device can be rounded by multiplying a and L , to obtain the Y value, so that the delay correction device can compensate the fractional delay a*T' in the F' data domain after adjusting Y sampling clock periods T in the sampling clock frequency F data domain.

The selection module 14 , after connecting Y delay modules 13 in series among the X delay modules 13 according to Y, each delay module is then connected to the selection module 14 .

Specifically, when the above-mentioned selection module 14 includes X-1 selection switches K, the selection module can open the Y+1 selection switch of the selection module 14 to indicate that there are Y series-connected switches in front of the selection module 14 Delay module 13 .

Y serial delay modules 13 are used to adjust Y T in the F data domain; each delay module 13 adjusts one sampling clock period T; X is greater than or equal to Y.

N series-connected decimation modules 15 are used to reduce the sampling clock frequency F to the data interface rate F' through N-level decimation.

Specifically, since each stage of decimation modules can reduce the data interface rate F' by M times, the delay correction device can reduce the data interface rate F' by L times through N series-connected decimation modules 15, which is about to sample The clock frequency F drops to the data interface rate F'.

Specifically, the specific function realization process of each of the above-mentioned N extraction modules 15 is described by taking the r-th level extraction module in the above-mentioned N extraction modules as an example, wherein the r-th extraction module 15 The level extraction module 15 is any level extraction module among the N extraction modules.

Specifically, the rth level extraction module 15 is used to reduce the first data rate Fr before the _rth level extraction module 15 extracts the value to the second data rate Fr ' after the _rth extraction module 15 extracts the value. abovementioned abovementioned 1≤r≤N.

Exemplarily, when r=1, it can be considered that the delay correction apparatus performs the first decimation on F, therefore, F ₁ =F. Correspondingly, when r=N, it can be considered that the delay correction device is performing the last stage of decimation to obtain F'. Therefore, according to L=M ^N , then

Specifically, a delay correction device with an oversampling multiple L of 4 is taken as an example here. As shown in FIG. 2 , the delay correction device includes two extraction modules 11 with double extraction values and three delay units 12 . and a selection module 13, namely L=4, M=2, N=2, X=3.

Fig. 3 is a time delay diagram corresponding to the time delay correction device shown in Fig. 2. Referring to the experimental diagram shown in Fig. 3, in an oversampling system, when the time delay correction device shown in Fig. 2 does not perform time delay correction, only When the rate of high-speed original data is reduced by 2-level decimation, there is a total data delay of 3 T in the entire oversampling system. The total data delay of these 3 T is the delay that the oversampling system itself needs to appear. , the fractional delay between the feedback channel and the transmit channel that occurs in the system cannot be compensated.

At this time, if the fractional delay that needs to be compensated for the sampled raw data is 0.75T', first, the delay correction device decomposes 0.75T' into 3*0.25T'=3 according to the formula T'=4*T *T, so as to obtain Y=3; secondly, according to Y=3, the time delay correction device selects the switch of the selection module 13 in the time delay correction device at the position of switch K3, at this time, the entire oversampling system has 6 T total data delay. The total data delay of the 6 Ts includes the 3 T delays of the system itself as described above and the 3 T delays adjusted by the present invention. The delay correction device adjusts 3 Ts in the F data domain, thereby completing the delay requirement of 0.75T' in the F' data domain, and the delay diagram of the process of compensating the fractional delay by the delay correction device is shown in Figure 3 shown.

The embodiment of the present invention provides a delay correction device, the delay correction device determines the time delay correction device sampling clock frequency F in the data domain according to the fractional delay between the feedback channel and the transmission channel and the oversampling multiple of the delay correction device The number of sampling clock cycles T of the delay correction device to be adjusted is Y, which can meet the delay requirement of the fractional delay in the F' data domain, so that Y T in the F data domain are adjusted, and F is reduced to F' through multi-stage extraction, thereby realizing the high-precision delay adjustment function of the analog signal from the input to the output of the delay correction device, and the realization cost is low, which can reduce the cost and improve the performance of the wireless base station system. .

The unit division of the delay correction apparatus in the embodiment of the present invention is an exemplary description, and in practice, there may be multiple unit division methods to constitute the time delay correction apparatus in the embodiment of the present invention. The time delay correction apparatus according to the embodiment of the present invention may be integrated on the base station side or the mobility management entity (Moblity Management Entity, MME for short) side in the wireless base station system. The functions of each module unit in the delay correction apparatus according to the embodiment of the present invention may be implemented by a base station controller in the base station or a controller in the MME.

An embodiment of the present invention also provides a time delay correction device, which is applied to a wireless base station system. In this embodiment, the delay correction device is used to correct the loop fractional time between the transmission channel and the feedback channel in the overall wireless base station system. The delay is distributed to all levels of delay correction modules for implementation, thereby compensating for the loop fractional delay. As shown in FIG. 4 , the time delay correction device 2 includes: a data acquisition module 21, a data processing module 22 connected to the data acquisition module 21, and N time delay correction modules 23 connected to the data processing module 22; the above-mentioned Each delay correction module 23 in the N delay correction modules 23 corresponds to a drawing level, wherein:

The data acquisition module 21 is used for acquiring the fractional delay and delay correction parameters between the feedback channel and the transmission channel of the wireless base station system.

The above-mentioned time delay correction parameter includes the oversampling multiple L of the time-delay correction device; the above-mentioned fractional time delay is equal to a times the data interface period T' of the time-delay correction device. Specifically, the above-mentioned parameter a is taken as The range of values is a decimal less than 1, that is, 0<a<1. The above-mentioned time delay correction parameter includes the oversampling multiple L of the time delay correction device. The oversampling factor L is a multiple of the difference between the sampling clock frequency F of the delay correction device and the data interface rate F' of the delay correction device, that is, L=F/F'. In addition, since the delay correction device in the embodiment of the present invention reduces the sampling clock frequency F of the high speed to the data interface rate F' of the low speed through the decimation module in the N-stage delay correction module 23, and the The decimation multiple of each delay correction module 23 in the delay correction device is ^M , and the oversampling multiple between the sampling clock frequency F and the data interface rate F' is L, therefore, L=MN can be obtained.

The data processing module 22 is configured to decompose the fractional delay into N parts of delays to be corrected based on the decimation level of each delay correction module 23 .

Wherein, each stage of the delay correction module 23 in the N-level delay correction module 23 in the embodiment of the present invention corresponds to a copy of the delay to be corrected respectively. Specifically, the above N delays to be corrected are respectively a ₁ T', a ₂ T', ..., a _N T', a=∑(a ₁ +a ₂ +...+a _r +...+a _N ); the delay to be corrected corresponding to the r-th stage delay correction module is a _r times T'; r∈(1,2,...,N). In addition, when the time delay correction device decomposes the fractional time delay into N parts of the time delay to be corrected, since the time delays that can be compensated by the time delay correction module 23 of each stage are different, the time delay correction device can Different sampling multiples are configured with different delay allocation strategies to decompose the fractional delay. The specific delay allocation strategy can be the mapping relationship between the extraction level of the delay correction module 23 and the delay that can be compensated. , it can also be a delay allocation formula, for example, a*T'=(Y ₁ *M ⁰ +Y ₂ *M ¹ +...+Y _r *M ^r-1 +...+Y _N *M ^N-1 )*T.

Exemplarily, when the data processing module 22 decomposes the fractional delay, it usually distributes the delay adjustment requirements of the fractional delay to each delay correction module according to the extraction level corresponding to the delay correction modules at all levels. Therefore, the data processing module decomposes the above-mentioned fractional delay into N pieces of delays to be corrected, that is, in order to obtain the delay adjustment requirements for each piece of delays to be corrected subsequently. However, it should be noted that when the fractional delay is decomposed, since the delay to be corrected that can be corrected by each level of delay correction module has a certain range, so that the final decomposed N pieces of band correction delay, There will be multiple groups of situations, you can choose one of them to deal with.

The data processing module 22 is also used to determine, according to the multiplier M of the time delay correction module 23, that when the time delay correction module 23 of each stage meets the time delay requirement of _ar times T', the time delay correction module of this level needs to be The number Y _r of clock cycles Tr adjusted in the data domain of the data rate _Fr of ₂₃ .

Wherein, the above-mentioned _Fr and Tr are respectively the data rate and data period before the decimation of the _r -th stage delay correction module 23, and satisfy Tr=1/ _{Fr ;} the above-mentioned _Yr is obtained by _ar and decimation The value multiple M is multiplied and rounded up; and the data period after the r-th stage delay correction module 23 draws the value is T _r ',

_Tr '=M* _Tr . It should be noted that the above-mentioned F _r , _{Tr , and Y r correspond} to these three values with different extraction levels of the delay correction module. Specifically, each delay correction module 23 has Its corresponding F _r , _{Tr ', Y r .}

Illustratively, taking the number Y _r of Tr that needs to be adjusted in the _Fr data domain by the _r -th stage delay correction module 23 as an example, specifically, the derivation process of the formula Y _r = _ar *M is as follows.

First, it can be seen from the above process that the _{r-th stage delay correction module 23 adjusts Y r sampling} clock cycles T in the data domain of the pre-decimation data rate Fr, so as to compensate the post-decimation data of _ar times the time delay to be corrected The clock cycle Tr ' corresponding to the rate _Fr ', namely a _r * _Tr '=Y* _Tr (formula 3); secondly, since the decimation multiple M is the value before the decimation of the _rth stage delay correction module 23 The multiple of the difference between the data rate Fr and the decimation data rate _Fr ' of the _r -th stage delay correction module 23, namely

M= _Fr / _Fr ', therefore, the relationship between the clock period Tr corresponding to the data rate _Fr and the data rate _Fr ', the clock period _Tr ' and the _decimation multiple M can be _Tr '=M*T _r (formula 4); finally, according to formula 3 and formula 4, Y _r = _ar *M can be calculated, therefore, based on the above formula Y _r = _ar *M, it can be directly deduced that the delay correction device passes a _r and M are multiplied and rounded up to obtain the value of Y _r , so that the _r -th stage delay correction module 23 adjusts Y _r clock cycles Tr in the data domain of the data rate Fr, and then the value of Y _r can be adjusted in the data domain of _Fr ' The delay requirement of the to-be-corrected delay a _r *T' allocated in compensation.

The N time delay correction modules 23 are used to sequentially adjust T' of the time delay to be corrected a _r times corresponding to the time delay correction module of the rth stage according to Y _r .

Specifically, the above-mentioned N delay correction modules 23 are formed in series from low to high according to the extraction level of the delay correction module 23. When the above-mentioned fractional delay is input to the N serially connected delay correction modules After being in the module, each stage delay correction module 23 sequentially compensates the fractional delay according to the size of the delay to be corrected that can be compensated.

According to the delay correction device provided by the embodiment of the present invention, the delay correction device distributes the fractional delay to the delay correction modules of all levels according to the fractional delay between the feedback channel and the transmission channel and the decimation multiple of the delay correction device. Compensation correction is performed, and the number of _{T r that needs to be adjusted in the Fr data domain Y r is determined when} the delay correction module of each stage meets the delay requirement of the corresponding delay to be corrected in the Fr ' data domain. , so that the corresponding delays to be corrected are adjusted from low to high according to the extraction level of the N delay correction modules, so as to realize the high-precision delay adjustment function of the analog signal from the input to the output of the delay correction device. At the same time, because each level of delay correction module adjusts different data periods in different data domains, and the higher the extraction level, the longer one data period corresponds to the delay, which greatly reduces the number of delay units, making The implementation cost of the solution is low, the cost can be reduced, and the performance of the wireless base station system can be improved at the same time.

Optionally, as shown in FIG. 5 , each delay correction module 23 in the above-mentioned N delay correction modules 23 includes a delay unit 231, a selection unit 232 and a value extraction unit 233,

Here, the rth level delay correction module 23 in the N delay correction modules 23 is taken as an example to illustrate the specific function realization process of each delay correction module 23 in the above N delay correction modules 23. The rth delay correction module 23 The stage delay correction module 23 is any stage delay correction module 23 among the above N delay correction modules 23 .

Specifically, as shown in FIG. 6 , the delay unit 231 in the r-th delay correction module 23 includes X delay subunits 231a, where X is a natural number greater than 1 and X is greater than Yr, and the X delay subunits 231a are connected in series After that, each delay subunit is connected with the above-mentioned selection unit 232, and the above-mentioned selection unit 232 is connected with the value extraction unit 233, wherein:

The selection unit 233 in the r-th stage delay correction module 23 in the N delay correction modules 23 is configured to connect Y _r delay subunits 231a in series in the _r -th stage delay correction module 23 according to Y r, Each time delay subunit is further connected to the selection unit 233 in the above-mentioned r-th delay correction module 23 .

Exemplarily, when the selection unit 233 includes X-1 selection switches K, the above-mentioned selection unit 233 may turn on the Y _r th selection switch to indicate that Y _r time delays connected in series are connected in front of the selection unit 232 . unit 231a.

Y _r serial delay subunits 231a are used to adjust Y _r Tr in the _Fr data domain _; each delay subunit adjusts 1 _Tr .

The decimation unit 233 in the r-th stage delay correction module 23 is used to reduce _Fr to _Fr '; wherein, 1≤r≤N, where the above-mentioned r-th stage delay correction module is any level of delay correction module 23 in the N delay correction modules 23 .

Exemplarily, when r=1, it can be considered that the delay correction apparatus performs the first decimation on F, therefore, F ₁ =F. Correspondingly, when r=N, it can be considered that the delay correction device is performing the last stage of decimation to obtain F'. Therefore, according to L=M ^N , then

In addition, when the data processing module 22 determines that each stage of the delay correction module 23 meets the time delay requirement of _{ar times T', the clock period that needs to be adjusted in the data rate Fr data} domain of the stage delay correction module 23 The number Y _r of T _r can be determined according to the following equations (1) and (2).

a*T'=(Y ₁ *M ⁰ +Y ₂ *M ¹ +...+Y _r *M ^r-1 +...+Y _N *M ^N-1 )*T Equation (1)

a*T' ⁼ MN*T equation (2).

It should be noted that the specific module architecture of the r-th stage delay correction module 23 described in FIG. 5 and FIG. 6 is also applicable to other delay correction modules 23 of the delay correction device provided in this embodiment. The r-level delay correction module 23 is only one of the delay correction modules 23 in the delay correction apparatus provided in this embodiment.

Exemplarily, if a delay correction device with an oversampling multiple L of 4 is taken as an example, as shown in FIG. 7 , the delay correction device includes two levels of delay correction modules 21 , and each level of delay correction module 21 includes A decimation module 233 with twice the decimation value, a delay unit 231 and a selection unit 232 are composed, that is, L=4, M=2, N=2, X=2.

Fig. 8 is a time delay diagram corresponding to the time delay correction device shown in Fig. 7. Referring to Fig. 8, in an oversampling system, when the time delay correction device shown in Fig. 7 does not perform time delay correction, When the rate of high-speed raw data is reduced, the entire oversampling system will have a total data delay of 3 T, and the total data delay of these 3 T is the delay that the oversampling system itself needs to appear, and cannot be compensated. The fractional delay between the feedback channel and the transmit channel that occurs in the system.

When the fractional delay to be compensated for the sampled raw data is 0.75T', first the delay correction device is based on the formula 0.75*T'=(Y ₁ 2 ⁰ +Y ₂ 2 ¹ )*T, and the formula 0.75*T '=3*T, Y ₁ =1, Y ₂ =1 are calculated; secondly, according to Y ₁ =1, Y ₂ =1, the time delay correction device The ON selection is on switch W1, so that the delay correction module 23 adjusts one time period T1 (T1=T) in the F1 (F1=F) data field. Referring to the delay diagram shown in FIG. 8, it can be seen that at this time the original The data is delayed by 1 T. After another T1 delay, the data is extracted by the extraction unit in the first-level delay correction module. After twice the sampling value of the sampling unit in the first-stage delay correction module, the period of the data becomes T1'(T1'=T2=2T). Then, the switch of the selection unit 232 of the second-stage delay correction module 23 is selected on the switch W1, so that the delay correction module 21 is adjusted in the data field of F2 (F2=1/T2=1/2T=F/2) One time period T2 (T2=2T), referring to the time delay diagram shown in FIG. 8 , it can be known that the original data at this time is equivalent to a delay of 2 T in the F data domain. After another T2 delay, the data is extracted by the extraction unit in the second-level delay correction module. After the extraction unit 233 in the second stage delay correction module 23 doubles the extraction value, the period of the data becomes T2'(T2'=T'=2T*2=4T). In this way, there is a total data delay of 6 T in the entire oversampling system. The total data delay of the 6 Ts includes the 3 T delays of the system itself as described above and the 3 T delays adjusted by the present invention. Through the delay correction device, the delay requirement of 0.75T' is realized by delaying by 3 T.

According to the delay correction device provided by the embodiment of the present invention, the delay correction device determines, according to the fractional delay between the feedback channel and the transmission channel and the decimation multiple of the delay correction device, whether each stage of the delay correction module satisfies the corresponding needs to be corrected. When the delay is required by the delay in the _Fr ' data domain, the number Y _r of _Tr needs to be adjusted in the _Fr data domain, so as to adjust the extraction level of the N delay correction modules in order from low to high The corresponding time delay to be corrected is adjusted, so as to realize the high-precision time delay adjustment function of the analog signal from the input to the output of the time delay correction device, and the realization cost is low, which can reduce the cost.

The unit division of the delay correction apparatus in the embodiment of the present invention is an exemplary description, and in practice, there may be multiple unit division methods to constitute the time delay correction apparatus in the embodiment of the present invention. The delay correction apparatus in the embodiment of the present invention may be integrated on the base station side or the mobility management entity side in the wireless base station system. The functions of each module unit in the delay correction apparatus according to the embodiment of the present invention may be implemented by a base station controller in the base station or a controller in the MME.

The embodiment of the present invention also provides a time delay correction method, which applies the time delay correction device 1 described in the corresponding embodiments of FIGS. 1 and 2. Specifically, the time delay correction device 1 is specifically applied to a wireless base station system, Wherein, as shown in FIG. 9 , the time delay correction method specifically includes the following steps:

301. The delay correction device acquires the fractional delay and delay correction parameters between the feedback channel and the transmission channel of the wireless base station system.

The above-mentioned time delay correction parameter includes the oversampling multiple L of the time-delay correction device; the above-mentioned fractional time delay is equal to a times the data interface period T' of the time-delay correction device. Specifically, the above-mentioned parameter a is taken as The range of values is a decimal less than 1, that is, 0<a<1. The above-mentioned time delay correction parameter includes the oversampling multiple L of the time delay correction device. The oversampling factor L is a multiple of the difference between the sampling clock frequency F of the delay correction device and the data interface rate F' of the delay correction device, that is, L=F/F'. In addition, because the time delay correction device in the embodiment of the present invention reduces the sampling clock frequency F of the high speed to the data interface rate F' of the low speed through N decimation modules, and each time delay correction device in the delay correction device The decimation multiple of each decimation module is ^M , and the oversampling multiple between the sampling clock frequency F and the data interface rate F' is L, therefore, L=MN can be obtained.

302. The delay correction device determines, according to the oversampling multiple L and the fractional delay, that the sampling clock periods T of Y delay correction devices need to be adjusted in the data domain of the sampling clock frequency F of the delay correction device, so that the fractional delay can be satisfied. The delay requirement in the data interface rate F' data field of the delay correction device.

Wherein, the above-mentioned number Y of sampling clock periods T is a natural number greater than 1. In an embodiment, the number Y of the sampling clock periods T is equal to the multiplication of a and L to an integer. Specifically, the derivation process of the formula Y=a*L is as follows.

First of all, it can be seen from the above process that the time delay correction device adjusts Y sampling clock cycles T in the data domain of the sampling clock frequency F, so as to compensate the data interface cycle T' with a fractional time delay a times, that is, a*T'=Y* T (formula 1); secondly, since the oversampling multiple L is the multiple of the difference between the sampling clock frequency F of the delay correction device and the data interface rate F' of the delay correction device, that is, L=F/F', therefore, The relationship between the sampling clock period T corresponding to the sampling clock frequency F and the data interface rate F' and the data interface period T' and the oversampling multiple L can be T'=L*T (formula 2); finally, according to formula 1 With formula 2, Y=a*L is calculated, and then based on the above formula Y=a*L, it is directly derived that the delay correction device can multiply a and L to obtain the Y value, and then make the delay correction device in After the sampling clock frequency F is adjusted by Y sampling clock periods T in the data domain, the fractional delay a*T' can be compensated in the F' data domain.

303. The time delay correction device adjusts Y T in the F data domain, and reduces F to F' through multi-stage extraction.

Optionally, in step 303, reducing F to F' through multi-level pumping specifically includes the following content:

303a. The time delay correction device reduces F to F' through N-level draw values according to the draw value multiple M of the time delay correction device.

Wherein, L=MN; the r-th level of extraction in the above-mentioned ^N -level extraction is to reduce the first data rate Fr before the _r -th level of extraction to the second data rate Fr after the _r -th level of extraction ';abovementioned abovementioned 1≤r≤N.

Exemplarily, when r=1, it can be considered that the delay correction apparatus performs the first decimation on F, therefore, F ₁ =F. Correspondingly, when r=N, it can be considered that the delay correction device is performing the last stage of decimation to obtain F'. Therefore, according to L=M ^N , then

In the time delay correction method provided by the embodiment of the present invention, the time delay that needs to be adjusted in the data domain of the sampling clock frequency F of the time delay correction device is determined according to the fractional time delay between the feedback channel and the transmission channel and the oversampling multiple of the delay correction device The number of sampling clock cycles T of the correction device is Y, which can meet the delay requirement of the fractional delay in the F' data domain, so that Y T in the F data domain is adjusted, and the multi-stage extraction is performed. F is reduced to F', thereby realizing the high-precision delay adjustment function of the analog signal from the input to the output of the delay correction device, and the realization cost is low, which can reduce the cost and improve the performance of the wireless base station system.

An embodiment of the present invention further provides a time delay correction method, which applies the time delay correction device 2 described in the corresponding embodiments of FIGS. 4 to 7 . Specifically, the time delay correction device 2 is specifically applied to a wireless base station system, Wherein, as shown in FIG. 10 , the time delay correction method specifically includes the following steps:

401. The delay correction apparatus acquires the fractional delay and delay correction parameters between the feedback channel and the transmission channel of the wireless base station system.

The above-mentioned time delay correction parameter includes the oversampling multiple L of the time-delay correction device; the above-mentioned fractional time delay is equal to a times the data interface period T' of the time-delay correction device. Specifically, the above-mentioned parameter a is taken as The range of values is a decimal less than 1, that is, 0<a<1. The above-mentioned time delay correction parameter includes the oversampling multiple L of the time delay correction device. The oversampling factor L is a multiple of the difference between the sampling clock frequency F of the delay correction device and the data interface rate F' of the delay correction device, that is, L=F/F'. In addition, because the time delay correction device in the embodiment of the present invention reduces the sampling clock frequency F of the high speed to the data interface rate F' of the low speed through N-level decimation, and the time delay correction device decimates the value at each stage The decimation multiple is ^M , and the oversampling multiple between the sampling clock frequency F and the data interface rate F' is L, therefore, L=MN can be obtained.

402. The delay correction device decomposes the fractional delay into N delays to be corrected based on the delay allocation strategy and the extraction level of each delay correction module.

Wherein, each stage of the delay correction module in the embodiment of the present invention corresponds to one copy of the time delay to be corrected; and the above N copies of the time delay to be corrected are respectively a ₁ T', a ₂ T', ..., a _N T', a=∑(a ₁ +a ₂ +...+a _r +...+a _N ), for example, the delay to be corrected corresponding to the r-th stage delay correction module is T' whose time delay is a _r times; r∈( 1,2,...,N). In addition, when the time delay correction device decomposes the fractional time delay into N parts of the time delay to be corrected, since the time delays that can be compensated by the time delay correction module 23 of each stage are different, the time delay correction device can Different sampling multiples are configured with different delay allocation strategies for fractional delay decomposition. The specific delay allocation strategy can be the mapping relationship between the extraction level of the delay correction module and the delay that can be compensated. It can also be a delay allocation formula, for example, a*T'=(Y ₁ *M ⁰ +Y ₂ *M ¹ +...+Y _r *M ^r-1 +...+Y _N *M ^N-1 ) *T.

Exemplarily, when the delay correction device decomposes the fractional delay, it usually distributes the delay adjustment requirements of the fractional delay to each delay correction module according to the decimation level corresponding to the delay correction modules at all levels. Therefore, the delay correction device decomposes the above-mentioned fractional delay into N pieces of delays to be corrected, that is, in order to obtain the delay adjustment requirements for each piece of delays to be corrected subsequently. However, it should be noted that when the fractional delay is decomposed, since the delay to be corrected that can be corrected by each stage of the delay correction module has a certain range, so that the N parts of the band finally decomposed by the delay correction device When correcting the delay, there will be multiple groups of situations, and you can choose one of them for processing.

403. The delay correction device determines, according to the extraction multiple M of the delay correction module, that when the delay correction module of each stage meets the delay requirement of _ar times T', the data rate F of the delay correction module at this level is required. The number Y _r of clock cycles _Tr adjusted in the _r data domain.

Optionally, step 403 specifically includes the following content:

403a. The time delay correction device determines, according to the decimation multiple M of the time delay correction module and equations (1) and (2), when each level of time delay correction module meets the time delay requirement of _ar times T', it needs to be The number Y _r of clock cycles Tr adjusted under the data rate _Fr data domain of the delay correction module of this _stage . Wherein, the above equation (1) is:

a*T'=(Y ₁ *M ⁰ +Y ₂ *M ¹ +...+Y _r *M ^r-1 +...+Y _N *M ^N-1 )*T;

Equation (2) is: a*T' ⁼ MN*T.

Wherein, the above-mentioned _Fr and Tr are respectively the data rate and data period before the decimation of the _r -th stage delay correction module 23, and satisfy Tr=1/ _{Fr ;} the above-mentioned _Yr is obtained by _ar and decimation The value multiple M is multiplied and rounded up; and the data period after the r-th stage delay correction module 23 draws the value is T _r ',

_Tr '=M* _Tr . It should be noted that the above-mentioned F _r , _{Tr ' and Y r correspond} to these three values with different extraction levels of the delay correction module. Specifically, each delay correction module 23 has a There are corresponding F _r , _{Tr ', Y r .}

Illustratively, taking the number Y _r of Tr that needs to be adjusted in the _Fr data domain by the _r -th stage delay correction module 23 as an example, specifically, the derivation process of the formula Y _r = _ar *M is as follows.

First, it can be seen from the above process that the _{r-th stage delay correction module 23 adjusts Y r sampling} clock cycles T in the data domain of the pre-decimation data rate Fr, so as to compensate the post-decimation data of _ar times the time delay to be corrected The clock cycle Tr ' corresponding to the rate _Fr ', namely a _r * _Tr '=Y* _Tr (formula 3); secondly, since the decimation multiple M is the value before the decimation of the _rth stage delay correction module 23 The multiple of the difference between the data rate Fr and the decimated data rate _Fr ' of the _r -th stage delay correction module 23, that is, M= _Fr / _Fr ', therefore, the data rate _Fr and the data rate _Fr 'The relationship between the corresponding clock cycle _Tr and clock cycle _Tr ' and the multiplier M can be _Tr '=M* _Tr (Formula 4); finally, Y can be calculated according to Formula 3 and Formula 4 _r = _ar *M, therefore, based on the above formula Y _r = _ar *M, it can be directly deduced that the time delay correction device multiplies a _r and M to an integer to obtain the value of Y _r , and then makes the r-th stage time After the delay correction module 23 adjusts the clock period Tr corresponding to the data rate _Fr ' after Y _r decimations in the data field of the data rate _Fr before the _decimation , it can compensate the allocated time to be corrected in the data field of _Fr '. Delay requirement for delay a _r *T'.

404. According to Y _r , the time delay correction device sequentially adjusts T′ of the time delay to be corrected a _r times corresponding to the time delay correction module of the rth stage.

Optionally, step 404 specifically includes the following process:

404a. The delay correction device selects any delay to be corrected, and determines that when the extraction level of the delay correction module corresponding to any corrected delay is the _rth level, the number of Tr that needs to be adjusted in the _Fr data domain _Yr .

404b. The time delay correction device adjusts Y _{r Tr} in the _Fr data domain.

404c. The time delay correction device reduces _Fr to _Fr '.

Among them, the above abovementioned Exemplarily, when r=1, it can be considered that the delay correction apparatus performs the first decimation on F, therefore, F ₁ =F. Correspondingly, when r=N, it can be considered that the delay correction device is performing the last stage of decimation to obtain F'. Therefore, according to L=M ^N , then It should be noted that any of the above-mentioned delays to be corrected is one of the N pieces of delays to be corrected, and the above-mentioned N pieces of delays to be corrected constitute the fractional delay mentioned in the embodiment of the present invention.

In the time delay correction method provided by the embodiment of the present invention, according to the fractional time delay between the feedback channel and the transmission channel and the decimation multiple of the time delay correction device, the fractional time delay is distributed to all levels of time delay correction modules for compensation and correction, and the correction is performed. When the delay correction module of each stage meets the delay requirements of the corresponding delay to be corrected in the _Fr ' data domain, the number Y _r of _Tr needs to be adjusted in the _Fr data domain, so that according to N The extraction level of the delay correction module adjusts the corresponding delay to be corrected in order from low to high, so as to realize the high-precision delay adjustment function of the analog signal from the input to the output of the delay correction device. The delay correction module adjusts different data cycles in different data domains, and the higher the extraction level, the longer the corresponding delay data cycle, thus greatly reducing the number of delay units and making the solution less expensive. , which can reduce the cost and improve the performance of the wireless base station system at the same time.

Those skilled in the art can clearly understand that, for the convenience and conciseness of the description, only the division of the above-mentioned functional modules is used for illustration. In practical applications, the above-mentioned functions can be allocated to different functional modules as required. The internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For the specific working process of the system, apparatus and unit described above, reference may be made to the corresponding process in the foregoing method embodiments, and details are not described herein again.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be Incorporation may either be integrated into another system, or some features may be omitted, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.

The integrated unit, if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM, Read-Only Memory), Random Access Memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes .

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: The technical solutions described in the embodiments are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions in the embodiments of the present application.

Claims (10)

1. A delay correction apparatus applied to a wireless base station system, the apparatus comprising: the system comprises a data acquisition module, a data processing module, X time delay modules, a selection module and N serial decimation modules, wherein each decimation module in the N decimation modules corresponds to a decimation level, the selection module is connected with the N serial decimation modules, X is a natural number greater than 1, and N is a natural number, wherein:

the data acquisition module is used for acquiring decimal time delay and time delay correction parameters between a feedback channel and a transmitting channel of the wireless base station system; wherein the delay correction parameter comprises an oversampling multiple L of the delay correction device; the decimal time delay is a times of the data interface period T' of the time delay correction device, 0< a < 1;

the data processing module is configured to determine, according to the oversampling multiple L and the fractional delay, that Y sampling clock periods T of the delay correction device need to be adjusted in a sampling clock frequency F data domain of the delay correction device, so as to meet a delay requirement of the fractional delay in a data interface rate F' data domain of the delay correction device; wherein Y is a natural number greater than 1, Y is equal to or less than X, Y is obtained by rounding the product of a and L, T ═ L ═ T, F ═ 1/T';

the selection module is used for serially connecting Y time delay modules to the selection module in the X time delay modules according to the Y;

the Y serial time delay modules are used for adjusting Y T in the F data domain; each delay module adjusts a T;

the N serial decimation modules are used for reducing the F to the F' through N levels of decimation.

2. The apparatus of claim 1, wherein the decimation module has a decimation multiple of M, and wherein L is M^N：

An r-th-level decimation module of the N decimation modules, configured to decimate a first data rate F before the r-th-level decimation module_rSecond data rate F after dropping to the r-th decimation module decimation_r'; the above-mentionedThe above-mentioned

The above-mentioned r-level decimation module is any one of the N decimation modules.

3. A delay correction apparatus applied to a wireless base station system, the apparatus comprising: the system comprises a data acquisition module, a data processing module and N time delay correction modules; each of the N delay correction modules corresponds to a decimation level, where N is a natural number greater than 1, where:

the data acquisition module is used for acquiring decimal time delay and time delay correction parameters between a feedback channel and a transmitting channel of the wireless base station system; the time delay correction parameters comprise a decimation multiple M and an oversampling multiple L of the time delay correction device; the decimal time delay is a times of the data interface period T' of the time delay correction device, 0< a < 1;

the data processing module is used for decomposing the fractional time delay into N times of time delay to be corrected based on the decimation level of each time delay correction module; each stage of time delay correction module corresponds to one time delay to be corrected; the N time delays to be corrected are a₁，a₂，……，a_N(ii) a The time delay to be corrected corresponding to the r-th stage time delay correction module is a_rMultiple T'; r ∈ (1, 2...., N);

the data processing module is also used for determining that the delay correction module of each stage meets a according to the decimation multiple M of the delay correction module_rThe data rate F of the delay correction module at the stage is required when the delay requirement of T' is multiplied_rAdjusted clock period T under data field_rNumber of (2)_r(ii) a Wherein, F is_rAnd T_rThe data rate and the data period before the sampling of the r-stage time delay correction module are respectively and satisfy T_r＝1/F_r(ii) a Said Y is_rIs obtained by a_rThe integer is obtained by multiplying the decimation factor M; the data period after the gamma-stage time delay correction module is subjected to value extraction is T_r'，T_r'＝M*T_r；

The N time delay correction modules are used for correcting the time delay according to Y_rSequentially adjusting the time delay a to be corrected corresponding to the r-th stage time delay correction module_rMultiple of T'.

4. The apparatus of claim 3, wherein each delay correction module comprises a decimation unit, a delay unit and a selection unit, the delay unit comprises X delay sub-units, X is a natural number greater than 1 and X is greater than Y_rThe selection module is connected with the decimation unit;

a selection unit in the r-th stage delay correction module of the N delay correction modules, configured to select the Y-th stage delay correction module according to the Y-th stage delay correction module_rY is converted in the r-stage time delay correction module_rThe delay subunits are connected in series to the selection unit in the r-th stage delay correction module;

said Y is_rA series of delay sub-units for delaying at F_rAdjusting Y in data field_rA T_r(ii) a Adjusting 1T per delay subunit_r；

A decimation unit in the r-th stage delay correction module for dividing the F_rDown to said F_r'; wherein, theThe above-mentioned

The r-th stage delay correction module is any one stage of the N delay correction modules.

5. The apparatus of claim 3 or 4, wherein the data processing module determines the data rate F required for the delay correction module at each stage according to equation (1) and equation (2)_rAdjusted clock period T under data field_rNumber of (2)_r；

a*T'＝(Y₁*M⁰+Y₂*M¹+……+Y_r*M^r-1+……+Y_N*M^N-1)*T (1)

a*T'＝M^N*T (2)。

6. A delay correction method is applied to a delay correction device, and the delay correction device is applied to a wireless base station system, and is characterized by comprising the following steps:

acquiring decimal time delay and time delay correction parameters between a feedback channel and a transmitting channel of the wireless base station system; the time delay correction parameters comprise a decimation multiple M and an oversampling multiple L of the time delay correction device; the decimal time delay is a times of the data interface period T' of the time delay correction device, 0< a < 1;

according to the oversampling multiple L and the fractional delay, determining that the sampling clock period T of Y delay correction devices needs to be adjusted in a sampling clock frequency F data domain of the delay correction device, so that the delay requirement of the fractional delay in a data interface rate F' data domain of the delay correction device can be met; wherein Y is a natural number greater than 1, and is obtained by rounding up a by multiplying L, and T' ═ L × T;

and adjusting Y T in the F data field, and reducing the F to the F' through multi-stage decimation.

7. The method of claim 6, wherein the reducing the F to the F' by multi-level decimation comprises: according to the decimation multiple M of the time delay correction device, reducing the F to the F' through N-level decimation; wherein, L ═ M^N(ii) a The nth decimation value of the N decimation values is a first data rate F before the nth decimation value_rSecond data rate F after dropping to the r-th level snapshot_r'; the above-mentionedThe above-mentioned

8. A delay correction method is applied to a delay correction device, and the delay correction device is applied to a wireless base station system, and is characterized by comprising the following steps:

acquiring decimal time delay and time delay correction parameters between a feedback channel and a transmitting channel of the wireless base station system; wherein the delay correction parameter comprises a decimation multiple M of the delay correction device; the decimal time delay is a times of the data interface period T' of the time delay correction device, 0< a < 1;

decomposing the fractional time delay into N times of time delay to be corrected based on the decimation level of each time delay correction module; the sampling level of the N time delay correction modules is set to be N levels, each time delay correction module corresponds to one sampling level, and each time delay correction module corresponds to one time delay to be corrected; the N time delays to be corrected are a₁，a₂，……，a_N(ii) a The time delay to be corrected corresponding to the r-th stage time delay correction module is a_rMultiple T'; r ∈ (1, 2...., N);

according to the decimation multiple M of the time delay correction module, determining that the time delay correction module of each stage meets a_rThe data rate F of the delay correction module at the stage is required when the delay requirement of T' is multiplied_rAdjusted clock period T under data field_rNumber of (2)_r(ii) a Wherein, F is_rAnd T_rThe data rate and the data period before the sampling of the r-stage time delay correction module are respectively and satisfy T_r＝1/F_r(ii) a Said Y is_rIs obtained by a_rThe integer is obtained by multiplying the decimation factor M; the data period after the gamma-stage time delay correction module is subjected to value extraction is T_r'，T_r'＝M*T_r；

According to Y_rSequentially adjusting the time delay a to be corrected corresponding to the r-th stage time delay correction module_rMultiple of T'.

9. The method of claim 8, wherein the function is Y_rSequentially adjusting the time delay a to be corrected corresponding to the r-th stage time delay correction module_rThe multiples of T' include in particular:

selecting any time delay to be corrected, and determining that the sampling value grade of the time delay correction module corresponding to any time delay to be corrected is the r-th grade when F_rIn the data fieldT to be adjusted_rNumber of (2)_r；

At F_rAdjusting Y in data field_rA T_r；

Subjecting said F to_rDown to said F_r'; wherein, theThe above-mentioned

And any delay to be corrected is one of the N delays to be corrected, and the N delays to be corrected form the decimal delay.

10. The method according to claim 8 or 9, wherein the determining that the delay correction module at each stage satisfies a is performed according to the decimation multiple M of the delay correction module_rThe data rate F of the delay correction module at the stage is required when the delay requirement of T' is multiplied_rAdjusted clock period T under data field_rNumber of (2)_rThe method specifically comprises the following steps:

determining that the delay correction module of each stage meets a according to the decimation multiple M of the delay correction module and equations (1) and (2)_rThe data rate F of the delay correction module at the stage is required when the delay requirement of T' is multiplied_rAdjusted clock period T under data field_rNumber of (2)_r；

a*T'＝(Y₁*M⁰+Y₂*M¹+……+Y_r*M^r-1+……+Y_N*M^N-1)*T (1)

a*T'＝M^N*T (2)。