CN105453450A

CN105453450A - Time delay correction method and device

Info

Publication number: CN105453450A
Application number: CN201480008803.XA
Authority: CN
Inventors: 时子恒; 张雪坤; 黄宝平; 朱尔霓
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2014-05-23
Filing date: 2014-05-23
Publication date: 2016-03-30
Anticipated expiration: 2034-05-23
Also published as: CN105453450B; WO2015176313A1

Abstract

The present invention relates to the field of signal processing. A time delay correction method and device, being capable of realizing the function of high precision time delay adjustment of an analog signal from an input to an output of the time delay correction device. The specific implementation method comprises: a time delay correction device obtains a fractional delay between a feedback channel and a transmission channel of a wireless base station system, and a time delay correction parameter; the time delay correction parameter comprises an oversampling multiple L; the fractional delay is a times the data interface period T', 0<a<1; according to the oversampling multiple L and the fractional delay, determining that in a sampling clock frequency F data field of the time delay correction device, sampling Y clock periods of T of the time delay correction device need to be adjusted to meet the delay requirement of the fractional delay in a data interface rate F' data field of the time delay correction device; Y is a natural number greater than 1, and is obtained by rounding a times L, and T'=L*T; adjusting Y clock periods of T in the F data field, and reducing F to F' through multilevel value extraction. The present invention is applied to time delay correction.

Description

Time delay correction method and device

A kind of time delay adjustment method and device technical field

The present invention relates to field of signal processing, more particularly to a kind of time delay adjustment method and device.

Background technology

In wireless base system, in order to obtain preferable transmission signal, it is generally necessary to which digital pre-calibration is sampled, modeled and carried out to the analog signal exported to antenna feedback, but with the development increasingly of wireless communication technology, wireless base system requires more and more higher for versatility, the flexibility ratio of hardware device, so that wireless base system is also all the more sensitive for the loop decimal time delay between the transmission channel and feedback channel in system, so as to have influence on digital pre-distortion（Digital Pre-Distortion, abbreviation DPD) limit correction ability, and then also cause wireless base system can not get the higher transmission signal of quality.

Specifically, ideally, certain transmission signal is on transmission channel after the A t times, the feedback signal of the transmission signal is sampled in feedback channel, but because wireless base system is for the limited of time delay Adjustment precision, less than 1 minimum step time delay can not be corrected, so the time delay that wireless base system is delayed to the signal and the signal of original transmitted that sample when compensate for integer often also in the presence of a decimal can not be compensated, the time delay of this decimal is loop decimal time delay.And wireless base system can not just complete signal alignment, cause the inaccurate of mathematical modeling, obtained correction result is also inaccurate, so as to have influence on DPD limit correction ability when time delay is less than 1 minimum step.Now, although there is segmentation scheme decimal time delay can be tried one's best in theory compensation, but the precision compensated in actual applications is not high, not only realizes that cost is too big, can also reduce the performance of wireless base system.

The content of the invention

Embodiments of the invention provide a kind of time delay adjustment method and device, can realize the high-precision time-delay adjustment function that is input to output of the analog signal from time delay adjustment device.

To reach above-mentioned purpose, embodiments of the invention are adopted the following technical scheme that： First aspect is there is provided a kind of time delay adjustment device, and applied to wireless base system, the device includes：Value module is taken out in data acquisition module, data processing module, X time delay module, selecting module and N number of series connection, N number of value rank of taking out for taking out value module is set to N grades, each to take out value module correspondence one-level, the selecting module is connected wherein with the value module of taking out of N number of series connection：

The data acquisition module, decimal time delay between feedback channel and transmission channel and time delay correction parameter for obtaining the wireless base system；Wherein, the time delay adjustment parameter includes the over-sampling multiple L of the time delay adjustment device;The decimal time delay is the data-interface cycle Γ ' of a times of the time delay adjustment device, 0<a<l;

The data processing module, for according to the over-sampling multiple L and the decimal time delay, it is determined that needing to adjust the sampling clock cycle T of the Y time delay adjustment devices in the sample clock frequency F data fields of the time delay adjustment device, to meet the delay requirement in the data-interface speed data domain of the time delay adjustment device of the decimal time delay；Wherein, the Y is the natural number more than 1, and the Y is to be multiplied to round acquisition with L by a, Τ '=Σ * Τ, F=l/T, '=l/7';

The selecting module, the Y time delay module connected is connected to the selecting module according to the Y in the X time delay module；

The time delay module of the Y series connection, for adjusting Y T in the F data fields;Each time delay module adjusts a T;X is more than or equal to Y;

Value module is taken out in N number of series connection, for by N grades take out value the F is dropped to it is described.

In the first possible implementation of first aspect, the value multiple of taking out for taking out value module is M, L=M^N

N number of r grades taken out in value module take out value module, take out the first data rate before value and drop to the r and take out value module for taking out value module by described r grades and take out described in the second data rate after value=~ ^, described '=_ ^,<r<N\

r^r M^r- ^{1 r} M^r

Wherein, it is that N number of any level taken out in value module takes out value module that above-mentioned r grades, which are taken out value module,.

Second aspect is there is provided a kind of time delay adjustment device, applied to wireless base system, institute Stating device includes：Data acquisition module, data processing module, N time delay adjustment module；Each time delay adjustment module correspondence one in N number of time delay adjustment module takes out value rank, wherein：

The data acquisition module, decimal time delay between feedback channel and transmission channel and time delay correction parameter for obtaining the wireless base system；Wherein, the time delay adjustment parameter takes out value multiple M and over-sampling multiple L including the time delay adjustment device;The decimal time delay is the data-interface cycle Γ ' of a times of the time delay adjustment device, 0<a< l ;

The data processing module, for taking out value rank based on each time delay adjustment module, N parts of time delays to be corrected are decomposed into by the decimal time delay；Wherein, every grade of a time delay to be corrected of time delay adjustment module correspondence；The N parts of time delay to be corrected be^αι' …… ' ^αThe_rThe corresponding time delay to be corrected of level time delay adjustment module is^αTou Τ '; re⁽L,²... ..., N)

The data processing module, it is additionally operable to take out value multiple M according to the time delay adjustment module, determine every grade of time delay adjustment module in satisfaction " during ^ times of Γ ' delay requirement; need the number ^ of clock cycle adjusted under the data-rate data domain of this grade of time delay adjustment module wherein; the data rate taken out before value of described and respectively r grades time delay adjustment modules and data cycle, and satisfaction^{= 1 / F}It is described to be obtained by being multiplied to round with taking out value multiple M；The data cycle after r grades of time delay adjustment modules take out value is

N number of time delay adjustment module, for basis, is sequentially adjusted in the corresponding time delay to be corrected of r grades of time delay adjustment modules^αTou Τ '.

In the first possible implementation of second aspect, each time delay adjustment module includes taking out value cell, time delay elements and selecting unit, the time delay elements include X time delay subelement, X is more than Yr for the natural number and X more than 1, and the selecting module is connected with the value cell of taking out；

The selecting unit in r grades of time delay adjustment modules in the N time delay adjustment module, for connecting a time delay subelement being serially connected in the r grades of time delay adjustment modules according to described；

The time delay subelement of described series connection, for adjusting individual in data field⁷The each time delay subelements of ^ adjust 1⁷^

Value cell is taken out in the r grades of time delay adjustment modules, for dropping to institute by described State F ';Wherein, the F=~ ^ ~, the F'=, l≤r≤N;

r^r M^r-^{1 r} M^r

Wherein, r grades of above-mentioned time delay adjustment modules are any level time delay adjustment module in N number of time delay adjustment module.

With reference to the first possible implementation of second aspect or second aspect, in second of possible implementation of second aspect, the data processing module is according to equation（And equation 1)（2) number for the clock cycle that needs are adjusted under the data-rate data domain of time delay adjustment modules at different levels is determined；

a*r'=(Y₁*M°+Y₂*M¹ + +Y_r*M^r^+ +Ύ_Ν*Μ^Ν'^ι)*Τ (1) α*Τ'^Μ^Ν*Τ (2).The third aspect is there is provided a kind of time delay adjustment method, applied to time delay adjustment device, and the time delay adjustment device is applied to wireless base system, including：

Obtain the decimal time delay and time delay correction parameter between the feedback channel and transmission channel of the wireless base system；Wherein, the time delay adjustment parameter takes out value multiple Μ and over-sampling multiple L including the time delay adjustment device;The decimal time delay is a times of data-interface cycle, 0<a<l;

According to the over-sampling multiple L and the decimal time delay, it is determined that needing to adjust the sampling clock cycle T of the Y time delay adjustment devices in the sample clock frequency F data fields of the time delay adjustment device, the delay requirement in the data-interface speed data domain of the time delay adjustment device of the decimal time delay just can be met；Wherein, the Y is the natural number more than 1, and the Y is to be multiplied to round acquisition with L by a, T'=L*T

Y T is adjusted in the F data fields, and value is taken out by the F by N grades and drops to the F'.

It is described value is taken out by the F by multistage to drop to described specifically include in the first possible implementation of the third aspect：Value multiple M is taken out according to the time delay adjustment device, by N grades take out value by the F drop to it is described wherein, L=M^NIt is that the first data rate for taking out r grades before value drops to described in described r grades the second data rates taken out after value=~ ^, the F '=~ ^ that N grades of r grades taken out in value, which take out value ,≤r≤N.

M^r M^r

Fourth aspect is there is provided a kind of time delay adjustment method, applied to time delay adjustment device, and the time delay adjustment device is applied to wireless base system, including： Obtain the decimal time delay and time delay correction parameter between the feedback channel and transmission channel of the wireless base system；Wherein, the time delay adjustment parameter takes out value multiple M including the time delay adjustment device;The decimal time delay is the data-interface cycle Γ ' of a times of the time delay adjustment device, 0<a<l;

Value rank is taken out based on each time delay adjustment module, the decimal time delay is decomposed into N parts of time delays to be corrected；Wherein, the value rank of taking out of N number of time delay adjustment module is set to N grades, and each time delay adjustment module correspondence one takes out value rank, every grade of a time delay to be corrected of time delay adjustment module correspondence；The N parts of time delay to be corrected is " 1, "²... ... '；The_rThe corresponding time delay to be corrected of level time delay adjustment module is⁶W Tou's^re(1,²... ...,^N);

Value multiple M is taken out according to the time delay adjustment module, every grade of time delay adjustment module is determined when meeting Tou delay requirement, it is necessary to the number of the clock cycle adjusted under the data-rate data domain of this grade of time delay adjustment module；Wherein, it is described and⁷^ is respectively the data rate taken out before value and the data cycle of r grades of time delay adjustment modules, and meets^{7 1}/ ；It is described to be obtained by being multiplied to round with taking out value multiple M；The data cycle after r grades of time delay adjustment modules take out value is ^,^Tr' = M*T_r.

According to being sequentially adjusted in the corresponding time delay to be corrected of r grades of time delay adjustment modules⁶W Tou T'.

In the first possible implementation of fourth aspect, the basis is sequentially adjusted in the corresponding time delay to be corrected of r grades of time delay adjustment modules⁶W Tou's specifically includes：

Select any time delay to be corrected, determine the corresponding time delay adjustment module of any correction time delay take out value rank for r grades when, the number adjusted is needed in data field；Adjusted in data field individual

r F _F' ₌J_ by it is described drop to it is described '；Wherein, it is described^r M^r-¹, it is described^r M^r , l≤r≤N_;

Wherein, a copy of it of Yanzhong when any time delay to be corrected is described Ν parts to be corrected, the Ν parts of time delay to be corrected constitutes the decimal time delay.

With reference to the first possible implementation of fourth aspect or fourth aspect, in second of possible implementation of fourth aspect, it is described that value multiple Μ is taken out according to the time delay adjustment module, determine every grade of time delay adjustment module satisfaction " ^ times of Γ ' delay requirement when, it is necessary to The number of the clock cycle adjusted under the data-rate data domain of this grade of time delay adjustment module is specifically included：

Value multiple M and equation are taken out according to the time delay adjustment module（And equation 1)（2) every grade of time delay adjustment module is determined when meeting A times of delay requirement, it is necessary to the clock cycle 7 adjusted under the data-rate data domain of this grade of time delay adjustment module；Number 1;

a* T ' =( *Μ。 +Υ₂ +…… +Y_r *M^r- ¹ +…… +Υ_Ν*Μ^Ν'^ι) * Τ ( 1 ) α * Τ' = Μ^Ν* Τ (2).The time delay adjustment method and device that embodiments of the invention are provided, according to the decimal time delay between feedback channel and transmission channel and the over-sampling multiple L of time delay means for correcting, the corresponding number data cycle is adjusted in high speed data field, can time delay adjustment device by it is multistage take out value by the rate reductions of high power data when, meet delay requirement of the decimal time delay in the numeric field of low power number, so as to realize the high-precision time-delay adjustment function that is input to output of the analog signal from time delay adjustment device, and realize that cost is relatively low, cost can be reduced, the performance of wireless base system is improved simultaneously.

Brief description of the drawings

In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, the required accompanying drawing used in embodiment or description of the prior art will be briefly described below, apparently, drawings in the following description are only some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.

A kind of structural representation for time delay adjustment device that Fig. 1 provides for embodiments of the invention；

The structural representation for another time delay adjustment device that Fig. 2 provides for embodiments of the invention；

A kind of timing diagram that Fig. 3 provides for embodiments of the invention；

The structural representation for another time delay adjustment device that Fig. 4 provides for embodiments of the invention；

The structural representation for another time delay adjustment device that Fig. 5 provides for embodiments of the invention； The module diagram of r grades of time delay adjustment modules in a kind of time delay adjustment device that Fig. 6 provides for embodiments of the invention；

The structural representation for another time delay adjustment device that Fig. 7 provides for embodiments of the invention；

Another timing diagram that Fig. 8 provides for embodiments of the invention；

A kind of schematic flow sheet for time delay adjustment method that Fig. 9 provides for embodiments of the invention；

The schematic flow sheet for another time delay adjustment method that Figure 10 provides for embodiments of the invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made belongs to the scope of protection of the invention.

Embodiments of the invention provide a kind of time delay adjustment device, applied to wireless base system, in the present embodiment, time delay adjustment device is after high speed output is completed, by adjusting the corresponding number data cycle in the numeric field of high speed, then taking out value by multistage reduces data rate, so as to compensate for the loop decimal time delay in wireless base system between transmission channel and feedback channel.Specifically, as shown in Fig. 1, the time delay adjustment device 1 includes：Value module 15 is taken out in data acquisition module 11, data processing module 12, X time delay module 13, selecting module 14 and N number of series connection, above-mentioned N number of each correspondence of value module 15 one of taking out taken out in value module 15 takes out value rank, and the selecting module 14 is connected with above-mentioned N number of value module 15 of taking out being serially connected, wherein：

Data acquisition module 11, for obtaining decimal time delay and time delay correction parameter between the feedback channel of wireless base system and transmission channel.

Wherein, above-mentioned decimal time delay is equal to a times of the data-interface cycle of the time delay adjustment device, specifically, above-mentioned parameter a span is the decimal less than 1, i.e. 0<a< l.Above-mentioned time delay adjustment parameter includes the over-sampling multiple L of the time delay adjustment device. Over-sampling multiple L is the data-interface speed F of sample clock frequency F and the time delay adjustment device of time delay adjustment device, between the multiple that differs, i.e. ,=F/F '.In addition, because the time delay adjustment device in the embodiment of the present invention is to take out the data-interface speed F that value module 15 drops to the sample clock frequency F of high speed low power speed by N number of,, and each value multiple of taking out for taking out value module 15 in the time delay adjustment device is M, sample clock frequency F and data-interface speed F, between over-sampling multiple be L, therefore, it can draw=M

Exemplary, with oversampling analog-to-digital converter（Analog-to-Digital Converter, abbreviation ADC) exemplified by system, the data rate after the completion of ADC samplings under normal circumstances（That is sample clock frequency F) it is generally very high, typically in 3 6GHz (Gigahertzs）More than, this high-speed data for field-programmable gate array it is bad ' J (Field-Programmable Gate Array, abbreviation FPGA) or application specific integrated circuit (Application Specific Integrated Circuits, abbreviation ASIC) for be typically what is be unable to properly receive, these data not necessarily will all be used for being applied simultaneously for over-sampling system, as long as the bandwidth of useful signal can be covered, therefore, typically high-speed data is taken out value to reduce speed by multistage now, so that reduction after data-interface speed F '-as 100MHz 500MHz (megahertz）, it is easy to receiving terminal to receive, sample clock frequency F is reduced to data-interface speed F, the multiple to be reduced, i.e. over-sampling multiple L during this.

Data processing module 12, for according to over-sampling multiple L and decimal time delay, it is determined that needing to adjust Y sampling clock cycle T in the sample clock frequency F data fields of time delay adjustment device, to meet the delay requirement in the data-interface speed data domain of time delay adjustment device of decimal time delay.

Wherein, above-mentioned sampling clock cycle T number Y is the natural number more than 1.In one embodiment, sampling clock cycle T number Y is multiplied equal to a with L rounds, specifically, " * derivation is as follows for formula=.

First, by said process, time delay adjustment device adjusts Y sampling clock cycle T under sample clock frequency F data fields, just can compensate for the data-interface cycle T of a times of decimal time delay, i.e., " V=" (formula 1);Secondly as over-sampling multiple L is the data-interface speed F of sample clock frequency F and the time delay adjustment device of time delay adjustment device, between the multiple that differs, i.e. ,=F/F ', therefore, sample clock frequency F and data-interface speed F, Corresponding sampling clock cycle T and data-interface cycle T ' the relation between over-sampling multiple L can be Γ '=￡ * Γ (formula 2);Finally, according to F=l/T, F'=IT, and formula 1 and formula 2, calculate=" * and then based on above-mentioned formula=" * directly releases time delay adjustment device and can be multiplied by a with L and rounded, so as to obtain Y value, and then time delay adjustment device is adjusted after Y sampling clock cycle T in sample clock frequency F data fields, decimal time delay a* just can be compensated in data field.

Selecting module 14, selecting module 14 is connected to according to Y in X time delay module 13 by Y time delay module 13.

Specifically, when above-mentioned selecting module 14 includes X-1 selecting switch K, the selecting module can be by opening the Y+1 selecting switch of the selecting module 14, to show to be connected with the Y time delay module 13 connected before selecting module 14.

The time delay module 13 of Y series connection, for adjusting Y T in F data fields;Each time delay module 13 adjusts a sampling clock cycle T;X is more than or equal to $.

Value module 15 is taken out in N number of series connection, and data-interface speed F' is dropped to for taking out value by sample clock frequency F by N grades.

Specifically, taking out value module and can reduce M times of data-interface speed F due to every grade, therefore, time delay adjustment device just can taking out value module 15 and reduce L times of data-interface speed F by N series connection, i.e., sample clock frequency F is dropped into data-interface speed F'.

Specifically, so that above-mentioned N number of r grades taken out in value module take out value module as an example, to illustrate the concrete function implementation process of above-mentioned N number of each value of taking out module 15 taken out in value module 15, wherein, it is that N number of any level taken out in value module takes out value module that this r grades, which are taken out value module 15,.

Specifically, r grades are taken out value module 15 and are used to taking out value module 15 by r grades to take out the first data rate before value and drop to r and take out value module 15 and take out the second data rate ^ after value.

r F _F,=_

Above-mentioned^r M^r-¹, it is above-mentioned^r M^r , l≤r≤N。

Exemplary, as r=l, it is believed that time delay adjustment device carries out taking out value for the first time to F, therefore,^{F =F}.Accordingly, as r=N, it is believed that time delay adjustment device exists

_F , ₌ H _F, carry out afterbody and take out and is worth to, therefore, according to=^^, then^N M^N L 。

Specifically, such as scheming so that over-sampling multiple L is 4 time delay adjustment device as an example here Shown in 2, constituted in the time delay adjustment device comprising 22 times take out value module 11,3 time delay elements 12 and the selecting modules 13 for taking out value, i.e. L=4, M=2, N=2, X=3.

Fig. 3 is the corresponding time delay figure of time delay adjustment device shown in Fig. 2, lab diagram shown in reference picture 3, in over-sampling system, when the time delay adjustment device as shown in Fig. 2 is without time delay adjustment, when only taking out value by the rate reduction of the initial data of high speed by 2 grades, the data that whole over-sampling system has 3 T are always delayed, the always delay of this 3 T data is the delay that the over-sampling system inherently needs to occur, it is impossible to the decimal delay between the feedback channel and transmission channel appeared in compensation system.

Now, if the initial data sampled needs the decimal time delay compensated to be 0.75 7¹' when, first, the time delay adjustment device is according to formula r'=⁴* 7 0.75 is decomposed into³*0.²⁵Γ' = ³* Γ, so as to obtain Υ=3;Secondly, the time delay adjustment device is according to Υ=3, and by the switch selection of the selecting module 13 in the time delay adjustment device in switch Κ 3 position, now, the data that whole over-sampling system has 6 Τ are always delayed.The always delay of this 6 Τ data includes 3 Τ of system as described above delay in itself and 3 Τ adjusted by the present invention delay.3 Τ are adjusted under F data fields by the time delay adjustment device, so as to complete 0.75 7 " delay requirement in data field, and the delay figure of time delay adjustment device compensation decimal time delay process is as shown in Figure 3.

The time delay adjustment device that embodiments of the invention are provided, the time delay adjustment device is according to the decimal time delay and the over-sampling multiple of time delay means for correcting between feedback channel and transmission channel, it is determined that needing the sampling clock cycle Τ of the time delay adjustment device of adjustment number to be Υ in time delay adjustment device sample clock frequency F data fields, just the delay requirement in data field of the decimal time delay can be met, so as to adjust Υ Τ in F data fields, and value is taken out by multistage F is dropped to and then realize the high-precision time-delay adjustment function that is input to output of the analog signal from time delay adjustment device, and realize that cost is relatively low, cost can be reduced, the performance of wireless base system is improved simultaneously.

The embodiment of the present invention, to the dividing elements of time delay adjustment device, is a kind of exemplary explanation, can have the division methods of a variety of units in practice to constitute the time delay adjustment device of the embodiment of the present invention.The time delay adjustment device of the embodiment of the present invention can be integrated in base station side or mobile management entity (moblity management entity, abbreviation in wireless base system MME) side.The function of each modular unit in the time delay adjustment device of the embodiment of the present invention can be realized by the controller in the base station controller or MME in base station.

Embodiments of the invention additionally provide a kind of time delay adjustment device, applied to wireless base system, in the present embodiment, time delay adjustment device is realized by the way that the loop decimal time delay in total wireless base system between transmission channel and feedback channel is distributed in time delay adjustment modules at different levels, so as to compensate for the loop decimal time delay.As shown in Fig. 4, the time delay adjustment device 2 includes：Data acquisition module 21, data processing module 22, N number of time delay adjustment module 23;Each time delay adjustment module 23 correspondence one in above-mentioned N number of time delay adjustment module 23 takes out value rank, wherein：

Data acquisition module 21, for obtaining decimal time delay and time delay correction parameter between the feedback channel of wireless base system and transmission channel.

Wherein, above-mentioned time delay adjustment parameter includes the over-sampling multiple L of the time delay adjustment device;Above-mentioned decimal time delay is equal to the data-interface cycle of the time delay adjustment device_aTimes, specifically, above-mentioned parameter a span is the decimal less than 1, i.e. 0<a<l.Above-mentioned time delay adjustment parameter includes the over-sampling multiple L of the time delay adjustment device.Over-sampling multiple L is the data-interface speed F of sample clock frequency F and the time delay adjustment device of time delay adjustment device, between the multiple that differs, i.e. F/F'.In addition, because the time delay adjustment device in the embodiment of the present invention is by the data-interface speed F that value module drops to the sample clock frequency F of high speed low power speed that takes out in N grades of time delay adjustment modules 23,, and the value multiple of taking out of each time delay adjustment module 23 in the time delay adjustment device is M, sample clock frequency F and data-interface speed F, between over-sampling multiple be L, therefore, it can draw=MW.

Data processing module 22, for taking out value rank based on each time delay adjustment module 23, N parts of time delays to be corrected are decomposed into by decimal time delay.

Wherein, every grade of time delay adjustment module 23 in the N level time delay adjustments module 23 in embodiments of the invention corresponds to a time delay to be corrected respectively.Specifically, above-mentioned N parts time delay to be corrected is respectively^αι^Γ',^Τ, ... ...,^αΝ^Τ' , α = (α_{ι +} α_{2 +}→α +→α_Ν _rThe corresponding time delay to be corrected of level time delay adjustment module is^αTou Τ ';^re(1,²'…… ' ^N).In addition, time delay adjustment device by decimal time delay be decomposed into N parts it is to be corrected when be delayed, the time delay that can be compensated by every grade of time delay adjustment module 23 is different, therefore time delay adjustment device can be according to its value of taking out The difference of multiple, over-sampling multiple, configure different time delay allocation strategies to carry out the decomposition of decimal time delay for it, the specific time delay allocation strategy can take out value rank and the mapping relations for the time delay that can be compensated for time delay adjustment module 23, it can also be time delay distribution formula, such as, a* T '=(* Μ. +Υ₂ +…… +Y_r *M^r- ¹ +…… *MW- ¹ ) * Γ。

Exemplary, data processing module 22 to decimal time delay when decomposing, typically value rank is taken out according to time delay adjustment modules at different levels are corresponding, the time delay adjustment requirement of the decimal time delay is distributed into each time delay adjustment module to disperse to be realized, therefore, above-mentioned decimal time delay is decomposed into Ν parts of time delays to be corrected by data processing module, i.e., in order to which the time delay for subsequently obtaining every part of time delay to be corrected adjusts demand.However, it is desirable to explanation, when being decomposed to decimal time delay, by the time delay to be corrected that every grade of time delay adjustment module can be corrected has certain scope, therefore so that the Ν parts band correction time delay finally decomposed, multigroup situation occurs, can optionally one handled.

Data processing module 22, it is additionally operable to take out value multiple Μ according to time delay adjustment module 23, determine every grade of time delay adjustment module 23 when meeting Γ ' again delay requirement, it is necessary to the number of the clock cycle adjusted under the data-rate data domain of this grade of time delay adjustment module 23

Y_rWherein, the data rate taken out before value of above-mentioned and respectively r grade time delay adjustment modules 23 and data cycle, and satisfaction^{7 1/ F}It is above-mentioned to be obtained by being multiplied to round with taking out value multiple M；And the data cycle after r grades of time delay adjustment modules 23 take out value is ^,^{= Μ}It should be noted that above-mentioned,^ΤBe it is also different with its different these three corresponding value for taking out value rank of time delay adjustment module, specifically, each time delay adjustment module 23 have corresponding thereto,

It is exemplary, so that r grades of time delay adjustment modules 23 need the number that is adjusted under data field as an example, specifically, formula^{= α}^^ΜDerivation it is as follows.

First, pass through said process, r grades of time delay adjustment modules 23 lower whole sampling clock cycle T taking out data-rate data domain before value, and just can compensate for time delay to be corrected times takes out data rate after value ' corresponding clock cycle, i.e., '=(formula 3);Secondly as take out the data rate taken out value after of the data rate taken out before value with r grades of time delay adjustment modules 23 that value multiple M is r grades of time delay adjustment modules 23 ' between times that differs Number, i.e. bis-/^ of ^, therefore, data rate clock cycle corresponding with data rate and clock cycle and the relation taken out between value multiple M can be^{= M}^ (formula 4);Finally, just it can be calculated according to formula 3 and formula 4^{= α Μ}, therefore, based on above-mentioned formula y_r=* M, can directly it release, time delay adjustment device is rounded by being multiplied with M, so as to acquisition value, and then r grade time delay adjustment modules 23 were adjusted in data-rate data domain after the individual clock cycle, just can in data field the time delay * Γ ' to be corrected of compensation distribution delay requirement.

Ν time delay adjustment module 23, for basis, is sequentially adjusted in the corresponding time delay to be corrected of r grades of time delay adjustment modules^αTou Τ '.

Specifically, Ν above-mentioned time delay adjustment module 23 is to take out value rank according to time delay adjustment module 23, it is sequentially connected in series from low to high, after above-mentioned decimal time delay is input in the Ν time delay adjustment modules being serially connected, every grade of time delay adjustment module 23 is compensated successively according to the size of its time delay to be corrected that can be compensated to the decimal time delay.

The time delay adjustment device that embodiments of the invention are provided, the time delay adjustment device takes out value multiple according to the decimal time delay between feedback channel and transmission channel and time delay means for correcting, the decimal time delay is distributed to time delay adjustment modules at different levels and compensates correction, timing determines every grade of time delay adjustment module when meeting delay requirement of the corresponding time delay to be corrected under ' data field, the number adjusted under data field is needed to take out value rank according to Ν time delay adjustment module, corresponding time delay to be corrected is adjusted successively from low to high, so as to realize the high-precision time-delay adjustment function that is input to output of the analog signal from time delay adjustment device, simultaneously because every grade of time delay adjustment module is that the different data cycles are adjusted under different pieces of information domain, and it is longer to take out 1 data cycle of the higher correspondence delay of value rank, so as to greatly reducing the number of time delay elements, so that scheme realizes that cost is relatively low, cost can be reduced, the performance of wireless base system is improved simultaneously.

Optionally, as shown in Figure 5, each time delay adjustment module 23 in Ν above-mentioned time delay adjustment module 23 includes time delay elements 23 1, selecting unit 232 and takes out value cell 233, here by taking r grades of time delay adjustment modules 23 in Ν time delay adjustment module 23 as an example, to illustrate the concrete function implementation process of each time delay adjustment module 23 in above-mentioned N number of time delay adjustment module 23, the r grades of time delay adjustment modules 23 are above-mentioned N number of time delay adjustment mould Any level time delay adjustment module 23 in block 23.

Specifically, as shown in fig. 6, the time delay elements 231 in r grades of time delay adjustment modules 23 include X time delay subelement 231a, X is more than Yr for the natural number and X more than 1, above-mentioned selecting module 232 is connected with taking out value cell 233, wherein：

The selecting unit 233 in r grades of time delay adjustment modules 23 in N number of time delay adjustment module 23, for according to the time delay subelement 231 that connection is serially connected in r grades of time delay adjustment modules 23.

Exemplary, when the selecting unit 233 includes X-1 selecting switch K, above-mentioned selecting unit 233 can be by opening the selecting switch, to show to be connected with a time delay subelement 231a being serially connected before selecting unit 232.

The time delay subelement 231a of individual series connection, for adjusting individual 7 in data field；;Each time delay subelement adjusts 1⁷^

Value cell 233 is taken out in r grades of time delay adjustment modules 23, for that will drop to^F r F _p , ₌ J_

Wherein,^r M-¹ , ^r M^r, l≤r≤N, wherein, above-mentioned_rLevel time delay adjustment module is any level time delay adjustment module 23 in N number of time delay adjustment module 23.

_F , ₌ H _F, carry out afterbody and take out and is worth to, therefore, according to=MW, then N M^N L 。

In addition, data processing module 22 it is determined that every grade of time delay adjustment module 23 meet times T' delay requirement when, it is necessary to the clock cycle adjusted under the data-rate data domain of this grade of time delay adjustment module 23⁷, can be according to following equatioies during ^ number（And equation 1)（2) determine.

a*r'=(Y₁*M。+Y₂*M¹+…… +Y_r*M^r— …… +Υ_Ν*Μ^Ν'^ι) * Τ equatioies (1) α * Τ=Μ^Ν* Τ equatioies（2).It should be noted that, the specific module frame of r grades of time delay adjustment modules 23 described by Fig. 5, Fig. 6, other time delay adjustment modules 23 of the time delay adjustment device provided in the present embodiment are equally applicable, one of time delay adjustment module 23 in the r grades of time delay adjustment modules 23 time delay adjustment device that simply the present embodiment is provided here.

Exemplary, if here so that over-sampling multiple L is 4 time delay adjustment device as an example, As shown in fig. 7, comprising 2 grades of time delay adjustment modules 21 in the time delay adjustment device, every grade of time delay adjustment module 21 is constituted including 12 times take out value module 213,1 time delay elements 211 and 1 selecting unit 212 for taking out value, that is L=4, M=2, N=2, X=2.

Fig. 8 is the corresponding time delay figure of time delay adjustment device shown in Fig. 7, reference picture 8, in over-sampling system, when as shown in Fig. 7 time delay adjustment device without time delay adjustment, when only taking out value by the rate reduction of the initial data of high speed by 2 grades, the data that whole over-sampling system has 3 T are always delayed, the always delay of this 3 T data is the delay that the over-sampling system inherently needs to occur, it is impossible to the decimal delay between the feedback channel and transmission channel appeared in compensation system.

When the decimal time delay that the initial data needs sampled are compensated is, the time delay adjustment device is according to formula first⁰ ·⁷⁵*^Γ'^=(Υι²°^+Υ22ΐ)*^Γ, and formula 0.⁷⁵*Γ' = ³* Γ, is calculated^Yi = l, ^Y2= l;Secondly, the time delay adjustment device according to^γι = 1, ^Y2=l, the choice-start of the selecting unit 233 of first order time delay adjustment module 23 is selected on switch W1, so that the time delay adjustment module 23 adjusts 1 period of time T l (1=Τ of Τ) under Fl (F1=F) data field, knowable to time delay figure shown in reference picture 8,1 Τ of now initial data delay.It is delayed again after 1 T1, what data were taken out value cell in the 1st grade of time delay adjustment module takes out value.After 2 times of value cell are taken out in the 1st grade of time delay adjustment module and takes out value, the cycle of data is changed into Τ Γ

( ΤΓ=Τ2=2Τ).Then by the switch selection of the selecting unit 232 of second level time delay adjustment module 23 on switch W1 so that the time delay adjustment module 21 is in F2

1 period of time T 2 (T2=2T) is adjusted under (F2=l/T2=l/2T=^/2) data field, the time delay figure shown in reference picture 8 is understood, now initial data is equivalent to 2 Τ that are delayed under F data fields.It is delayed again after 1 Τ 2, what data were taken out value cell in the 2nd grade of time delay adjustment module takes out value.After 2 times of value cell 233 are taken out in the 2nd grade of time delay adjustment module 23 and takes out value, the cycle of data is changed into Τ 2,（The Τ of the Τ of Τ 2 ,=Τ ,=2 * 2=4).So, the data that whole over-sampling system has 6 Τ are always delayed.The always delay of this 6 Τ data includes 3 Τ of system as described above delay in itself and 3 Τ adjusted by the present invention delay.By time delay adjustment device by be delayed 3 Τ, realize 0.757 " delay requirement.

The time delay adjustment device that embodiments of the invention are provided, the time delay adjustment device takes out value multiple according to the decimal time delay between feedback channel and transmission channel and time delay means for correcting, it is determined that Every grade of time delay adjustment module is when meeting delay requirement of the corresponding time delay to be corrected under data field, it is necessary to be adjusted under data field⁷^ number, so as to take out value rank according to N number of time delay adjustment module, corresponding time delay to be corrected is adjusted successively from low to high, so as to realize the high-precision time-delay adjustment function that is input to output of the analog signal from time delay adjustment device, and realize that cost is relatively low, cost can be reduced.

The embodiment of the present invention, to the dividing elements of time delay adjustment device, is a kind of exemplary explanation, can have the division methods of a variety of units in practice to constitute the time delay adjustment device of the embodiment of the present invention.The time delay adjustment device of the embodiment of the present invention can be integrated in base station side or mobile management entity side in wireless base system.The function of each modular unit in the time delay adjustment device of the embodiment of the present invention can be realized by the controller in the base station controller or MME in base station.

Embodiments of the invention additionally provide a kind of time delay adjustment method, using the time delay adjustment device 1 as described in Fig. 1,2 correspondence embodiments, specifically, the time delay adjustment device 1 is applied particularly to wireless base system, wherein, as shown in Fig. 9, the time delay adjustment method specifically includes following steps：

301st, time delay adjustment device obtains the decimal time delay and time delay correction parameter between the feedback channel and transmission channel of wireless base system.

Wherein, above-mentioned time delay adjustment parameter includes the over-sampling multiple L of the time delay adjustment device;Above-mentioned decimal time delay is equal to the data-interface cycle of the time delay adjustment device_aTimes, specifically, above-mentioned parameter a span is the decimal less than 1, i.e. 0<a< l.Above-mentioned time delay adjustment parameter includes the over-sampling multiple L of the time delay adjustment device.Over-sampling multiple L is the data-interface speed F of sample clock frequency F and the time delay adjustment device of time delay adjustment device, between the multiple that differs, i.e. F/F'.In addition, because the time delay adjustment device in the embodiment of the present invention is to take out the data-interface speed F that value module drops to the sample clock frequency F of high speed low power speed by N number of,, and each value multiple of taking out for taking out value module in the time delay adjustment device is M, sample clock frequency F and data-interface speed F, between over-sampling multiple be L, therefore, it can draw

302nd, time delay adjustment device is according to over-sampling multiple L and decimal time delay, it is determined that needing to adjust Y time delay adjustment device in the sample clock frequency F data fields of time delay adjustment device Sampling clock cycle τ, just can meet the delay requirement in the data-interface speed data domain of time delay adjustment device of decimal time delay.

First, by said process, time delay adjustment device adjusts Y sampling clock cycle T under sample clock frequency F data fields, just can compensate for the data-interface cycle T of a times of decimal time delay, i.e., " V=" (formula 1);Secondly, because over-sampling multiple L is data-interface speed Fs of the sample clock frequency F with time delay adjustment device of time delay adjustment device, between the multiple that differs, i.e.=F/F', therefore, sample clock frequency F and data-interface speed F, corresponding sampling clock cycle T and data-interface cycle T ' the relation between over-sampling multiple L can be Γ '=￡ * Γ (formula 2);Finally, just Y=* L can be calculated according to formula 1 and formula 2, and then based on above-mentioned formula；T=" *; directly release time delay adjustment device can be multiplied by a with L rounds; so as to obtain Y value, and then time delay adjustment device is adjusted after Y sampling clock cycle T in sample clock frequency F data fields, decimal time delay a* 7 " just can be compensated in data field.

303rd, time delay adjustment device adjusts Y T in F data fields, and takes out value by F by multistage and drop to F'.

Optionally, taking out value by multistage and drop to F in step 303 specifically includes following content：

303a, time delay adjustment device takes out value multiple M according to time delay adjustment device, and taking out value by F by N grades drops to F'.

Wherein, L=M^N', take out in value r grades of above-mentioned N levels take out value be the first data rate for taking out r grades before value drop to r grades of the second data rates taken out after value '；Above-mentioned r F_F' = J_

's^r M^r-¹, it is above-mentioned^r M^r , ≤r≤N。

_F , ₌ _ _{= = F}' carry out afterbody and take out and be worth to, therefore, according to=^^, then N M^N L 。

The time delay adjustment method that embodiments of the invention are provided, it is logical with transmitting according to feedback channel The over-sampling multiple of decimal time delay and time delay means for correcting between road, it is determined that needing the sampling clock cycle T of the time delay adjustment device of adjustment number to be Y in time delay adjustment device sample clock frequency F data fields, just the delay requirement in data field of the decimal time delay can be met, so as to adjust Y T in F data fields, and value is taken out by multistage F is dropped to and then realize the high-precision time-delay adjustment function that is input to output of the analog signal from time delay adjustment device, and realize that cost is relatively low, cost can be reduced, the performance of wireless base system is improved simultaneously.

Embodiments of the invention additionally provide a kind of time delay adjustment method, using the time delay adjustment device 2 as described in the correspondence embodiments of Fig. 4 to 7, specifically, the time delay adjustment device 2 is applied particularly to wireless base system, wherein, as shown in Figure 10, the time delay adjustment method specifically includes following steps：

401st, time delay adjustment device obtains the decimal time delay and time delay correction parameter between the feedback channel and transmission channel of the wireless base system.

Wherein, above-mentioned time delay adjustment parameter includes the over-sampling multiple L of the time delay adjustment device;Above-mentioned decimal time delay is equal to the data-interface cycle of the time delay adjustment device_aTimes, specifically, above-mentioned parameter a span is the decimal less than 1, i.e. 0<a< l.Above-mentioned time delay adjustment parameter includes the over-sampling multiple L of the time delay adjustment device.Over-sampling multiple L is the data-interface speed F of sample clock frequency F and the time delay adjustment device of time delay adjustment device, between the multiple that differs, i.e. F/F'.In addition, because the time delay adjustment device in the embodiment of the present invention is to take out the data-interface speed F that value drops to the sample clock frequency F of high speed low power speed by N grades,, and the value multiple of taking out that every grade of the time delay adjustment device takes out value is M, sample clock frequency F and data-interface speed F, between over-sampling multiple be L, therefore, it can to draw=.

402nd, time delay adjustment device takes out value rank based on time delay allocation strategy and each time delay adjustment module, and decimal time delay is decomposed into N parts of time delays to be corrected.

Wherein, every grade of time delay adjustment module in embodiments of the invention corresponds to a time delay to be corrected respectively；And above-mentioned N parts time delay to be corrected is respectively^αι^Τ '' ⁷" ' ...,^αΝ^Γ , =∑ _{+ +}-+^+' "+), for example, the corresponding time delay to be corrected of r grades of time delay adjustment modules is again^{r e (1},²'…… ' ^N).In addition, time delay adjustment device divides by decimal time delay Solve for N parts it is to be corrected when be delayed, by the time delay that every grade of time delay adjustment module 23 can be compensated is different, therefore time delay adjustment device can be according to the difference of its value of taking out multiple, over-sampling multiple, configure different time delay allocation strategies to carry out the decomposition of decimal time delay for it, the specific time delay allocation strategy can take out value rank and the mapping relations for the time delay that can be compensated for time delay adjustment module, it can also be time delay distribution formula, such as, a* T '=(* Μ. +Υ₂ +…… +Y_r *M^r- ¹ +…… *MW- ¹ ) * Γ。

Exemplary, time delay adjustment device to decimal time delay when decomposing, typically value rank is taken out according to time delay adjustment modules at different levels are corresponding, the time delay adjustment requirement of the decimal time delay is distributed into each time delay adjustment module to disperse to be realized, therefore, above-mentioned decimal time delay is decomposed into Ν parts of time delays to be corrected by time delay adjustment device, i.e., in order to which the time delay for subsequently obtaining every part of time delay to be corrected adjusts demand.But, it should be noted that, when being decomposed to decimal time delay, by the time delay to be corrected that every grade of time delay adjustment module can be corrected has certain scope, therefore, so that time delay adjustment device finally decomposed Ν parts band correction time delay, it may appear that multigroup situation, can optionally one handled.

403rd, time delay adjustment device takes out value multiple Μ according to time delay adjustment module, determine that every grade of time delay adjustment module is meeting Α times of T, delay requirement when, it is necessary to the number of the clock cycle adjusted under the data-rate data domain of this grade of time delay adjustment module.

Optionally, step 403 specifically includes following content：

403 a, time delay adjustment device takes out value multiple M and equation (1) and equation according to time delay adjustment module（2) every grade of time delay adjustment module is determined when meeting A times of delay requirement, it is necessary to the number of the clock cycle adjusted under the data-rate data domain of this grade of time delay adjustment module.Wherein, above-mentioned equation（1) it is： a*r'=(Y₁*M。+Y₂*M¹ +…… +Y_r*M^r— …… +Y_N*M^N-¹) * T；Equation（2) it is： a * T、 = M^N * T 。

Wherein, the data rate taken out before value of above-mentioned and respectively r grade time delay adjustment modules 23 and data cycle, and satisfaction^{7 1 / F}It is above-mentioned to be obtained by being multiplied to round with taking out value multiple M；And the data cycle after r grades of time delay adjustment modules 23 take out value is,^{= M}*^TIt should be noted that it is above-mentioned, be it is also different with its different these three corresponding value for taking out value rank of time delay adjustment module, specifically, each time delay adjustment module 23 have corresponding thereto, It is exemplary, so that r grades of time delay adjustment modules 23 need the number that is adjusted under ^ ^ data fields as an example, specifically, formula^{= α}^^ΜDerivation it is as follows.

First, pass through said process, r grades of time delay adjustment modules 23 lower whole sampling clock cycle T taking out data-rate data domain before value, and just can compensate for time delay to be corrected times takes out data rate after value ' corresponding clock cycle, i.e., '=(formula 3);Secondly as take out the data rate taken out value after of the data rate taken out before value with r grades of time delay adjustment modules 23 that value multiple M is r grades of time delay adjustment modules 23 ' between the multiple that differs, i.e. ,=^/F, therefore, data rate clock cycle corresponding with data rate and clock cycle and the relation taken out between value multiple M can be^{= M}^ (formula 4);Finally, just it can be calculated according to formula 3 and formula 4^{=α Μ}, therefore, based on above-mentioned formula Can directly it release, time delay adjustment device is rounded by being multiplied with M, so as to acquisition value, and then cause r grade time delay adjustment modules 23 adjustment is individual in data-rate data domain take out after value after the data rate C corresponding clock cycle taking out before value, just can in C data domain the time delay * ^ to be corrected of compensation distribution delay requirement.

404th, time delay adjustment device according to, be sequentially adjusted in r grades of time delay adjustment modules corresponding time delay to be corrected times T,.

Optionally, step 404 specifically includes following process：

404a, time delay adjustment device selects any time delay to be corrected, determine the corresponding time delay adjustment module of any correction time delay take out value rank for r grades when, the number adjusted is needed in data field

404b, time delay adjustment device adjusts individual in data field⁷^

404c, time delay adjustment device will drop to '.

r F _F, ₌ J_

Wherein, it is above-mentioned^r, it is above-mentioned^r M^r _oExemplary, as r=l, it is believed that time delay adjustment device carries out taking out value for the first time to F, therefore,^Fi ^{= F}.Accordingly, as r=N, it is believed that time delay adjustment device carry out afterbody take out be worth to because

F F _ ,

This, is according to=MW, then ^⁼^ ^{= = ?}.It should be noted that the decimal time delay being previously mentioned in a copy of it of above-mentioned any time delay to be corrected for the N parts of Yanzhong when to be corrected, above-mentioned N parts time delay composition embodiment of the present invention to be corrected.

The time delay adjustment method that embodiments of the invention are provided, it is logical with transmitting according to feedback channel Decimal time delay and time delay means for correcting between road take out value multiple, the decimal time delay is distributed to time delay adjustment modules at different levels and compensates correction, timing determines every grade of time delay adjustment module when meeting delay requirement of the corresponding time delay to be corrected under data field, need the number adjusted under data field, so as to take out value rank according to N number of time delay adjustment module, corresponding time delay to be corrected is adjusted successively from low to high, so as to realize the high-precision time-delay adjustment function that is input to output of the analog signal from time delay adjustment device, simultaneously because every grade of time delay adjustment module is that the different data cycles are adjusted under different pieces of information domain, and it is longer to take out 1 data cycle of the higher correspondence delay of value rank, so as to greatly reducing the number of time delay elements, so that scheme realizes that cost is relatively low, cost can be reduced, the performance of wireless base system is improved simultaneously.

It is apparent to those skilled in the art that, for convenience and simplicity of description, only it is illustrated with the division of above-mentioned each functional module, in practical application, it can as needed and by above-mentioned functions distribute and be completed by different functional modules, the internal structure of device is divided into different functional modules, to complete all or part of function described above.The specific work process of the system, apparatus, and unit of foregoing description, may be referred to the corresponding process in preceding method embodiment, will not be repeated here.

In several embodiments provided herein, it should be understood that disclosed system, apparatus and method can be realized by another way.For example, device embodiment described above is only schematical, for example, the division of the module or unit, it is only a kind of division of logic function, there can be other dividing mode when actually realizing, such as multiple units or component can combine or be desirably integrated into another system, or some features can be ignored, or do not perform.Another, it, by some interfaces, the INDIRECT COUPLING or communication connection of device or unit, can be electrical, machinery or other forms that shown or discussed coupling or direct-coupling or communication connection each other, which can be,.

The unit illustrated as separating component can be or may not be physically separate, the part shown as unit can be or may not be physical location, a place can be located at, or can also be distributed on multiple NEs.Some or all of unit therein can be selected to realize the purpose of this embodiment scheme according to the actual needs. In addition, each functional unit in the application each embodiment can be integrated in a processing unit or unit is individually physically present, can also two or more units it is integrated in a unit.Above-mentioned integrated unit can both be realized in the form of hardware, it would however also be possible to employ the form of SFU software functional unit is realized.

If the integrated unit is realized using in the form of SFU software functional unit and as independent production marketing or in use, can be stored in a computer read/write memory medium.Understood based on such, the part or all or part of the technical scheme that the technical scheme of the application substantially contributes to prior art in other words can be embodied in the form of software product, the computer software product is stored in a storage medium, including some instructions are to cause a computer equipment（Can be personal computer, server, or network equipment etc.）Or processor（Processor all or part of step of each embodiment methods described of the application) is performed.And foregoing storage medium includes：U disks, mobile hard disk, read-only storage（ROM, Read-Only Memory), random access memory（RAM, Random Access Memory), magnetic disc or CD etc. are various can be with the medium of store program codes.

Described above, above example is only to the technical scheme for illustrating the application, rather than its limitations；Although the application is described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It can still modify to the technical scheme described in foregoing embodiments, or carry out equivalent substitution to which part technical characteristic；And these modifications or replacement, the essence of appropriate technical solution is departed from the spirit and scope of each embodiment technical scheme of the application.

Claims

Claims

1st, a kind of time delay adjustment device, applied to wireless base system, it is characterised in that the device includes：Value module is taken out in data acquisition module, data processing module, X time delay module, selecting module and N number of series connection, N number of each value module correspondence one of taking out taken out in value module takes out value rank, the selecting module is connected with the value module of taking out of N number of series connection, X is the natural number more than 1, N is natural number, wherein：

The data acquisition module, decimal time delay between feedback channel and transmission channel and time delay correction parameter for obtaining the wireless base system；Wherein, the time delay adjustment parameter includes the over-sampling multiple L of the time delay adjustment device;The decimal time delay is the data-interface cycle of a times of the time delay adjustment device, 0<a<l;

The data processing module, for according to the over-sampling multiple L and the decimal time delay, it is determined that needing to adjust the sampling clock cycle T of the Y time delay adjustment devices in the sample clock frequency F data fields of the time delay adjustment device, to meet the delay requirement in the data-interface speed F' data fields of the time delay adjustment device of the decimal time delay；Wherein, the Y is natural number more than 1, and the Y is less than or equal to the X, and the Y is to be multiplied to round acquisition with the L by a, T'=l*T, F=l/T, F=IT

The selecting module, the selecting module is connected to according to the Y in the X time delay module by Y time delay block coupled in series；

The time delay module of the Y series connection, for adjusting Y T in the F data fields;Each time delay module adjusts a T;

Value module is taken out in N number of series connection, for by N grades take out value the F is dropped to it is described.

2nd, device according to claim 1, it is characterised in that the value multiple of taking out for taking out value module is M, L=M^N

N number of r grades taken out in value module take out value module, take out the first data rate before value and drop to the r and take out value module for taking out value module by described r grades and take out described in the second data rate after value=~ ^, described '=_ ^,<r<N\

r^r M^r- ^{1 r} M^r

Wherein, it is that N number of any level taken out in value module takes out value module that above-mentioned r grades, which are taken out value module,.

3rd, a kind of time delay adjustment device, applied to wireless base system, it is characterised in that institute Stating device includes：Data acquisition module, data processing module, N number of time delay adjustment module；Each time delay adjustment module correspondence one in N number of time delay adjustment module takes out value rank, and N is the natural number more than 1, wherein：

The data acquisition module, decimal time delay between feedback channel and transmission channel and time delay correction parameter for obtaining the wireless base system；Wherein, the time delay adjustment parameter takes out value multiple M and over-sampling multiple L including the time delay adjustment device;The decimal time delay is the data-interface cycle Γ ' of a times of the time delay adjustment device, 0<a< l ;

The data processing module, for taking out value rank based on each time delay adjustment module, N parts of time delays to be corrected are decomposed into by the decimal time delay；Wherein, every grade of a time delay to be corrected of time delay adjustment module correspondence；The N parts of time delay to be corrected be^α2' ...,^aThe corresponding time delay to be corrected of r grades of time delay adjustment modules of N is Γ ' again;Re (l, 2 ..., N);

The data processing module, is additionally operable to take out value multiple M according to the time delay adjustment module, determines every grade of time delay adjustment module when meeting a times of Γ ' delay requirement, it is necessary in the data rate of this grade of time delay adjustment module^FThe clock cycle T adjusted under-data field_rNumber 1；Wherein, it is described and 7；The data rate taken out before value of respectively r grades time delay adjustment modules and data cycle, and meet 7；= 1 / ；It is described to be obtained by being multiplied to round with taking out value multiple M；The data cycle after r grades of time delay adjustment modules take out value is Γ,^{= M}, N number of time delay adjustment module for basis, is sequentially adjusted in the T' of the corresponding time delay to be corrected times of r grades of time delay adjustment modules.

4th, device according to claim 3, it is characterized in that, each time delay adjustment module includes taking out value cell, time delay elements and selecting unit, the time delay elements include X time delay subelement, and X is connected for the natural number and X more than 1 more than the selecting module with the value cell of taking out；

The selecting unit in r grades of time delay adjustment modules in the Ν time delay adjustment module, for according to the selecting unit being connected to individual time delay subelement in the r grades of time delay adjustment modules in the r grades of time delay adjustment modules；

The time delay subelement of described series connection, for adjusting individual 7 in data field；;Each time delay subelement adjusts 17；；

Value cell is taken out in the r grades of time delay adjustment modules, for by described in described drop to F';Wherein, described 7 '=, l≤_r<N;

r^r M^r- ^{1 r} M^r

Wherein, r grades of above-mentioned time delay adjustment modules are any level time delay adjustment module in N number of time delay adjustment module.

5th, the device according to claim 3 or 4, it is characterised in that the data processing module is according to equation（And equation 1)（2) the clock cycle T for needing to adjust under the data-rate data domain of time delay adjustment modules at different levels is determined_rNumber 1；

a*r'=(Y₁*M。+Y₂*M¹+…… +Y_r*M^r— …… +Υ_Ν*Μ^Ν'^ι)*Τ (1) α*Τ'^Μ^Ν*Τ (2)。

6th, a kind of time delay adjustment method, applied to time delay adjustment device, the time delay adjustment device is applied to wireless base system, it is characterised in that including：

Obtain the decimal time delay and time delay correction parameter between the feedback channel and transmission channel of the wireless base system；Wherein, the time delay adjustment parameter takes out value multiple Μ and over-sampling multiple L including the time delay adjustment device;The decimal time delay is the data-interface cycle Γ ' of a times of the time delay adjustment device, 0<a<l;

According to the over-sampling multiple L and the decimal time delay, it is determined that needing to adjust the sampling clock cycle T of the Y time delay adjustment devices in the sample clock frequency F data fields of the time delay adjustment device, the delay requirement in the data-interface speed F' data fields of the time delay adjustment device of the decimal time delay just can be met；Wherein, the Y is the natural number more than 1, and the Y is to be multiplied to round acquisition with L by a, T'=L*T;

Adjust Y T in the F data fields, and taken out by multistage described in value drops to the F.

7th, method according to claim 6, it is characterised in that it is described value is taken out by multistage the F is dropped into the F' specifically include：Value multiple M is taken out according to the time delay adjustment device, by N grades take out value the F is dropped to it is described；Wherein, L=M^N', it is that the first data rate for taking out r grades before value drops to described in described r grades the second data rates taken out after value=_ ^ that N grades of r grades taken out in value, which take out value, described '=,≤r≤N.

M^r M^r

8th, a kind of time delay adjustment method, applied to time delay adjustment device, the time delay adjustment device is applied to wireless base system, it is characterised in that including：

Obtain the decimal time delay and time delay correction parameter between the feedback channel and transmission channel of the wireless base system；Wherein, the time delay adjustment parameter includes taking out for the time delay adjustment device It is worth multiple M;The decimal time delay is the data-interface cycle Γ of a times of the time delay adjustment device, 0<a< l；

Value rank is taken out based on each time delay adjustment module, the decimal time delay is decomposed into N parts of time delays to be corrected；Wherein, the value rank of taking out of the N time delay adjustment module is set to N grades, and each time delay adjustment module correspondence one takes out value rank, every grade of a time delay to be corrected of time delay adjustment module correspondence；The N parts of time delay to be corrected is ^ ... '^αThe corresponding time delay to be corrected of r grades of time delay adjustment modules is Γ ' again;R e (1,2 ..., N)；

Value multiple M is taken out according to the time delay adjustment module, determines every grade of time delay adjustment module when meeting A times of Γ ' delay requirement, it is necessary to the clock cycle 7 adjusted under the data-rate data domain of this grade of time delay adjustment module；Number;Wherein, it is described and 7；The data rate taken out before value of respectively r grades time delay adjustment modules and data cycle, and meet 7；= 1/ ；It is described to be obtained by being multiplied to round with taking out value multiple M；The data cycle after r grades of time delay adjustment modules take out value is=M * T_r .

According to being sequentially adjusted in corresponding ^ times of the time delay to be corrected of r grades of time delay adjustment modules

Γ。

9th, method according to claim 8, it is characterised in that described according to 1, is sequentially adjusted in specifically including for r grades of corresponding ^ times of time delays to be corrected of time delay adjustment module：Select any time delay to be corrected, determine the corresponding time delay adjustment module of any correction time delay take out value rank for r grades when, the number adjusted is needed in data field

Adjusted in data field individual

By it is described drop to it is described '；Wherein, described=^ y, described '=" ^, l≤r≤N;

r^{r r} M^{r r} M^r

Wherein, a copy of it of Yanzhong when any time delay to be corrected is described Ν parts to be corrected, the Ν parts of time delay to be corrected constitutes the decimal time delay.

10th, method according to claim 8 or claim 9, it is characterized in that, it is described that value multiple Μ is taken out according to the time delay adjustment module, determine every grade of time delay adjustment module when meeting A times of Γ ' delay requirement, it is necessary to the clock cycle 7 adjusted under the data-rate data domain of this grade of time delay adjustment module；Number；Specifically include：

Value multiple M and equation are taken out according to the time delay adjustment module（And equation 1)（2) every grade of time delay adjustment module is determined when meeting a times of Γ delay requirement, it is necessary to during at this grade The clock cycle T adjusted under the data-rate data domain for prolonging correction module_rNumber 1；

α*Τ' = Μ^Ν*Τ

-21 -