CN105428524B - The method for manufacturing phase-change memory - Google Patents
The method for manufacturing phase-change memory Download PDFInfo
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- CN105428524B CN105428524B CN201510738267.5A CN201510738267A CN105428524B CN 105428524 B CN105428524 B CN 105428524B CN 201510738267 A CN201510738267 A CN 201510738267A CN 105428524 B CN105428524 B CN 105428524B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
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- 230000008859 change Effects 0.000 claims abstract description 36
- 238000010438 heat treatment Methods 0.000 claims abstract description 32
- 239000012782 phase change material Substances 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000007772 electrode material Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims description 57
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000000576 coating method Methods 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 5
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- 238000000227 grinding Methods 0.000 claims description 3
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- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 149
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- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 229910018110 Se—Te Inorganic materials 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
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- 229910052731 fluorine Inorganic materials 0.000 description 2
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- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- 229910005900 GeTe Inorganic materials 0.000 description 1
- 229910005939 Ge—Sn Inorganic materials 0.000 description 1
- 229910017629 Sb2Te3 Inorganic materials 0.000 description 1
- 229910020938 Sn-Ni Inorganic materials 0.000 description 1
- 229910020923 Sn-O Inorganic materials 0.000 description 1
- 229910002855 Sn-Pd Inorganic materials 0.000 description 1
- 229910018731 Sn—Au Inorganic materials 0.000 description 1
- 229910008937 Sn—Ni Inorganic materials 0.000 description 1
- 229910008772 Sn—Se Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- CFOAUMXQOCBWNJ-UHFFFAOYSA-N [B].[Si] Chemical compound [B].[Si] CFOAUMXQOCBWNJ-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical compound [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- 235000013399 edible fruits Nutrition 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- 229920000642 polymer Polymers 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
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- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
A kind of method for manufacturing phase-change memory：(i) heating element is formed on semiconductor substrate；(ii) the first dielectric layer is formed above semiconductor substrate and heating element, and there is the first dielectric layer opening to expose heating element；(iii) side wall that barrier layer lining wraps up in opening is formed；(iv) form phase-change material layer and cover the first dielectric layer and barrier layer, and fill opening；(v) remove phase-change material layer and be located at the part of the first dielectric layer, and expose the first dielectric layer；(vi) form phase change element in the opening, the upper surface of phase change element and and barrier layer define recess；(vii) form electrode material layer and cover the first dielectric layer, and fill recess；And (viii) removes the part that electrode material layer is located at the first dielectric layer, and formed and be embedded the electrode structure in recess.The above method can solve the alignment issues in exposure manufacture process.
Description
Technical field
The invention relates to a kind of manufacture method of phase-change memory device.
Background technology
Computer or other electronic devices are commonly configured with various types of memory bodys, such as random access memory
(RAM), read-only memory (ROM), Dynamic Random Access Memory (DRAM), synchronous dynamic random-access memory body (SDRAM),
Phase change random access memory (PCRAM) or fast flash memory bank.Phase-change memory is non-volatile memory body, can be passed through
Measure the resistance value of memory cell and obtain and be stored in data therein.Add in general, phase-change memory unit includes
Thermal element and phase change cell, phase change cell can be because be heated and undergoing phase transition.When being passed through electric current to heating element,
Heating element converts electric energy into heat, and caused heat promotes phase change cell to occur the change of phase, such as from amorphous phase
(amorphous) it is transformed into more crystalline phases (polycrystalline).Phase change cell mutually has different resistance in different
Value, via the resistance value for detecting or reading phase change cell, is just able to judge the data types of memory cell.At present, phase transformation
The manufacturing process for changing memory body still faces some problems, it is therefore necessary to proposes a kind of more preferable manufacture method.
The content of the invention
It is an aspect of the present invention to provide a kind of manufacture method of phase-change memory, the one of which technology of the method is imitated
Fruit is the alignment issues solved in exposure manufacture process.Another of the method has the technical effect that manufactured phase-change memory can
Effectively the material of phase change element is prevented to be diffused into neighbouring dielectric layer.
Various embodiments according to the present invention, the method include following operation：(i) heating element is formed in semiconductor
On base material；(ii) the first dielectric layer is formed above semiconductor substrate and heating element, wherein the first dielectric layer has at least one
Opening exposes heating element；(iii) side wall that barrier layer lining wraps up in opening is formed；(iv) phase change element is formed in opening,
Wherein the upper surface of phase change element and barrier layer define a recess；(v) form electrode material layer and cover the first dielectric layer,
And fill recess；And (vi) removes the part that electrode material layer is located at the first dielectric layer, and formed and be embedded in recess
Electrode structure.
In some embodiments, aforesaid operations (iv) comprise the steps of：(a) phase-change material layer covering first is formed
Dielectric layer and barrier layer, and fill opening；(b) remove phase-change material layer and be located at the part of the first dielectric layer, and expose
Go out the first dielectric layer；And (c) removes a part for the phase-change material layer in opening, make phase-change material layer in opening
Residual fraction forms phase change element.
In some embodiments, semiconductor substrate includes first electrode and the second dielectric in first electrode
There is through hole to expose first electrode for layer, the second dielectric layer, and wherein heating element is filled in through-holes, and connects first electrode.
In some embodiments, the second dielectric layer and barrier layer include identical material, and the identical material is
Selected from by silicon nitride, the silicon nitride of adulterated al, adulterated al silica, adulterate boron silicon nitride, adulterate phosphorus silicon nitride, nitrogen oxygen
The group that SiClx (silicon oxynitride), tin oxide and combinations of the above are formed.
In some embodiments, the resistance value of heating element is more than the resistance value of first electrode, and the width of heating element
Width of the degree less than first electrode.
In some embodiments, the width of the opening is more than the width of heating element.
In some embodiments, the operation for forming barrier layer comprises the steps of：The deposition resistance of conformal (conformal)
Barrier the first dielectric layer of material layer coating and opening, wherein barrier material layer include horizontal component and vertical component, horizontal component
The upper surface of the first dielectric layer of coating and the bottom of opening, the side wall of vertical component coating opening；And lost using anisotropic
The horizontal component for removing barrier material layer is carved, and forms barrier layer.
In some embodiments, barrier layer include an at least material be selected from by silicon nitride, adulterated al silicon nitride, mix
The silica of miscellaneous aluminium, the silicon nitride for adulterating boron, the silicon nitride for adulterating phosphorus, silicon oxynitride (silicon oxynitride), oxidation
The group that tin and combinations of the above are formed.
In some embodiments, the operation bag for removing phase-change material layer and being located at the part of the first dielectric layer
Containing using chemical mechanical grinding.
In some embodiments, the operation of the part for removing the phase-change material layer in opening is included using wet
Formula etches.
In some embodiments, the depth of recess is about 25nm to about 200nm, and the thickness of phase change element is about
25nm to about 200nm.
Brief description of the drawings
Fig. 1 illustrates the flow chart of the method for the manufacture phase-change memory of various embodiments according to the present invention；
Fig. 2 illustrate Fig. 1 execution operation 12 after resulting structures upper schematic diagram；
Fig. 3-Figure 13 illustrates diagrammatic cross-section of the various embodiments of the present invention under different process stages.
Embodiment
In order to make the description of the present invention more exhaustive and complete, below for embodiments of the present invention and specific implementation
Example proposes illustrative description；But this not implements or the unique forms with the specific embodiment of the invention.It is disclosed below
Each embodiment, beneficial in the case of can be mutually combined or substitute, can also add others embodiments in one embodiment, and
Without further record or explanation.
Recently, some technical problems are faced when developing " phase-change memory " (phase-change memory).Example
Such as, when using general deposition-lithographic-etch process to form patterned phase change element, micro-photographing process can face pair
The problem of quasi-.Specifically, after depositing one layer of phase-transition material on a semiconductor substrate, because the light of phase-transition material penetrates
Rate is smaller, and the phase-change material layer deposited can cover the alignment mark (alignment mark) on semiconductor substrate, cause
Follow-up micro-photographing process can not be aligned accurately.A kind of method of solution is that first the phase-change material layer of deposition is carried out
Once rough lithographic-etch process, to remove the part that alignment mark is covered in phase-change material layer, allows on semiconductor substrate
Alignment mark be exposed.Then, accurately aligned using the alignment mark exposed, and perform again a lithographic-
Etch process, and form the phase change element with accurate pattern.Above-mentioned settling mode, do not merely have to using it is extra once
Rough lithographic-etch process, and this step has to rely on the experience of operational staff individual and judges to complete.
An aspect of of the present present invention relates to a kind of method for manufacturing phase-change memory.The manufacture method tool herein proposed
Standby multiple technologies effect, one of which technique effect is that can avoid above-mentioned alignment issues completely.
In the following description, many specific details be will be described in detail so that reader can fully understand following embodiment.
However, the embodiment of the present invention can be put into practice in the case of without these specific details.In other cases, it is ripe to simplify attached drawing
The structure known only symbolically is illustrated in figure with device.
Space relative terms used herein, for example, " lower section ", " under ", " top ", " on " etc., this is in order to just
Relativeness between one element of narration or feature and another element or feature, as depicted in figure.These phases spatially
Other orientation are included to the true meaning of term.For example, when diagram spins upside down 180 degree, an element and another element it
Between relation, may from " lower section ", " under " become " top ", " on ".In addition, spatially opposite used herein
Narration should also make same explanation.
Fig. 1 illustrates the flow chart of the method 10 of the manufacture phase-change memory of various embodiments according to the present invention.Method
10 include operation 12, operation 14, operation 16, operation 18, operation 20, operation 22, operation 24 and operation 26.Fig. 2-Figure 13 is illustrated
Schematic diagram of the various embodiments of the present invention in different process stages.Although a series of operation used herein illustrates herein
The method of exposure, but the order shown in these operations is not construed as the limitation of the present invention.Specifically, some operations
It can in a different order carry out or be carried out at the same time with other steps.In addition, and the not all operation illustrated and/or step be all
It is necessary to realize embodiments of the present invention.In addition, each operation described herein can include multiple steps or dynamic
Make, to realize described operation.
Fig. 1 is refer to, in operation 12, forms an at least heating element on semiconductor substrate.Fig. 2 illustrate the present invention certain
A little embodiments perform the upper schematic diagram of operation 12, and Fig. 3 is illustrated in Fig. 2 along the diagrammatic cross-section of line segment 3-3 '.Such as Fig. 2 and figure
Shown in 3, heating element 120 is formed on semiconductor substrate 100.In some embodiments, semiconductor substrate 100 includes actively
Element 102, interlayer dielectric layer (ILD) 104, vertical interconnecting structure 106 and first electrode 108 are (for example, each memory cell
Bottom electrode).In some embodiments, semiconductor substrate 100 includes insulate on doped or undoped Silicon Wafer or semiconductor
Body (SOI) base material.Active member 102 may be, for example, N-type metal-oxide semiconductor (MOS) (NMOS) element, p-type metal oxide half
Conductor (PMOS) element or complementary metal oxide semiconductor (CMOS) element or similar element.In certain embodiments
In, active member 102 includes grid 102G and source/drain region 102S, 102D.In certain embodiments, semiconductor substrate 100
At least one shallow slot isolation structure 103 is also included, to isolate the drain region 102D between two active members 102.Layer
Between dielectric layer 104 can be any suitable dielectric material, such as silicon nitride, silica, the dielectric material such as silica glass of doping,
Interlayer dielectric layer 104 can also be formed by the dielectric material of low-k, such as phosphosilicate glass (PSG), boron phosphorus silicon
Glass (BPSG), fluorine silica glass (FSG), carbofrax material or combinations of the above or similar material.In some embodiments,
Semiconductor substrate 100 also includes metal silicide layer 105, and in source/drain region 102S, 102D, vertical interconnecting structure 106 passes through
Source/drain region 102S, 102D is electrically connected to by metal silicide layer 105.In one embodiment, vertical interconnecting structure 106
It may be, for example, the metal via structure for including tungsten (W) material.In some embodiments, semiconductor substrate 100 also includes dielectric
Layer 116, dielectric layer 116 is formed in the top of interlayer dielectric layer 104 and first electrode 108, and dielectric layer 116 has through hole 116a
In the top of first electrode 108.The through hole 116a of dielectric layer 116 exposes first electrode 108.
In some embodiments, heating element 120 is formed in the through hole 116a of dielectric layer 116, and entity connects
First electrode 108.Heating element 120 has higher resistance value, when electric current is by heating element 120,120 meeting of heating element
The electric energy of a part is transformed into thermal energy, therefore produces heat.The material of heating element 120 may be, for example, titanium nitride (TiN), nitrogen
Change combination or the similar material of tantalum (TaN), titanium (Ti) or above-mentioned material.In certain embodiments, the resistance of heating element 120
Resistance value of the value higher than first electrode 108.In certain embodiments, heating element 120 may be, for example, column structure, and heat
The width W1 of element 120 is less than the width W2 of first electrode 108.
In the operation 14 shown in Fig. 1, the first dielectric layer is formed above semiconductor substrate and heating element.Fig. 4-Fig. 5
Illustrate the diagrammatic cross-section of the execution operation 14 of certain embodiments of the present invention.As shown in figure 4, sequentially sink on dielectric layer 116
Product dielectric layer 135 and dielectric layer 137, and form the first dielectric layer 130.Although Fig. 4 illustrates the first dielectric layer 130 and includes multilayer
Dielectric layer, but in certain embodiments, the first dielectric layer 130 can also be single layer structure.First dielectric layer 130 can pass through
Such as rotary coating mode, chemical vapor deposition (CVD) and/or plasma enhanced chemical vapor (PECVD) etc. are any appropriate
Method is formed.Then, patterning mask layer 138 is formed above the first dielectric layer 130, patterning mask layer 138 can be such as
For eurymeric photoresist or other suitable hard mask (hard mask) layers.In this operation, because not having also on semiconductor substrate 100
Have and deposit any phase-transition material, so exposure sources can be gone forward side by side with the alignment mark in clear view to semiconductor substrate
Row accurately aligns and forms accurately patterning mask layer 138.Afterwards, as shown in figure 5, being lost to the first dielectric layer 130
Scribe journey and opening 132 is formed in the first dielectric layer 130, opening 132 exposes at least one heating element 120, therefore opens
The width W3 of mouth 132 is more than the width W1 of heating element 120 (sign is in figure 3).Any appropriate technology may serve to shape
Into opening 132.
In some embodiments, dielectric layer 137 and dielectric layer 116 may be, for example, made by silicon nitride or similar material,
Dielectric layer 135 may be, for example, made by silica or similar material, dielectric layer 135 be interposed in dielectric layer 116 and dielectric layer 137 it
Between.In certain embodiments, the thickness of dielectric layer 135 is more than the thickness of dielectric layer 137 and/or dielectric layer 116.
In other certain embodiments, the first dielectric layer 130 can include one layer or more phosphosilicate glass (PSG),
The combination or the like of boron-phosphorosilicate glass (BPSG), fluorine silica glass (FSG), polymer, carborundum or above-mentioned material.
In operation 16, the side wall that barrier layer lining wraps up in opening is formed.Fig. 6-Fig. 7 illustrates the shape of certain embodiments of the present invention
Into the diagrammatic cross-section of barrier layer.First, as shown in fig. 6, the deposition barrier material layer 140a coatings of conformal (conformal)
The inner surface of one dielectric layer 130 and opening 132.Specifically, barrier material layer 140a includes horizontal component 142 and hangs down
Straight part 144, the horizontal component 142 of barrier material layer 140a cover upper surface 131 and the opening 132 of the first dielectric layer 130
Bottom 134, the vertical component 144 of barrier material layer 140a is coated on the side wall 132a of opening 132.
In some embodiments, barrier material layer 140a is to use the deposition technique of code-pattern and formed, such as physics
Vapor deposition process (PVD), chemical vapor deposition process (CVD), plasma enhanced chemical vapor (PECVD), atomic layer deposition
Processing procedure (ALD) and/or atomic layer chemical vapor deposition processing procedure (ALCVD) etc..In certain embodiments, barrier material layer 140a is
Made by dielectric material.Specifically, barrier layer barrier material layer 140a can include silicon nitride, the silicon nitride of adulterated al, doping
The silica of aluminium, the silicon nitride for adulterating boron, silicon nitride, silicon oxynitride (silicon oxynitride), the tin oxide for adulterating phosphorus
Or combination or the similar material of above-mentioned material.
Then, as shown in fig. 7, removing the horizontal component 142 of barrier material layer 140a using anisotropic etching, and hinder
The vertical component 144 that barrier material layer 140a left behind forms barrier layer 140, and barrier layer 140 serves as a contrast the side wall for wrapping up in opening 132
132a.In this operation, because of the deposition technique using code-pattern and comprehensive anisotropic etching, so in this operation
Without having to the alignment mark used on semiconductor substrate.
In operation 18, form phase-change material layer and cover the first dielectric layer and barrier layer, and fill opening.In some realities
Apply in mode, as shown in figure 8, using such as physical vapour deposition (PVD) processing procedure (PVD), chemical vapor deposition process (CVD), plasma
The blankets such as Assisted Chemical Vapor (PECVD), atomic layer deposition processing procedure (ALD) and/or atomic layer chemical vapor deposition processing procedure (ALCVD)
The deposition technique of formula is covered to form phase-change material layer 150.Phase-change material layer 150 covers the first dielectric layer 130 and barrier layer
140, and fill opening 132.In more detail, phase-change material layer 150 includes the part for being deposited on the top of the first dielectric layer 130
The phase-transition material 150a and partial phase change material 150b being filled in opening 132.In this operation, phase-change material layer
150 are formed by the deposition technique of code-pattern, and without having to the alignment mark used on semiconductor substrate.In some implementations
In mode, phase-change material layer 150 includes germanium-antimony-tellurium (GST) material, such as Ge2Sb2Te5、Ge1Sb2Te4、Ge1Sb4Te7Or
Combinations of the above or similar material.Other phase-transition materials may be, for example, GeTe, Sb2Te3、GaSb、InSb、Al-Te、Te-
Sn-Se、Ge-Sb-Te、In-Sb-Te、Ge-Se-Ga、Bi-Se-Sb、Ga-Se-Te、Sn-Sb-Te、In-Sb-Ge、Te-Ge-
Sb-S、Te-Ge-Sn-O、Sb-Te-Bi-Se、Te-Ge-Sn-Au、Pd-Te-Ge-Sn、In-Se-Ti-Co、Ge-Sb-Te-Pd、
Ag-In-Sb-Te, Ge-Te-Sn-Pt, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd and Ge-Sb-Se-Te.
In operation 20, remove phase-change material layer and be located at the part of the first dielectric layer, and expose the first dielectric
Layer.In some embodiments, as shown in figure 9, removing the part that phase-change material layer 150 is located at the top of the first dielectric layer 130
150a, and expose the first dielectric layer 130.In one embodiment, operation 20 is included removes position using chemical mechanical grinding
The partial phase change material 150a of phase-change material layer 150 above the first dielectric layer 130, but leave inside opening 132
The partial phase change material 150b of phase-change material layer 150.In this operation, because being moved using comprehensive eatch-back mode
Except the phase-change material layer 150 of a part, so this is operated without having to using the alignment mark on semiconductor substrate.Implement one
In example, operation 20 includes the first dielectric layer 130 for removing a part, such as removes dielectric layer 137.
In operation 22, phase change element is formed, the upper surface of phase change element and barrier layer define a recess.
In certain embodiments, as shown in Figure 10, remaining phase-transition material is etched back, and forms phase change element 152.Citing
For, the phase-transition material of part is removed to the part 150b progress wet etching processing procedures of phase-change material layer, remainder
Phase-transition material then forms phase change element 152, and the upper surface 152a of phase change element 152 is less than the table of the first dielectric layer 130
Face, therefore the upper surface 152a of phase change element 152 defines recess 154 with barrier layer 140.In certain embodiments, recess
154 depth D1 is about 25nm to about 200nm, for example, about 30nm, 40nm, 50nm, 60nm, 80nm, 100nm or 150nm.
In addition in some embodiments, the thickness T1 of phase change element 152 is about 25nm to about 200nm, for example, about 30nm, 40nm,
50nm, 60nm, 80nm, 100nm or 150nm.In a specific embodiment, the depth D1 of recess 154 is substantially equal to phase change
The thickness T1 of element 152.
In operation 24, form electrode material layer and cover the first dielectric layer, and fill recess.In some embodiments,
As shown in figure 11, electrode material layer 160 is formed on the first dielectric layer 130, and electrode material layer 160 fills recess 154.In detail
Thin says, electrode material layer 160 includes some electrode materials 160a for being deposited on the top of the first dielectric layer 130 and is filled in recessed
Some electrode materials 160b in mouth 154.For example, physical vapour deposition (PVD) processing procedure (PVD), chemical vapor deposition can be used
Processing procedure (CVD), plasma enhanced chemical vapor (PECVD), atomic layer deposition processing procedure (ALD) and/or atomic layer chemical vapor are sunk
The deposition technique of product processing procedure (ALCVD) etc. code-pattern forms electrode material layer 160.In some embodiments, electrode material
Layer 160 includes combination or the similar material of titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti) or above-mentioned material.Implement one
In example, electrode material layer 160 is with first electrode 108 made by identical material.In operation 24, electrode material layer 160 is
Formed by the deposition technique of code-pattern, so this is operated without having to using the alignment mark on semiconductor substrate.
In operation 26, the part that electrode material layer is located at the first dielectric layer is removed, and is formed and is embedded in recess
Second electrode.In some embodiments, as shown in figure 11, the electrode material layer positioned at the top of the first dielectric layer 130 is removed
160 some electrode materials 160a, but retain some electrode materials 160b of electrode material layer 160 in recess 154, and formed embedding
The second electrode 162 being located in recess 154.In certain embodiments, operation 26 is included and moved using CMP step
Except the part 160a for the electrode material layer 160 for being deposited on the top of the first dielectric layer 130, and remaining electrode material layer 160 is formed
It is embedded the second electrode 162 in recess 154.In certain embodiments, the upper surface of second electrode 162 is substantially situated between with first
The upper surface of electric layer 130 extends on sustained height.It is to remove part using the eatch-back mode of holohedral form in this operation
Electrode material layer 160, this operation is also without having to the alignment mark used on semiconductor substrate.
It was found from various embodiments described above, in operation 14 into operation 26, only operation 14 must be used and partly led
Alignment mark on body base material is aligned, and others operation is all without having to using the alignment mark on semiconductor substrate, therefore
Efficiently solve previously described alignment issues.Technique effect described herein be only in many technological merits of the present invention wherein
One, it should not be limited the scope of the invention with this technique effect.
In addition, in the structure shown in Figure 12, phase change element 152 is situated between by barrier layer 140, second electrode 162 and second
Electric layer 116 intactly envelopes.In a specific embodiment, the second dielectric layer 116 and barrier layer 140 include identical material,
For example, silicon nitride, the silicon nitride of adulterated al, the silica of adulterated al, the silicon nitride for adulterating boron, silicon nitride, the nitrogen oxygen of doping phosphorus
Combination or the similar material of SiClx (silicon oxynitride), tin oxide and/or above-mentioned material.These above-mentioned material energy
Enough the material of phase change element 152 is prevented to penetrate.So the material of phase change element 152 can be effectively prevented in follow-up process
Material is penetrated into because of diffusion phenomena in neighbouring dielectric layer.In addition, barrier layer 140 can preserve heat caused by heating element
Amount, contributes to phase change element that the change of crystalline phase occurs.Above-mentioned technique effect is only its in many technological merits of the present invention
In one, the present invention be not only restricted to above-mentioned technique effect.
Various embodiments according to the present invention, other operations or step can be carried out after operation 26.Citing and
Speech, as shown in figure 13, forms the 3rd dielectric layer 170 of single or multiple lift in the structure that Figure 12 is illustrated, then forms multiple pass through
The perforate 180 of the 3rd dielectric layer 170 and/or the first dielectric layer 130 is worn, and vertical interconnecting structure is formed in these perforates 180
191、192.Vertical interconnecting structure 191 connects phase change element 152 via second electrode 162, and is electrically connected drain region
102D.Vertical interconnecting structure 192 is then electrically connected source region 102S.Afterwards, can be formed other various logic circuits or
Functional circuit.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any to be familiar with this skill
Person, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations, therefore protection scope of the present invention is worked as
Subject to the scope of which is defined in the appended claims.
Claims (9)
- A kind of 1. method for manufacturing phase-change memory, it is characterised in that include：An at least heating element is formed on semiconductor base material；One first dielectric layer is formed above the semiconductor substrate and the heating element, wherein first dielectric layer has at least one Opening exposes the heating element；It is horizontal that conformal one barrier material layer coating first dielectric layer of deposition and the opening, wherein the barrier material layer include one Part and a vertical component, a upper surface of the horizontal component coating first dielectric layer and a bottom of the opening, this hangs down The one side wall of the straight part coating opening；The horizontal component of the barrier material layer is removed using anisotropic etching, and is formed One barrier layer serves as a contrast the side wall for wrapping up in the opening；A phase change element is formed in the opening, wherein a upper surface of the phase change element and the barrier layer define one Recess；Form an electrode material layer and cover first dielectric layer, and fill the recess；AndThe part that the electrode material layer is located at first dielectric layer is removed, and is formed and is embedded the electrode knot in the recess Structure.
- 2. it is according to claim 1 manufacture phase-change memory method, it is characterised in that formed the phase change element in Operation in the opening comprises the steps of：Form a phase-change material layer and cover first dielectric layer and the barrier layer, and fill the opening；Remove the phase-change material layer and be located at the part of first dielectric layer, and expose first dielectric layer；AndA part for the phase-change material layer in the opening is removed, makes the residual fraction of the phase-change material layer in the opening Form the phase change element.
- 3. the method for manufacture phase-change memory according to claim 1, it is characterised in that the semiconductor substrate includes one First electrode and one second dielectric layer are located on the first electrode, which there is a through hole to expose first electricity Pole, the wherein heating element are filled in the through hole, and connect the first electrode.
- 4. the method for manufacture phase-change memory according to claim 3, it is characterised in that second dielectric layer and the resistance Barrier layer includes an identical material, and the identical material is the oxidation being selected from by silicon nitride, the silicon nitride of adulterated al, adulterated al Silicon, the silicon nitride for adulterating boron, adulterate the group that silicon nitride, silicon oxynitride, tin oxide and the combinations of the above of phosphorus are formed.
- 5. the method for manufacture phase-change memory according to claim 3 a, it is characterised in that resistance of the heating element Value is more than a resistance value of the first electrode, and a width of the heating element is less than a width of the first electrode.
- 6. the method for manufacture phase-change memory according to claim 1, it is characterised in that the width of the opening is more than should The width of heating element.
- 7. the method for manufacture phase-change memory according to claim 1, it is characterised in that the barrier layer includes at least one Material is selected from by the nitridation of silicon nitride, the silicon nitride of adulterated al, the silica of adulterated al, the silicon nitride for adulterating boron, doping phosphorus The group that silicon, silicon oxynitride, tin oxide and combinations of the above are formed.
- 8. the method for manufacture phase-change memory according to claim 2, it is characterised in that remove the phase-change material layer The step of positioned at the part of first dielectric layer, includes and uses chemical mechanical grinding；AndRemove a part for the phase-change material layer in the opening operation include use Wet-type etching.
- 9. the method for manufacture phase-change memory according to claim 1, it is characterised in that the depth of the recess is 25nm To 200nm, and the thickness of the phase change element is 25nm to 200nm.
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| CN103137862A (en) * | 2011-12-02 | 2013-06-05 | 旺宏电子股份有限公司 | Memory device and manufacturing method thereof |
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| KR100626381B1 (en) * | 2004-07-19 | 2006-09-20 | 삼성전자주식회사 | Phase change memory device and its formation method |
| US7754522B2 (en) * | 2008-08-06 | 2010-07-13 | Micron Technology, Inc. | Phase change memory structures and methods |
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| CN101132051A (en) * | 2006-08-22 | 2008-02-27 | 尔必达存储器股份有限公司 | Semiconductor memory device and fabrication method thereof |
| CN103137862A (en) * | 2011-12-02 | 2013-06-05 | 旺宏电子股份有限公司 | Memory device and manufacturing method thereof |
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