CN105427789A - Drive circuit, array substrate and display device - Google Patents
Drive circuit, array substrate and display device Download PDFInfo
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- CN105427789A CN105427789A CN201511031628.9A CN201511031628A CN105427789A CN 105427789 A CN105427789 A CN 105427789A CN 201511031628 A CN201511031628 A CN 201511031628A CN 105427789 A CN105427789 A CN 105427789A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
- G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
Abstract
The invention provides a driving circuit, an array substrate and a display device, wherein the driving circuit comprises at least one stage of virtual stage shift register; and a shift register group electrically connected to the virtual stage shift register in a cascade manner; the shift register group comprises a first-stage shift register to an Nth-stage shift register, the occupied layout area of the virtual-stage shift register is smaller than that of the ith-stage shift register, N is an integer not smaller than 2, and i is a positive integer not larger than N. Because the occupied layout area of the virtual stage shift register is smaller than that of the ith stage shift register, the frame area of the display device can be relatively reduced, and the narrow frame requirement of the display device is met.
Description
Technical field
The present invention relates to display technique field, more specifically, relate to a kind of driving circuit, array base palte and display device.
Background technology
Existing display device, comprises viewing area and the frame region being positioned at this viewing area surrounding.In this display device, driving chip provides drive singal by the driving circuit that is integrated in frame region to the pixel cell of viewing area, controls the display that pixel cell carries out picture.
In prior art; reset signal is provided in order to avoid the output of rub-out signal for giving the shift register in driving circuit; usually vitual stage shift register can be added in the driving circuit; this vitual stage shift register is arranged in one end or the two ends of the shift register of the multiple cascade of driving circuit, to provide reset signal to shift register.But the introducing due to vitual stage shift register can cause the frame of display device wider, therefore, the narrow frame design of display device is unfavorable for.
Summary of the invention
In view of this, the invention provides a kind of driving circuit, array base palte and display device, to solve owing to introducing the wider problem of display device frame that vitual stage shift register causes.
For achieving the above object, technical scheme provided by the invention is as follows:
A kind of driving circuit, comprising:
At least one-level vitual stage shift register;
And, the shift register group be electrically connected in cascaded fashion with described vitual stage shift register;
Wherein, described shift register group comprises first order shift register to N level shift register, and described vitual stage shift register take that chip area is less than described i-th grade of shift register take chip area, N be not less than 2 integer, i is the positive integer being not more than N.
A kind of array base palte, comprise viewing area and be positioned at the gate driver circuit of periphery, described viewing area, described gate driver circuit provides signal to described viewing area, and wherein, described gate driver circuit is driving circuit as above.
A kind of display device, described display device comprises array base palte as above.
Compared to prior art, technical scheme provided by the invention at least has the following advantages:
Driving circuit provided by the invention, array base palte and display device, the shift register group that driving circuit comprises at least one-level vitual stage shift register and is electrically connected in cascaded fashion with vitual stage shift register, this shift register group comprises first order shift register to N level shift register, due to vitual stage shift register take that chip area is less than i-th grade of shift register take chip area, therefore, relatively can reduce the frame area of display device, meet the narrow frame demand of display device.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
The structural representation of a kind of driving circuit that Fig. 1 provides for the embodiment of the present invention;
The structural representation of the another kind of driving circuit that Fig. 2 provides for the embodiment of the present invention;
The structural representation of another driving circuit that Fig. 3 provides for the embodiment of the present invention;
The structural representation of another driving circuit that Fig. 4 provides for the embodiment of the present invention;
The structural representation of a kind of array base palte that Fig. 5 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The one side of the embodiment of the present invention provides a kind of driving circuit, the shift register group that this driving circuit comprises at least one-level vitual stage shift register and is electrically connected in the mode of cascade with vitual stage shift register, wherein, this shift register group comprises first order shift register to N level shift register, and this N number of shift register is also be electrically connected in the mode of cascade.
In the present embodiment, vitual stage shift register is identical with the internal circuit configuration of i-th grade of shift register, its difference is only, vitual stage shift register in the present embodiment take that chip area is less than i-th grade of shift register take chip area, namely vitual stage shift register take that chip area is less than arbitrary grade of shift register take chip area, wherein, N be not less than 2 integer, i is the positive integer being not more than N.That is, take by what reduce vitual stage shift register the frame area that chip area reduces display device in the present invention.
As shown in Figure 1, a kind of structural representation of driving circuit that provides for the embodiment of the present invention of Fig. 1.In this driving circuit plane, vitual stage shift register and N number of shift register arrange along first direction Y, and vitual stage shift register is less than the length L2 of i-th grade of shift register along first direction Y along the length L1 of first direction Y, thus by reducing vitual stage shift register at the length L1 of first direction Y, reduce the length of frame on first direction Y of display device.
In another embodiment of the embodiment of the present invention, vitual stage shift register is less than or equal to the length L4 of i-th grade of shift register along second direction X along the length L3 of second direction X, wherein, first direction Y is vertical with second direction X, thus by reducing vitual stage shift register at the length L3 of second direction X, reduce the length of frame on second direction X of display device.
Or, in the another embodiment of the embodiment of the present invention, vitual stage shift register is less than the length L2 of i-th grade of shift register along first direction Y along the length L1 of first direction Y, simultaneously, this vitual stage shift register is less than or equal to the length L4 of i-th grade of shift register along second direction X along the length L3 of second direction X, wherein, first direction Y is vertical with second direction X, thus by reducing the length L1 of vitual stage shift register at first direction Y and the length L3 at second direction X, reduce the length of frame on first direction Y and second direction X of display device.
Optionally, in the present embodiment, vitual stage shift register take 0.6 ~ 0.8 times that takies chip area that chip area is i-th grade of shift register, comprise endpoint value.Concrete, vitual stage shift register is similar to the inner structure of shift register, all comprise some transistors, capacitance structure and connect above-mentioned transistor, the circuit of capacitance structure, because vitual stage shift register does not need the pixel to viewing area to provide effective drive singal, therefore, inner structure and the arrangement of vitual stage shift register appropriately adjust, such as, suitably can reduce the length of its internal transistor on first direction Y, or reduce the quantity of the transistor arranged along first direction Y, thus the length L1 of vitual stage shift register along first direction Y can be reduced, similarly, suitably can reduce the length of its internal transistor along second direction X, or reduce the quantity of the transistor along second direction X arrangement, thus the length L3 of vitual stage shift register along second direction X can be reduced.
In the present embodiment, as shown in Figure 1, because shift register arranges along first direction Y, when vitual stage shift register along first direction Y length L1 reduce time, effectively can reduce the frame area at driving circuit two ends, realize the narrow frame of display panel.
Further, in the present embodiment, inventor studies through many experiments, and result shows, when vitual stage shift register take chip area be i-th grade of shift register take 0.6 ~ 0.8 times of chip area time, said structure has good narrow frame effect.Concrete, when vitual stage shift register take chip area be less than i-th grade of shift register take 0.6 times of chip area time, the transistor size of vitual stage shift register inside is too little, be not enough to support the signal I/O in the vitual stage shift register required by driving circuit, and transistor arrangement is too tight, also make the mutual crosstalk of its internal wiring, hinder the normal operation of vitual stage shift register.And when vitual stage shift register take chip area be greater than i-th grade of shift register take 0.8 times of chip area time, vitual stage shift register takies chip area and reduces can not play expected effect for the narrow frameization of display panel.To sum up, when vitual stage shift register take chip area be i-th grade of shift register take 0.6 ~ 0.8 times of chip area time, said structure has good narrow frame effect.
Certainly, the present invention is not limited to this, in other embodiments, can carry out the setting of its area according to the concrete structure of vitual stage shift register.Particularly, can by reducing length and/or the width of vitual stage shift register in embodiments of the invention, what reduce vitual stage shift register takies chip area.
In addition, the driving circuit in the present embodiment can comprise primary virtual level shift register and first order vitual stage shift register.As shown in Figure 1, first order vitual stage shift register and the cascade of N level shift register, and cascade between adjacent two-stage shift register in first order shift register to N level shift register, such as, first order shift register and second level shift register cascade, second level shift register and the cascade of third level shift register.
Wherein, with the cascade of N level shift register, first order vitual stage shift register refers to that the output terminal OUT of first order vitual stage shift register is connected with the reset terminal RESET of N level shift register, the output terminal OUT of N level shift register is connected with the input end SET of first order vitual stage shift register, thus, N level shift register provides an input signal to first order vitual stage shift register, first order vitual stage shift register provides a reset signal to N level shift register, to reset the shift registers at different levels with the cascade of N level shift register, avoid the output of rub-out signal.
In another embodiment of the embodiment of the present invention, with reference to figure 2, the structural representation of the another kind of driving circuit that Fig. 2 provides for the embodiment of the present invention, wherein, driving circuit comprises two-stage vitual stage shift register, and this two-stage vitual stage shift register is respectively first order vitual stage shift register and second level vitual stage shift register.Wherein, cascade between first order vitual stage shift register and first order shift register, cascade between second level vitual stage shift register and N level shift register, and cascade between adjacent two-stage shift register in first order shift register to N level shift register, such as, first order shift register and second level shift register cascade, second level shift register and the cascade of third level shift register.
Wherein, first order vitual stage shift register and cascade between first order shift register refer to that the output terminal OUT of first order vitual stage shift register is connected with the input end SET of first order shift register, the output terminal OUT of first order shift register is connected with the reset terminal RESET of first order vitual stage shift register, thus, first order shift register provides an input signal to first order vitual stage shift register, first order vitual stage shift register provides a reset signal to first order shift register, so that when reverse scan, shift registers at different levels with the cascade of first order shift register are reset, avoid the output of rub-out signal, with cascade between N level shift register, second level vitual stage shift register refers to that the output terminal OUT of second level vitual stage shift register is connected with the reset terminal RESET of N level shift register, the output terminal OUT of N level shift register is connected with the input end SET of second level vitual stage shift register, thus, N level shift register provides an input signal to second level vitual stage shift register, second level vitual stage shift register provides a reset signal to N level shift register, so that when forward scan, shift registers at different levels with the cascade of N level shift register are reset, avoid the output of rub-out signal.
Or, with reference to figure 3, the structural representation of another driving circuit that Fig. 3 provides for the embodiment of the present invention, wherein, cascade between first order vitual stage shift register and N-1 level shift register, cascade between second level vitual stage shift register and N level shift register, and mutual cascade between adjacent two-stage shift register in all odd level shift registers in first order shift register to N level shift register, such as, first order shift register and the cascade of third level shift register, third level shift register and the cascade of level V shift register; And mutual cascade between adjacent two-stage shift register in all even level shift registers, such as, second level shift register and the cascade of fourth stage shift register, fourth stage shift register and the 6th grade of shift register cascade.
In like manner, with cascade between N-1 level shift register, first order vitual stage shift register refers to that the output terminal OUT of first order vitual stage shift register is connected with the reset terminal RESET of N-1 level shift register, the output terminal OUT of N-1 level shift register is connected with the input end SET of first order vitual stage shift register, with cascade between N level shift register, second level vitual stage shift register refers to that the output terminal OUT of second level vitual stage shift register is connected with the reset terminal RESET of N level shift register, the output terminal OUT of N level shift register is connected with the input end SET of second level vitual stage shift register, thus, N-1 level shift register provides an input signal to first order vitual stage shift register, first order vitual stage shift register provides a reset signal to N-1 level shift register, so that when forward scan, shift registers at different levels with the cascade of N-1 level shift register are reset, avoid the output of rub-out signal, similarly, N level shift register provides an input signal to second level vitual stage shift register, second level vitual stage shift register provides a reset signal to N level shift register, so that when forward scan, shift registers at different levels with the cascade of N level shift register are reset, avoids the output of rub-out signal.
In an embodiment again of the embodiment of the present invention, with reference to figure 4, the structural representation of another driving circuit that Fig. 4 provides for the embodiment of the present invention, wherein, driving circuit comprises level Four vitual stage shift register, and this level Four vitual stage shift register is respectively first order vitual stage shift register, second level vitual stage shift register, third level vitual stage shift register and fourth stage vitual stage shift register.Wherein, cascade between first order vitual stage shift register and first order shift register, cascade between second level vitual stage shift register and second level shift register, cascade between third level vitual stage shift register and N-1 level shift register, cascade between fourth stage vitual stage shift register and N level shift register, and mutual cascade between adjacent two-stage shift register in all odd level shift registers in first order shift register to N level shift register, and, mutual cascade between adjacent two-stage shift register in all even level shift registers.
In like manner, first order vitual stage shift register and cascade between first order shift register refer to that the output terminal OUT of first order vitual stage shift register is connected with the input end SET of first order shift register, and the output terminal OUT of first order shift register is connected with the reset terminal RESET of first order vitual stage shift register; Second level vitual stage shift register and cascade between the shift register of the second level refer to that the output terminal OUT of second level vitual stage shift register is connected with the input end SET of second level shift register, and the output terminal OUT of second level shift register is connected with the reset terminal RESET of second level vitual stage shift register; With cascade between N-1 level shift register, third level vitual stage shift register refers to that the output terminal OUT of third level vitual stage shift register is connected with the reset terminal RESET of N-1 level shift register, the output terminal OUT of N-1 level shift register is connected with the input end SET of third level vitual stage shift register; With cascade between N level shift register, fourth stage vitual stage shift register refers to that the output terminal OUT of fourth stage vitual stage shift register is connected with the reset terminal RESET of N level shift register, the output terminal OUT of N level shift register is connected with the input end SET of fourth stage vitual stage shift register.Thus, first order shift register provides an input signal to first order vitual stage shift register, first order vitual stage shift register provides a reset signal to first order shift register, so that when reverse scan, shift registers at different levels with the cascade of first order shift register are reset, avoids the output of rub-out signal; Similarly, second level shift register provides an input signal to second level vitual stage shift register, second level vitual stage shift register provides a reset signal to second level shift register, so that when reverse scan, shift registers at different levels with second level shift register cascade are reset, avoids the output of rub-out signal; N-1 level shift register provides an input signal to third level vitual stage shift register, third level vitual stage shift register provides a reset signal to N-1 level shift register, so that when forward scan, shift registers at different levels with the cascade of N-1 level shift register are reset, avoids the output of rub-out signal; N level shift register provides an input signal to fourth stage vitual stage shift register, fourth stage vitual stage shift register provides a reset signal to N level shift register, so that when forward scan, shift registers at different levels with the cascade of N level shift register are reset, avoids the output of rub-out signal.
It should be noted that, in the present embodiment, forward scan refers in shift register group, and signal is from first order shift register to the situation of N level shift register propagation; Reverse scan refers in shift register group, and signal is from N level shift register to the situation of first order shift register propagation.And when forward scan, the input end SET of above-mentioned shift register and vitual stage shift register is in order to receive input signal, and reset terminal RESET is in order to receive reset signal; When reverse scan, the reset terminal RESET of above-mentioned shift register and vitual stage shift register is in order to receive input signal, and input end SET is in order to receive reset signal.
In above-mentioned arbitrary embodiment, i-th grade of shift register and and the shift register of its cascade between annexation be: the output terminal OUT of i-th grade of shift register is connected with the input end SET of the shift register of its next stage cascade, the output terminal OUT of the shift register of next stage cascade is connected with the reset terminal RESET of i-th grade of shift register, simultaneously, the output terminal OUT of i-th grade of shift register is connected with the reset terminal RESET of the shift register of its upper level cascade, the output terminal OUT of the shift register of upper level cascade and i-th grade of shift register input end SET be connected.
In addition, vitual stage shift register in the present embodiment and first order shift register all pass through signal wire CK1 to the clock signal terminal CK of N level shift register and are connected with the clock signal output terminal of the driving chip of display device, and vitual stage shift register and first order shift register all pass through signal wire CKB to another clock signal terminal CKB of N level shift register and be connected with another clock signal output terminal of driving chip.
The driving circuit that the present embodiment provides, the shift register group comprising at least one-level vitual stage shift register and be electrically connected in cascaded fashion with vitual stage shift register, this shift register group comprises first order shift register to N level shift register, due to vitual stage shift register take that chip area is less than i-th grade of shift register take chip area, therefore, relatively can reduce the frame area of display device, meet the narrow frame demand of display device.
The another aspect of the embodiment of the present invention provides a kind of array base palte, is the structural representation of a kind of array base palte that the embodiment of the present invention provides with reference to figure 5, Fig. 5.As shown in Figure 5, this array base palte comprises viewing area 1 and is positioned at the frame region 2 of periphery, viewing area 1, frame region 2 has the gate driver circuit 3 providing signal to viewing area 1, the driving circuit that this gate driver circuit 3 provides for above-mentioned arbitrary embodiment.Particularly, gate driver circuit 3 provides signal by gate line 30 to pixel cell 4.
The another aspect of the embodiment of the present invention provides a kind of display device, and this display device comprises array base palte as above.
The array base palte that the embodiment of the present invention provides and display device, the shift register group that driving circuit wherein comprises at least one-level vitual stage shift register and is electrically connected in cascaded fashion with vitual stage shift register, this shift register group comprises first order shift register to N level shift register, due to vitual stage shift register take that chip area is less than i-th grade of shift register take chip area, therefore, relatively can reduce the frame area of display device, meet the narrow frame demand of display device.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a driving circuit, is characterized in that, comprising:
At least one-level vitual stage shift register;
And, the shift register group be electrically connected in cascaded fashion with described vitual stage shift register;
Wherein, described shift register group comprises first order shift register to N level shift register, and described vitual stage shift register take that chip area is less than described i-th grade of shift register take chip area, N be not less than 2 integer, i is the positive integer being not more than N.
2. driving circuit according to claim 1, it is characterized in that, in described driving circuit institute planar, described vitual stage shift register and described shift register arrange along first direction, and described vitual stage shift register is less than the length of described i-th grade of shift register along described first direction along the length of described first direction.
3. driving circuit according to claim 1, it is characterized in that, in described driving circuit institute planar, described vitual stage shift register and described shift register arrange along first direction, described vitual stage shift register is less than or equal to the length of described i-th grade of shift register along described second direction along the length of second direction, wherein, described first direction is vertical with described second direction.
4. driving circuit according to claim 1, is characterized in that, described vitual stage shift register take 0.6 ~ 0.8 times that takies chip area that chip area is described i-th grade of shift register, comprise endpoint value.
5. driving circuit according to claim 1, is characterized in that, described driving circuit comprises primary virtual level shift register, is first order vitual stage shift register;
Wherein, described first order vitual stage shift register and the cascade of described N level shift register, and cascade between adjacent two-stage shift register in described first order shift register to N level shift register.
6. driving circuit according to claim 1, is characterized in that, described driving circuit comprises two-stage vitual stage shift register, is respectively first order vitual stage shift register and second level vitual stage shift register;
Wherein, cascade between described first order vitual stage shift register and first order shift register, cascade between described second level vitual stage shift register and N level shift register, and cascade between adjacent two-stage shift register in described first order shift register to N level shift register.
7. driving circuit according to claim 1, is characterized in that, described driving circuit comprises two-stage vitual stage shift register, is respectively first order vitual stage shift register and second level vitual stage shift register;
Wherein, cascade between described first order vitual stage shift register and N-1 level shift register, cascade between described second level vitual stage shift register and N level shift register, and mutual cascade between adjacent two-stage shift register in all odd level shift registers in described first order shift register to N level shift register, and, mutual cascade between adjacent two-stage shift register in all even level shift registers.
8. driving circuit according to claim 1, it is characterized in that, described driving circuit comprises level Four vitual stage shift register, is respectively first order vitual stage shift register, second level vitual stage shift register, third level vitual stage shift register and fourth stage vitual stage shift register;
Wherein, cascade between described first order vitual stage shift register and first order shift register, cascade between described second level vitual stage shift register and second level shift register, cascade between described third level vitual stage shift register and N-1 level shift register, cascade between described fourth stage vitual stage shift register and N level shift register, and mutual cascade between adjacent two-stage shift register in all odd level shift registers in described first order shift register to N level shift register, and, mutual cascade between adjacent two-stage shift register in all even level shift registers.
9. an array base palte, comprise viewing area and be positioned at the gate driver circuit of periphery, described viewing area, described gate driver circuit provides signal to described viewing area, and wherein, described gate driver circuit is the driving circuit described in claim 1-8 any one.
10. a display device, is characterized in that, described display device comprises array base palte according to claim 9.
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| CN108615494A (en) * | 2016-12-13 | 2018-10-02 | 乐金显示有限公司 | Shift register and the gate drivers including shift register and display device |
| CN109147645A (en) * | 2018-10-18 | 2019-01-04 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109243399A (en) * | 2018-11-22 | 2019-01-18 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
| CN109507839A (en) * | 2018-12-27 | 2019-03-22 | 惠科股份有限公司 | Array substrate and display device |
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| CN104078024A (en) * | 2014-07-22 | 2014-10-01 | 友达光电股份有限公司 | Multiphase gate drive circuit and layout method thereof |
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| CN108615494A (en) * | 2016-12-13 | 2018-10-02 | 乐金显示有限公司 | Shift register and the gate drivers including shift register and display device |
| CN109147645A (en) * | 2018-10-18 | 2019-01-04 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109147645B (en) * | 2018-10-18 | 2021-10-22 | 武汉天马微电子有限公司 | A display panel and display device |
| CN113808517A (en) * | 2018-10-18 | 2021-12-17 | 武汉天马微电子有限公司 | Display panel and display device |
| CN113808517B (en) * | 2018-10-18 | 2023-08-08 | 武汉天马微电子有限公司 | Display panel and display device |
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| CN109507839A (en) * | 2018-12-27 | 2019-03-22 | 惠科股份有限公司 | Array substrate and display device |
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