CN105376964A - Multilayer circuit board expansion and shrinkage coefficient obtaining method and manufacturing method of multilayer circuit board - Google Patents
Multilayer circuit board expansion and shrinkage coefficient obtaining method and manufacturing method of multilayer circuit board Download PDFInfo
- Publication number
- CN105376964A CN105376964A CN201510885490.2A CN201510885490A CN105376964A CN 105376964 A CN105376964 A CN 105376964A CN 201510885490 A CN201510885490 A CN 201510885490A CN 105376964 A CN105376964 A CN 105376964A
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- Prior art keywords
- inner plating
- target
- circuit board
- multilayer circuit
- harmomegathus coefficient
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/061—Lamination of previously made multilayered subassemblies
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/162—Testing a finished product, e.g. heat cycle testing of solder joints
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a multilayer circuit board expansion and shrinkage coefficient obtaining method and a manufacturing method of a multilayer circuit board. The multilayer circuit board expansion and shrinkage coefficient obtaining method comprises the following steps: providing multiple inner plates to be pressed and an outer plate, adding more than three targets to the inner layers, and enabling the targets between the multiple inner layers to be arranged in a staggered mode; performing lamination processing on the multiple inner layers and the outer layer; obtaining target position information of the multiple inner plates through an X-Ray target drilling machine; and according to the target position information of the inner plates, obtaining an expansion and shrinkage coefficient b of the inner plates through calculation. According to the multilayer circuit board expansion and shrinkage coefficient obtaining method, the targets between each inner plate is arranged in a staggered mode, and after the targets between the inner plates are arranged in a staggered mode, the target position information of the N-2 inner layers can be simultaneously obtained through the X-Ray target drilling machine, such that the expansion and shrinkage coefficient of each inner plate can be obtained according to the target position information of each inner plate, and the alignment accuracy of line patterns between the inner plates can be improved.
Description
Technical field
The present invention relates to the manufacture technology field of multilayer circuit board plate, especially relate to a kind of harmomegathus coefficient acquisition methods of multilayer circuit board and the manufacture method of multilayer circuit board.
Background technology
The bonding processes of multilayer circuit board is also vacuumized the process controlling pressing plate by applying temperature of heat plate, moulding pressure, control duration, the prepreg between neighboring layer lines plate is made to be pressed into completely crued resin, and by bonding with Copper Foil for multiple internal substrate one-tenth one piece of multilayer circuit board, to ensure electric property and the mechanical performance of multilayer circuit board.The pressing plate mode of multilayer circuit board comprises MassLam (large-scale pressing-plate method) and PinLam (pin positioning pressuring plate method).Wherein, for conventional MassLam technique, can there is harmomegathus phenomenon in sheet material after the courses of processing such as HTHP.Therefore before pressing multilayer circuit board, generally need superimposed to multilayer circuit board after carry out pressure testing.Then obtain the pre-harmomegathus coefficient of each sandwich circuit board, then draw film graphic file according to pre-harmomegathus coefficient.The circuit that each sandwich circuit board is pressed into is made to have the dimensions identical with design like this.
Wherein, the pre-harmomegathus coefficient of each sandwich circuit board of the prior art obtains often by inquiry sheet material specification.So, for the multilayer circuit board of the number of plies higher (6 layers and more than), due to the difference such as the course of processing of the residual copper rate on sheet material kind, inner plating and sheet material, after the multilayer circuit board generation harmomegathus that MassLam technique obtains, the Aligning degree between each layer is restive in +/-4mil.
Summary of the invention
Based on this, the invention reside in the defect overcoming prior art, provide a kind of harmomegathus coefficient acquisition methods of multilayer circuit board, the manufacture method of multilayer circuit board, it can be convenient to the harmomegathus coefficient of each layer obtaining multi-layered board, can improve the Aligning degree between each layer.
Its technical scheme is as follows: a kind of multilayer circuit board harmomegathus coefficient acquisition methods, comprise the steps: to provide multiple inner plating to be laminated and lamina rara externa, described inner plating adds more than three targets, and the described target between multiple described inner plating is staggered setting; Multiple described inner plating and described lamina rara externa are carried out lamination treatment; The target position information on multiple described inner plating is obtained by X-Ray punch; The harmomegathus coefficient b of described inner plating is calculated according to the target position information on described inner plating.
The present invention also provides a kind of manufacture method of multilayer circuit board, and comprising the steps: provides multiple inner plating to be laminated and lamina rara externa, obtains the pre-harmomegathus coefficient a of described inner plating and described lamina rara externa according to sheet material kind; Make the line pattern of described inner plating according to described pre-harmomegathus coefficient a, wherein, described inner plating is provided with more than three targets, the setting and the described target between multiple described inner plating staggers; Multiple described inner plating and described lamina rara externa are carried out lamination treatment; Obtain the target position information on multiple described inner plating by X-Ray punch simultaneously; The actual harmomegathus coefficient b of described inner plating is calculated according to the target position information on described inner plating; Judge whether pre-harmomegathus coefficient a and actual harmomegathus coefficient b meets | a-b|≤0.2mil/inch; If met, then the laminated sheet obtained after described inner plating and described lamina rara externa pressing meets the requirements; If do not met, then the laminated sheet obtained after described inner plating and described lamina rara externa pressing is undesirable, and will make the line pattern of described inner plating according to described actual harmomegathus coefficient b.
Wherein in an embodiment, the target on described inner plating is four, four described target four drift angles at described inner plating in rectangular layout.
Wherein in an embodiment, the region that four described targets on inner plating described in any one surround is in the inside in the region that four described targets on inner plating described in its last layer surround, and/or four the described targets be on inner plating described in its lower one deck surround the outside in region.
Wherein in an embodiment, the described target upright projection on multiple described inner plating to described lamina rara externa after, the subpoint position of the described target on multiple described inner plating on lamina rara externa is on two straight lines arranged side by side.
Wherein in an embodiment, the described subpoint distance of positions of two described targets of the same drift angle of the described inner plating of arbitrary neighborhood layer is from S
1equal, and S
1be 5 ~ 10mm.
Wherein in an embodiment, the distance S of two described targets of inner side in two described straight lines arranged side by side
2be 200 ~ 300mm.
Wherein in an embodiment, described inner plating and described lamina rara externa are provided with two or more alignment target, the described alignment target one_to_one corresponding on the described alignment target on described inner plating and described lamina rara externa.
Wherein in an embodiment, described inner plating is provided with character, and described character is positioned at the periphery of described target, and the size of described character is the distance S of 1 ~ 15pt, described character and described target
3be 5 ~ 10mm.
Wherein in an embodiment, described target comprises copper sheet and is positioned at the annular slab of described copper sheet periphery, and the diameter R of described copper sheet is 1 ~ 2mm, and the ring width of described annular slab is 6 ~ 8mm.
Below in conjunction with technique scheme, principle of the present invention, effect are further illustrated:
1, above-mentioned multilayer circuit board harmomegathus coefficient acquisition methods, target between each inner plating to be staggered setting, after target between each inner plating staggers and arranges, just by X-Ray punch, the target position information on N-2 inner plating all can be got simultaneously, so then according to the harmomegathus coefficient of each inner plating of target position acquisition of information on each inner plating, the Aligning degree of the line pattern that can improve between each inner plating can be made.
2, be cross distribution relative to the target of four on inner plating in prior art, four rectangular distributions of target on inner plating of the present invention, make all have two groups of two targets in X-direction or Y-direction.After recognized four targets on inner plating by X-Ray punch, according in X-direction or Y-direction wherein one group of actual target position information of two targets carry out calculating with design target position information and just can draw a harmomegathus coefficient.So, just can obtain X-direction and each two the harmomegathus coefficients of Y-direction according to four of a distributed rectangular target, make the harmomegathus coefficient of inner plating more accurate.
3, after in the described target upright projection to lamina rara externa on N-2 inner plating, the subpoint position of the target on N-2 inner plating on lamina rara externa is on two straight lines arranged side by side.So, after the target of each inner plating being recognized by X-Ray punch, can be convenient to target corresponding with the inner plating of the corresponding number of plies, and be convenient to the harmomegathus coefficient calculating each laminate.
According to the harmomegathus coefficient of each inner plating got, the manufacture method of 4, above-mentioned multilayer circuit board, by after the harmomegathus coefficient that obtains each inner plating, then judges whether the pre-harmomegathus coefficient that pressing each inner plating front adopts meets code requirement.If judge that the pre-harmomegathus coefficient that inner plating adopts does not meet code requirement, then the harmomegathus coefficient of each inner plating obtained is used for the making of the line pattern of this inner plating follow-up.So visible, the manufacture method of multilayer circuit board of the present invention can improve the alignment precision of the line pattern between each inner plating, improves the product quality of Multi-layer force fit plate.
Accompanying drawing explanation
Fig. 1 is the structural representation that target on embodiment of the present invention N-2 inner plating projects to lamina rara externa;
Fig. 2 is the structural representation of target described in the embodiment of the present invention.
Description of reference numerals:
10, lamina rara externa, 11, alignment target, 12, character, 21, copper sheet, 22, annular slab, B
2, second layer target subpoint position, B
n-2, N-2 layer target subpoint position, B
n-1, N-1 layer target subpoint position.
Embodiment
Below embodiments of the invention are described in detail:
Multilayer circuit board harmomegathus coefficient acquisition methods of the present invention, comprises the steps:
There is provided N-2 inner plating to be laminated and lamina rara externa 10, four drift angles on each inner plating add target respectively, and the described target between each inner plating is staggered setting; Refer to Fig. 1, Fig. 1 target illustrated on N-2 inner plating projects to the structural representation on lamina rara externa 10, after target between each laminate staggers and arranges, just by X-Ray punch, the target position information on N-2 inner plating all can be got, so then can according to the harmomegathus coefficient of the target position acquisition of information inner plating on each inner plating simultaneously.
N-2 described inner plating and described lamina rara externa 10 are carried out lamination treatment; By MassLam technique of the prior art, inner plating and lamina rara externa 10 are carried out pressing and obtain multi-layer sheet.In pressing inner plating and lamina rara externa 10 process, because sheet material can exist harmomegathus phenomenon after the courses of processing such as HTHP.Therefore, the harmomegathus coefficient b obtaining sheet material harmomegathus change in lamination process by measuring process is below needed.
The target position information on N-2 described inner plating is obtained by X-Ray punch; Put into by multi-layer sheet in X-Ray punch, when X-Ray punch irradiates multi-layer sheet, the target due to each inner plating all staggers setting, does not have overlap.So, can the target position acquisition of information on N-2 described inner plating be arrived by X-Ray punch simultaneously.
The harmomegathus coefficient b of described inner plating is calculated according to the target position information on described inner plating.By the target position D on the inner plating that gets
2information, with the target position D preset on inner plating
1information, compares, by harmomegathus coefficient formulas
obtain harmomegathus coefficient b.
Above-mentioned multilayer circuit board harmomegathus coefficient acquisition methods, target between each inner plating to be staggered setting, after target between each inner plating staggers and arranges, just by X-Ray punch, the target position information on N-2 inner plating all can be got simultaneously, so then according to the harmomegathus coefficient of each inner plating of target position acquisition of information on each inner plating, the Aligning degree of the line pattern that can improve between each inner plating can be made.
Refer to Fig. 1, the target on described inner plating is four.Four described target four drift angles at described inner plating in rectangular layout.Be cross distribution relative to the target of four on inner plating in prior art, four rectangular distributions of target on inner plating of the present invention, make all have two groups of two targets in X-direction or Y-direction.After recognized four targets on inner plating by X-Ray punch, according in X-direction or Y-direction wherein one group of actual target position information of two targets carry out calculating with design target position information and just can draw a harmomegathus coefficient.So, just can obtain X-direction and each two the harmomegathus coefficients of Y-direction according to four of a distributed rectangular target, make the harmomegathus coefficient of inner plating more accurate.
The region that four described targets on inner plating described in any one surround is in the inside of four described targets on inner plating described in its last layer, and/or is in the outside in the region that four described targets on inner plating described in its lower one deck surround.Described target upright projection on N-2 described inner plating to described lamina rara externa 10 after, the subpoint position of described target on lamina rara externa 10 on N-2 described inner plating is on two straight lines arranged side by side and (illustrates four second layer target subpoint position B projected on lamina rara externa 10 in Fig. 1
2, four N-2 layer target subpoint position B
n-2and four N-1 layer target subpoint position B
n-1lay respectively on two dotted lines arranged side by side).So, after the target of each inner plating being recognized by X-Ray punch, can be convenient to target corresponding with the inner plating of the corresponding number of plies, and be convenient to the harmomegathus coefficient calculating each laminate.
The described subpoint distance of positions of two described targets of the same drift angle of the described inner plating of arbitrary neighborhood layer is from S
1equal, and S
1be 5 ~ 10mm.Article two, the distance S of two described targets of inner side in described straight line arranged side by side
2be 200 ~ 300mm.Described inner plating is provided with character 12.Described character 12 is positioned at the periphery of described target, and the size of described character 12 is 1 ~ 15pt, the distance S of described character 12 and described target
3be 5 ~ 10mm.Refer to Fig. 2, described target comprises copper sheet 21 and is positioned at the annular slab 22 of described copper sheet 21 periphery.The diameter R of described copper sheet 21 is 1 ~ 2mm, and the ring width of described annular slab 22 is 6 ~ 8mm.Setting like this, target is convenient to be recognized by X-Ray punch.
Described inner plating and described lamina rara externa 10 are provided with two or more alignment target 11.Described alignment target 11 on described inner plating and described alignment target 11 one_to_one corresponding on described lamina rara externa 10.Obtained the positional information of the alignment target 11 on inner plating and lamina rara externa 10 by X-Ray punch, after carrying out optical identification alignment target 11, can be convenient to inner plating together with lamina rara externa 10 contraposition.
The manufacture method of multilayer circuit board of the present invention, comprises the steps: to provide multiple inner plating to be laminated and lamina rara externa 10, obtains the pre-harmomegathus coefficient a of described inner plating and described lamina rara externa 10 according to sheet material kind; Make the line pattern of described inner plating according to described pre-harmomegathus coefficient a, wherein, described inner plating is provided with more than three targets, the setting and the described target between multiple described inner plating staggers; Multiple described inner plating and described lamina rara externa 10 are carried out lamination treatment; Obtain the target position information on multiple described inner plating by X-Ray punch simultaneously; The actual harmomegathus coefficient b of described inner plating is calculated according to the target position information on described inner plating; Judge whether pre-harmomegathus coefficient a and actual harmomegathus coefficient b meets | a-b|≤0.2mil/inch; If met, then the laminated sheet obtained after described inner plating and described lamina rara externa 10 pressing meets the requirements; If do not met, then the laminated sheet obtained after described inner plating and described lamina rara externa 10 pressing is undesirable, and will make the line pattern of described inner plating according to described actual harmomegathus coefficient b.
According to the harmomegathus coefficient of each inner plating got, the manufacture method of above-mentioned multilayer circuit board, by after the harmomegathus coefficient that obtains each inner plating, then judges whether the pre-harmomegathus coefficient that pressing each inner plating front adopts meets code requirement.If judge that the pre-harmomegathus coefficient that inner plating adopts does not meet code requirement, then the harmomegathus coefficient of each inner plating obtained is used for the making of the line pattern of this inner plating follow-up.So visible, the manufacture method of multilayer circuit board of the present invention can improve the alignment precision of the line pattern between each inner plating, improves the product quality of Multi-layer force fit plate.
Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this specification is recorded.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a multilayer circuit board harmomegathus coefficient acquisition methods, is characterized in that, comprise the steps:
Multiple inner plating to be laminated and lamina rara externa are provided, described inner plating adds more than three targets, and the described target between multiple described inner plating is staggered setting;
Multiple described inner plating and described lamina rara externa are carried out lamination treatment;
The target position information on multiple described inner plating is obtained by X-Ray punch;
The harmomegathus coefficient b of described inner plating is calculated according to the target position information on described inner plating.
2. multilayer circuit board harmomegathus coefficient acquisition methods according to claim 1, it is characterized in that, the target on described inner plating is four, four described target four drift angles at described inner plating in rectangular layout.
3. multilayer circuit board harmomegathus coefficient acquisition methods according to claim 2, it is characterized in that, the region that four described targets on inner plating described in any one surround is in the inside in the region that four described targets on inner plating described in its last layer surround, and/or four the described targets be on inner plating described in its lower one deck surround the outside in region.
4. multilayer circuit board harmomegathus coefficient acquisition methods according to claim 3, it is characterized in that, described target upright projection on multiple described inner plating to described lamina rara externa after, the subpoint position of the described target on multiple described inner plating on lamina rara externa is on two straight lines arranged side by side.
5. multilayer circuit board harmomegathus coefficient acquisition methods according to claim 4, is characterized in that, the described subpoint distance of positions of two described targets of the same drift angle of the described inner plating of arbitrary neighborhood layer is from S
1equal, and S
1be 5 ~ 10mm.
6. multilayer circuit board harmomegathus coefficient acquisition methods according to claim 4, is characterized in that, the distance S of two described targets of inner side in two described straight lines arranged side by side
2be 200 ~ 300mm.
7. multilayer circuit board harmomegathus coefficient acquisition methods according to claim 1, it is characterized in that, described inner plating and described lamina rara externa are provided with two or more alignment target, the described alignment target one_to_one corresponding on the described alignment target on described inner plating and described lamina rara externa.
8. multilayer circuit board harmomegathus coefficient acquisition methods according to claim 1, it is characterized in that, described inner plating is provided with character, and described character is positioned at the periphery of described target, and the size of described character is the distance S of 1 ~ 15pt, described character and described target
3be 5 ~ 10mm.
9. the multilayer circuit board harmomegathus coefficient acquisition methods according to any one of claim 1 to 8, it is characterized in that, described target comprises copper sheet and is positioned at the annular slab of described copper sheet periphery, and the diameter R of described copper sheet is 1 ~ 2mm, and the ring width D of described annular slab is 6 ~ 8mm.
10. a manufacture method for multilayer circuit board, is characterized in that, comprises the steps:
Multiple inner plating to be laminated and lamina rara externa are provided, obtain the pre-harmomegathus coefficient a of described inner plating and described lamina rara externa according to sheet material kind;
Make the line pattern of described inner plating according to described pre-harmomegathus coefficient a, wherein, described inner plating is provided with more than three targets, the setting and the described target between multiple described inner plating staggers;
Multiple described inner plating and described lamina rara externa are carried out lamination treatment;
Obtain the target position information on multiple described inner plating by X-Ray punch simultaneously;
The actual harmomegathus coefficient b of described inner plating is calculated according to the target position information on described inner plating;
Judge whether pre-harmomegathus coefficient a and actual harmomegathus coefficient b meets | a-b|≤0.2mil/inch;
If met, then the laminated sheet obtained after described inner plating and described lamina rara externa pressing meets the requirements;
If do not met, then the laminated sheet obtained after described inner plating and described lamina rara externa pressing is undesirable, and will make the line pattern of described inner plating according to described actual harmomegathus coefficient b.
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|---|---|---|---|
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|---|---|---|---|
| CN201510885490.2A CN105376964B (en) | 2015-12-03 | 2015-12-03 | A kind of production method of multilayer circuit board harmomegathus coefficient acquisition methods, multilayer circuit board |
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| CN105376964B CN105376964B (en) | 2018-09-07 |
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Cited By (5)
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| CN106793586A (en) * | 2016-12-08 | 2017-05-31 | 生益电子股份有限公司 | How to use the adhesive sheet |
| CN109600941A (en) * | 2019-01-28 | 2019-04-09 | 鹤山市世安电子科技有限公司 | A kind of PCB multilayer circuit board interlayer change in size measurement method |
| CN109922602A (en) * | 2019-04-02 | 2019-06-21 | 博敏电子股份有限公司 | A kind of Anylayer plate Multifunction target mark mistake proofing design method |
| CN113498276A (en) * | 2021-07-16 | 2021-10-12 | 丰顺县锦顺科技有限公司 | Control method of printed circuit board production equipment and printed circuit board production equipment |
| CN115348737A (en) * | 2022-08-12 | 2022-11-15 | 江苏迪飞达电子有限公司 | Preparation method of double-sided thick copper-aluminum-based mixed pressing plate |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106793586A (en) * | 2016-12-08 | 2017-05-31 | 生益电子股份有限公司 | How to use the adhesive sheet |
| CN109600941A (en) * | 2019-01-28 | 2019-04-09 | 鹤山市世安电子科技有限公司 | A kind of PCB multilayer circuit board interlayer change in size measurement method |
| CN109922602A (en) * | 2019-04-02 | 2019-06-21 | 博敏电子股份有限公司 | A kind of Anylayer plate Multifunction target mark mistake proofing design method |
| CN109922602B (en) * | 2019-04-02 | 2021-09-14 | 博敏电子股份有限公司 | Multi-functional target error-proofing design method for Analyyer plate |
| CN113498276A (en) * | 2021-07-16 | 2021-10-12 | 丰顺县锦顺科技有限公司 | Control method of printed circuit board production equipment and printed circuit board production equipment |
| CN113498276B (en) * | 2021-07-16 | 2022-07-12 | 丰顺县锦顺科技有限公司 | Control method of printed circuit board production equipment and printed circuit board production equipment |
| CN115348737A (en) * | 2022-08-12 | 2022-11-15 | 江苏迪飞达电子有限公司 | Preparation method of double-sided thick copper-aluminum-based mixed pressing plate |
| CN115348737B (en) * | 2022-08-12 | 2023-09-26 | 江苏迪飞达电子有限公司 | Preparation method of double-sided thick copper-aluminum-based mixed pressing plate |
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|---|---|
| CN105376964B (en) | 2018-09-07 |
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