CN105374390B - Static RAM, Static RAM storage unit and its layout - Google Patents
Static RAM, Static RAM storage unit and its layout Download PDFInfo
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- CN105374390B CN105374390B CN201410439751.3A CN201410439751A CN105374390B CN 105374390 B CN105374390 B CN 105374390B CN 201410439751 A CN201410439751 A CN 201410439751A CN 105374390 B CN105374390 B CN 105374390B
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Abstract
A kind of Static RAM, Static RAM storage unit and its layout.Wherein, the Static RAM storage unit, including being made on substrate：First driving transistor, the first load transistor, the second driving transistor and the second load transistor；The channel length of first driving transistor and the second driving transistor is located at first direction, and the first direction is parallel to the substrate (001) crystal face；The channel length of first load transistor and the second load transistor is located at second direction, and the second direction is parallel to the substrate (001) crystal face；In the first direction and the second direction, at least one direction and the angle of the substrate (100) crystal face are 0 °~22 °.The Static RAM storage unit performance improves.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of Static RAM, Static RAM to deposit
Storage unit and its layout.
Background technology
The prior art is in semiconductor storage unit, Static RAM (SRAM) device and dynamic random access memory
Device (DRAM) device, which is compared, has the advantages that lower power consumption and faster operating rate.Static RAM can be held very much again
It changes places and physical unit positioning is carried out by bitmap test equipment, study the actual effect pattern of product.
The storage unit of Static RAM can be divided into ohmic load Static RAM storage unit and complementation
Metal-oxide semiconductor (MOS) (CMOS) Static RAM storage unit.Ohmic load static random access memory cell is using high
The resistance of resistance value is as load device, and CMOS static random-access memory unit is using P-channel gold
Belong to oxide semiconductor (PMOS) transistor as load device.In CMOS static random access memory packet
Containing multiple NMOS transistors and PMOS transistor.
The performance of existing CMOS static random access memory is bad.
Invention content
The present invention solves the problems, such as to be to provide a kind of Static RAM, Static RAM storage unit and its cloth
Office, to improve the performance of Static RAM storage unit, and improves the performance of Static RAM simultaneously.
To solve the above problems, the present invention provides a kind of Static RAM storage unit, including being made on substrate
's：
First driving transistor, the first load transistor, the second driving transistor and the second load transistor；
The channel length of first driving transistor and the second driving transistor is located at first direction, the first direction
It is parallel to the substrate (001) crystal face；
The channel length of first load transistor and the second load transistor is located at second direction, the second direction
It is parallel to the substrate (001) crystal face；
In the first direction and the second direction, at least one direction and the angle of the substrate (100) crystal face are
0 °~22 °.
Optionally, in the first direction and the second direction, at least one direction and the substrate (100) crystal face
Angle is 0 °.
Optionally, the first direction is parallel with the second direction.
Optionally, first driving transistor, the first load transistor, the second driving transistor and the second load crystal
Pipe is located in rectangular area.
Optionally, first driving transistor, the first load transistor, the second driving transistor and the second load crystal
Pipe is fin formula field effect transistor.
Optionally, the gate vertical of first driving transistor is across the fin of first driving transistor；It is described
The gate vertical of second driving transistor is across the fin of second driving transistor；The grid of first load transistor
Vertically across the fin of first load transistor；The gate vertical of second load transistor is across the described second load
The fin of transistor.
Optionally, the grid of first driving transistor is connect with the grid of first load transistor；Described
The grid of two driving transistors is connect with the grid of second load transistor.
To solve the above problems, the present invention also provides a kind of Static RAM memory cell layout, including making
In on substrate：
First protrusion, the second protrusion, third protrusion and the 4th protrusion, second protrusion and the 4th protrusion are located at described the
Between one protrusion and third protrusion, second protrusion is located between the described first protrusion and the 4th protrusion；
First protrusion includes the first fin, and the length of first fin is located at first direction, the first direction
It is parallel to the substrate (001) crystal face；
Second protrusion includes the second fin, and the length of second fin is located at second direction, the second direction
It is parallel to the substrate (001) crystal face；
The third protrusion includes third fin, and the length of the third fin is located at the first direction；
4th protrusion includes the 4th fin, and the length of the 4th fin is located at the second direction；
In the first direction and the second direction, at least one direction and the angle of the substrate (100) crystal face are
0 °~22 °.
Optionally, in the first direction and the second direction, at least one direction and the substrate (100) crystal face
Angle is 0 °.
Optionally, the first direction is parallel with the second direction.
Optionally, it further includes：First grid, second grid, third grid and the 4th grid；The first grid is vertically horizontal
Across first fin, the second grid is vertically across second fin, and the third gate vertical is across the third
Fin, the 4th gate vertical is across the 4th fin.
Optionally, first fin, the second fin, third fin, the 4th fin, first grid, second grid, third
Grid and the 4th grid are located in rectangular area.
Optionally, the first grid is connect with the second grid；The third grid is connect with the 4th grid.
To solve the above problems, the present invention also provides a kind of Static RAM, have and make on substrate more
A static random access memory cell, a plurality of wordline, multiple bit lines；Each Static RAM storage unit, including：
First phase inverter has the first driving transistor and the first load transistor；
Second phase inverter has the second driving transistor and the second load transistor；
The output terminal of first phase inverter is connected to the input terminal of second phase inverter；
The input terminal of first phase inverter is connected to the output terminal of second phase inverter；
The channel length of first driving transistor and the second driving transistor is respectively positioned on first direction, the first party
To being parallel to the substrate (001) crystal face；
The channel length of first load transistor and the second load transistor is respectively positioned on second direction, the second party
To being parallel to the substrate (001) crystal face；
In the first direction and the second direction, at least one direction and the angle of the substrate (100) crystal face are
0 °~22 °.
Optionally, in the first direction and the second direction, at least one direction and the substrate (100) crystal face
Angle is 0 °.
Optionally, the first direction is parallel with the second direction.
Optionally, the Static RAM further includes：
First transmission transistor is connected between the output terminal of the bit line and first phase inverter, and described
One transfer transistor gate is connect with the wordline；
Second transmission transistor is connected between the output terminal of the bit line and second phase inverter, and described
Two transfer transistor gates are connect with the wordline；
The channel length of first transmission transistor and the channel length of the second transmission transistor are respectively positioned on third direction,
The third direction is parallel to (001) crystal face, and the third direction is parallel to the substrate (110) crystal face.
Optionally, first driving transistor, the first load transistor, the second driving transistor, the second load crystal
Pipe, the first transmission transistor and the second transmission transistor are located in rectangular area, and the third direction is parallel to the rectangle region
The wherein one side in domain.
Optionally, first driving transistor, the first load transistor, the second driving transistor, the second load crystal
Pipe, the first transmission transistor and the second transmission transistor are fin formula field effect transistor.
Optionally, the grid of first driving transistor is connect with the grid of first load transistor；Described
The grid of two driving transistors is connect with the grid of second load transistor.
Compared with prior art, technical scheme of the present invention has the following advantages：
In technical scheme of the present invention, the channel length of the first driving transistor and the second driving transistor is respectively positioned on first
Direction, the first direction are parallel to the substrate (001) crystal face, first load transistor and the second load transistor
Channel length is respectively positioned on second direction, and the second direction is parallel to the substrate (001) crystal face.And the first direction and
In the second direction, at least one direction and the angle of the substrate (100) crystal face are 0 °~22 °.Meet following two at this time
At least one of a condition：
The angle of condition one, first direction and the substrate (100) crystal face is 0 °, the electric current driving of the first driving transistor
Ability and the ratio β of the current driving ability of the first biography elm transistor can be improved to 1.05:More than 1, similarly second drive crystal
The ratio β of the current driving ability of the current driving ability of pipe and the second biography elm transistor can be improved to 1.05:More than 1, it is static
The stability of random-access memory unit improves, and corresponding Static RAM stability improves, Static RAM
Read noise tolerance improve；
The angle of condition two, second direction and the substrate (100) crystal face is 0 °, and first passes the electric current driving of elm transistor
Ability and the ratio γ of the current driving ability of the first load transistor can be improved to 1.2:More than 1, similarly second pass elm crystal
The ratio γ of the current driving ability of the current driving ability of pipe and the second load transistor can be improved to 1.2:More than 1, it is static
The stability of random-access memory unit improves, and corresponding Static RAM stability improves, Static RAM
Write noise margin raising.
Description of the drawings
Fig. 1 is the floor map of existing Static RAM；
Fig. 2 is the circuit diagram of existing Static RAM；
Fig. 3 is the floor map of wafer；
Fig. 4 is that the channel region length of NMOS transistor and PMOS transistor is respectively parallel to substrate (110) crystal face and (100)
Equivalent mobility curve figure during crystal face；
Fig. 5 is the Static RAM floor map that one embodiment of the invention is provided；
Fig. 6 is the Static RAM floor map that further embodiment of this invention is provided；
Fig. 7 to Fig. 8 is the Static RAM plane figure schematic diagram that further embodiment of this invention is provided；
Fig. 9 to Figure 10 is the Static RAM plane figure schematic diagram that further embodiment of this invention is provided.
Specific embodiment
As described in background, the performance of existing Static RAM is bad.Existing Static RAM is put down
Face layout is as shown in Figure 1.It includes six transistors (not marking), and plane figure shown in Fig. 1 shows six transistors
Active area (not marking) and grid.Usual Static RAM storage unit includes the first driving transistor, the first load
Transistor, the second driving transistor and the second load transistor, as shown in Figure 1 Static RAM storage unit be located at rectangle
Dotted line frame institute enclosing region.
It should be strongly noted that it is clear for mark, it, will when marking each grid in each attached drawing of this specification
Lead is drawn from one of position of grid layer.It should be appreciated to those skilled in the art that positioned at different active regions
Grid layer for different grids, i.e., each grid is actually a portion of grid layer.Such as in Fig. 1, grid D11 and grid
U11 belongs to same grid layer (not marking), in the grid layer, is positioned at the part of the first driving transistor active region
Grid D11 is grid U11 positioned at the part of the first load transistor active region.And it follows that grid D11 with
Grid U11 connections.
The grid G 11 of first transmission transistor is connect with bit line WL11, and 11 lower section of grid G is the ditch of the first transmission transistor
Road area.The grid G 11 of first transmission transistor is connect with wordline WL11, and source electrode and the interconnection line H11 of the first transmission transistor connect
It connects, the drain electrode of the first transmission transistor is connect with bit line B11.
The grid G 12 of second transmission transistor is connect with bit line WL12, and 12 lower section of grid G is the ditch of the second transmission transistor
Road area.The grid G 12 of second transmission transistor is connect with wordline WL12, and source electrode and the interconnection line H12 of the second transmission transistor connect
It connects, the drain electrode of the second transmission transistor is connect with bit line B12.
The grid D11 of first driving transistor (driving transistor is also referred to as pull-down transistor) and the first load transistor are (negative
Carry transistor be also referred to as pulls up transistor) grid U11 connections.The source electrode of first driving transistor and the ground wire in ground level
Vss connections, the source electrode of the first load transistor are connect with power voltage line Vdd, the drain electrode of the first driving transistor and interconnection line
H11 connections, therefore the source electrode of the first transmission transistor is electrically connected with the drain electrode of the first driving transistor.
The grid D12 of second driving transistor is connect with the grid U12 of the second load transistor.Second driving transistor
Source electrode is connect with the ground wire Vss in ground level, and the source electrode of the second load transistor is connect with power voltage line Vdd, and second
The drain electrode of driving transistor is connect with interconnection line H12, therefore the leakage of the source electrode of the second transmission transistor and the second driving transistor
Pole is electrically connected.
It please refers to Fig.2, Fig. 2 is the circuit diagram of Static RAM shown in Fig. 1, and specific connection mode can refer to Fig. 1
The content.
It please refers to Fig.3, Fig. 3 shows wafer 10.Wafer 10 has upper surface 10A, and subsequent semiconductor devices makes
On the 10A of upper surface.The upper surface 10A of wafer 10 is typically parallel to (001) crystal face.When the alignment notch along wafer 10 (is not shown
Go out) and the center of circle and during perpendicular to upper surface 10A cutting wafers 10, obtained cutting plane is parallel to (110) crystal face, i.e. in Fig. 3, edge
Dotted line 11 and after upper surface 10A cuttings wafer 10, obtained section is parallel to (110) crystal face.That is, (110)
Crystal face is projected as dotted line 11 on the 10A of upper surface.Similarly, after along dotted line 12 and perpendicular to upper surface 10A cuttings wafer 10,
Obtained section is parallel to (100) crystal face, i.e. (100) crystal face is projected as dotted line 12, and dotted line in 10 upper surface 10A of wafer
Angle between 11 and dotted line 12 is 45 °, i.e., (110) crystal face and (100) crystal face are 45 ° in the angle of the projection of upper surface 10A.
It please refers to Fig.4, in TCAD (semiconductor process simulation and device simulation tool), has obtained NMOS transistor
When the channel length of PMOS transistor is parallel to different crystal faces, different effective mobilities that (raceway groove) reverse-biased layer carrier is shown
(effective mobility).Wherein, what curve where filled circles represented is that PMOS transistor channel length is parallel to (110)
Effective mobility is distributed during crystal face, and what curve represented where open circles is that PMOS transistor channel length is parallel to (100) crystal face
When effective mobility be distributed, when what curve where closed square represented is that NMOS transistor channel length is parallel to (110) crystal face
Effective mobility is distributed, and what curve represented where hollow square is that NMOS transistor channel length has when being parallel to (100) crystal face
Imitate mobility distribution.
It can be seen from figure 4 that effective mobility when NMOS transistor channel length is parallel to (100) crystal face is higher than
NMOS transistor channel length is parallel to effective mobility during (110) crystal face, and the ratio of former and later two effective mobilities
About 1.1:1.It is long that effective mobility when PMOS transistor channel length is parallel to (100) crystal face is less than PMOS transistor raceway groove
Degree is parallel to effective mobility during (110) crystal face, and the ratio of former and later two effective mobilities is about 1:1.4.
With reference to Fig. 3 and Fig. 4 content it can be appreciated that in the prior art, generally select the channel length for enabling whole transistors
It is parallel to (110) crystal face：Because at this point, although the effective mobility of NMOS transistor is relatively low (is parallel to (110) than channel length
During crystal face it is low about 10%), but the effective mobility of PMOS transistor improve a lot (than channel length be parallel to (110) crystalline substance
It is improved about 40%) during face, therefore, for entire semiconductor circuit, performance is optimized.
In summary, in existing Static RAM, the channel length of each transistor is respectively positioned on parallel (110) crystal face
In direction, i.e. Fig. 1, (110) crystal face is oriented parallel to perpendicular to grid G 11, in other words, each transistor channel length in Fig. 1
Direction is each parallel to (110) crystal face.
However, for Static RAM, when the channel length of each transistor is entirely located in parallel (110) crystal face
Direction when, performance is bad.
Originally, the stability of Static RAM storage unit was brilliant with passing elm by the current driving ability of driving transistor
The ratio β of the current driving ability of body pipe and the electric current of current driving ability and load transistor for passing elm transistor drive
The ratio γ of ability is determined.By increasing the value of ratio β and ratio γ, the steady of Static RAM storage unit can be increased
Determine coefficient.
In order to which the coefficient of stability for making Static RAM storage unit reaches necessary requirement, it usually needs ensure ratio β
Value be more than or equal to 1.05:The value of 1 or ratio γ is more than or equal to 1.2:1.
However when the channel length of each transistor is entirely located in the direction of parallel (110) crystal face, it is clear that ratio β and ratio
The value of γ is 1:1, at this time the coefficient of stability of Static RAM storage unit be unable to reach necessary requirement.
For this purpose, the embodiment of the present invention provides a kind of Static RAM storage unit, including be made on substrate the
One driving transistor, the first load transistor, the second driving transistor and the second load transistor；First driving transistor
It is located at first direction with the channel length of the second driving transistor, the first direction is parallel to the substrate (001) crystal face；Institute
The channel length for stating the first load transistor and the second load transistor is located at second direction, and the second direction is parallel to described
Substrate (001) crystal face；In the first direction and the second direction, at least one direction and the substrate (100) crystal face
Angle is 0 °~22 °.
Usually in the prior art, first direction and second direction and the angle of the substrate (100) crystal face are 45 °, this
When the value of ratio β and the value of ratio γ be 1:1.But in the present invention, in first direction and the second direction, at least one side
It it is 0 °~22 ° to the angle with the substrate (100) crystal face, so as to reach at least one of following two conditions：Condition one,
The value of ratio β is more than or equal to 1.05:1；Condition two, the value of ratio γ are more than or equal to 1.2:1.Static random is deposited at this time
The coefficient of stability of reservoir storage unit reaches necessary requirement, and Static RAM performance improves.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
One embodiment of the invention provides a kind of Static RAM.
Fig. 5 is please referred to, there are the Static RAM the multiple static randoms being produced on substrate (not shown) to deposit
Storage unit, a plurality of wordline and multiple bit lines.The substrate is silicon monocrystalline substrate, is specifically as follows Silicon Wafer.On the substrate
Surface is (001) crystal face of silicon single crystal, i.e., plane shown in fig. 5 is parallel to (001) crystal face of the substrate, and perpendicular in Fig. 5
Straight dotted line (not marking) is the projection of the substrate (110) crystal face plane shown in Fig. 5.
Fig. 5 shows one of Static RAM storage unit and its periphery of this implementation Static RAM
Circuit structure.The Static RAM storage unit includes the first driving transistor being made on above-mentioned substrate (not
Mark), the first load transistor (not marking), the second driving transistor (not marking) and the second load transistor (not marking).
The source electrode of first driving transistor is connect with the ground wire Vss in ground level.The drain electrode of first driving transistor and interconnection line
H21 connections.The source electrode of second driving transistor is connect with the ground wire Vss in ground level.The drain electrode of second driving transistor
It is connect with interconnection line H22.The source electrode of first load transistor is connect with power voltage line Vdd.The drain electrode of first load transistor
It is connect with interconnection line H21.The source electrode of second load transistor is connect with power voltage line Vdd.The drain electrode of second load transistor
It is connect with interconnection line H22.
As shown in Figure 5, the Static RAM that the present embodiment is provided includes the first phase inverter (not marking) and second
Phase inverter (does not mark).First phase inverter includes the first driving transistor and the first load transistor.Second phase inverter includes the
Two driving transistors and the second load transistor.The output terminal of first phase inverter is connected to the second phase inverter by interconnection line H21
Input terminal.The input terminal of first phase inverter is connected to the output terminal of the second phase inverter by interconnection line H22.
The Static RAM that the present embodiment is provided further includes the first transmission transistor (not marking) and the second transmission
Transistor (does not mark).First transmission transistor is connected between the output terminal of bit line and the first phase inverter, and the first transmission
Transistor gate is connect with wordline.Second transmission transistor is connected between the output terminal of bit line and the second phase inverter, and the
Two transfer transistor gates are connect with wordline.
Specifically as shown in figure 5,21 lower section of grid G of the first transmission transistor is the channel region of the first transmission transistor.The
The grid G 21 of one transmission transistor is connect with wordline WL21.The source electrode of first transmission transistor is connect with interconnection line H21.First
The drain electrode of transmission transistor is connect with bit line B21.22 lower section of grid G of second transmission transistor is the ditch of the second transmission transistor
Road area.The grid G 22 of second transmission transistor is connect with wordline WL22.The source electrode of second transmission transistor connects with interconnection line H22
It connects.The drain electrode of second transmission transistor is connect with bit line B22.The leakage of the source electrode of first transmission transistor and the first driving transistor
Pole is electrically connected.The source electrode of second transmission transistor is electrically connected with the drain electrode of the second driving transistor.The grid of second driving transistor
Pole D22 is connect with the grid U22 of the second load transistor, and the two connection wordline W22, and wordline W22 connection interconnection lines
H21.The grid D21 of first driving transistor is connect with the grid U21 of the first load transistor, and the two connection wordline W21,
And wordline W21 connection interconnection lines H22.
In the present embodiment, the first driving transistor, the first load transistor, the second driving transistor, the second load crystal
Pipe, the first transmission transistor and the second transmission transistor are fin formula field effect transistor.And the first load transistor and
Two load transistors can be PMOS transistor, and the first driving transistor, the second driving transistor, the first transmission transistor and
Second transmission transistor can be NMOS transistor.The equivalent circuit diagram for the Static RAM that the present embodiment is provided can join
Examine Fig. 2.
Please continue to refer to Fig. 5, in the present embodiment, the grid D21 of the first driving transistor is vertically across the first driving crystal
The fin (not marking) of pipe.The grid D22 of second driving transistor (is not marked) vertically across the fin of the second driving transistor.
The grid U21 of first load transistor (is not marked) vertically across the fin of the first load transistor.Second load transistor
Grid U22 (is not marked) vertically across the fin of the second load transistor.The grid G 21 of first transmission transistor is vertically across
The fin (not marking) of one transmission transistor.The grid G 22 of second transmission transistor is vertically across the fin of the second transmission transistor
Portion (does not mark).
Please continue to refer to Fig. 5, in the present embodiment, the first driving transistor, the first load transistor, the second driving crystal
Pipe, the second load transistor, the first transmission transistor and the second transmission transistor are located at rectangular broken line frame (not marking) institute in Fig. 5
In the rectangular area shown, third direction DR3 is parallel to wherein one side of rectangular area.
Please continue to refer to Fig. 5, the projection in substrate (110) crystal face plane shown in Fig. 5 is as shown in vertical dotted line.The
The channel length of one driving transistor and the second driving transistor is respectively positioned on first direction DR1, first direction DR1 and is parallel to described
Substrate (001) crystal face, and the angle theta of first direction DR1 and the substrate (110) crystal face is 45 °.It is found that first party at this time
It it is 0 ° to the angle (not shown) of DR1 and the substrate (100) crystal face.
Since the angle theta of first direction DR1 and the substrate (100) crystal face is 0 °, the electricity of the first driving transistor
Stream driving force and the ratio β of the current driving ability of the first biography elm transistor can be improved to 1.1:1.Likewise, the second driving
The ratio β of the current driving ability of the current driving ability of transistor and the second biography elm transistor can be improved to 1.1:1.It is and entire
The performance of static random access memory cell is codetermined by two phase inverters, in two phase inverters ratio β improve to
1.1:When 1, the performance of static random access memory cell significantly improves, and corresponding Static RAM stability improves, tool
The read noise tolerance (read noise margin) that body shows as Static RAM significantly improves.
In addition, in the present embodiment, compared with the prior art for, the channel length direction of the first driving transistor is (i.e.
First direction DR1) it is rotated, the grid D21 of the first driving transistor is caused correspondingly to rotate, the first driving crystal
It rotates to the partial response that the grid D21 of pipe is connect with the grid U21 of the first load transistor, so as to ensure grid U21
Still it is parallel with the grid G of the first transmission transistor 21.Similarly, the channel length direction (i.e. of the second driving transistor
One direction DR1) it is rotated, the grid D22 of the second driving transistor is caused correspondingly to rotate, the second driving transistor
The partial responses that are connect with the grid U22 of the second load transistor of grid D22 rotate, so as to ensure grid U22 still
It is so parallel with the grid G of the second transmission transistor 22.But such rotation does not increase entire Static RAM storage
The area of plane of unit does not increase the making space (area) of Static RAM.And entire Static RAM
The area of plane of storage unit is still limited in the rectangular area similar with Fig. 1, and it is single to maintain Static RAM storage
The dense degree and regularity of member arrangement.
Please continue to refer to Fig. 5, the equal position of channel length of the channel length of the first transmission transistor and the second transmission transistor
In third direction DR3, third direction DR3 is parallel to (001) crystal face, and third direction DR3 is parallel to the substrate (110) crystalline substance
Face.
It should be noted that in other embodiments of the invention, first direction DR1 and the substrate (100) crystal face
Angle can be other angles between 0 °~22 ° in addition to 0 °, at this point, ratio β is located at 1.05 accordingly:1~1.1:
Between 1, still meet the corresponding Static RAM storage unit coefficient of stability and still meet requirement.
Further embodiment of this invention provides another Static RAM.
Fig. 6 is please referred to, there are the Static RAM the multiple static randoms being produced on substrate (not shown) to deposit
Storage unit, a plurality of wordline and multiple bit lines.The substrate is silicon monocrystalline substrate, is specifically as follows Silicon Wafer.On the substrate
Surface is (001) crystal face of silicon single crystal, i.e., plane shown in fig. 6 is parallel to (001) crystal face of the substrate, and two in Fig. 6
The vertical dotted line of item (not marking) is the projection of the substrate (110) crystal face plane shown in Fig. 6.
Fig. 6 shows one of Static RAM storage unit and its periphery of this implementation Static RAM
Circuit structure.The Static RAM storage unit includes the first driving transistor being made on above-mentioned substrate (not
Mark), the first load transistor (not marking), the second driving transistor (not marking) and the second load transistor (not marking).
The source electrode of first driving transistor is connect with the ground wire Vss in ground level.The drain electrode of first driving transistor and interconnection line
H31 connections.The source electrode of second driving transistor is connect with the ground wire Vss in ground level.The drain electrode of second driving transistor
It is connect with interconnection line H32.The source electrode of first load transistor is connect with power voltage line Vdd.The drain electrode of first load transistor
It is connect with interconnection line H31.The source electrode of second load transistor is connect with power voltage line Vdd.The drain electrode of second load transistor
It is connect with interconnection line H32.
It will be appreciated from fig. 6 that the Static RAM that the present embodiment is provided includes the first phase inverter (not marking) and second
Phase inverter (does not mark).First phase inverter includes the first driving transistor and the first load transistor.Second phase inverter includes the
Two driving transistors and the second load transistor.The output terminal of first phase inverter is connected to the second phase inverter by interconnection line H31
Input terminal.The input terminal of first phase inverter is connected to the output terminal of the second phase inverter by interconnection line H32.
The Static RAM that the present embodiment is provided further includes the first transmission transistor (not marking) and the second transmission
Transistor (does not mark).First transmission transistor is connected between the output terminal of bit line and the first phase inverter, and the first transmission
Transistor gate is connect with wordline.Second transmission transistor is connected between the output terminal of bit line and the second phase inverter, and the
Two transfer transistor gates are connect with wordline.
Specifically as shown in fig. 6,31 lower section of grid G of the first transmission transistor is the channel region of the first transmission transistor.The
The grid G 31 of one transmission transistor is connect with wordline WL31.The source electrode of first transmission transistor is connect with interconnection line H31.First
The drain electrode of transmission transistor is connect with bit line B31.32 lower section of grid G of second transmission transistor is the ditch of the second transmission transistor
Road area.The grid G 32 of second transmission transistor is connect with wordline WL32.The source electrode of second transmission transistor connects with interconnection line H32
It connects.The drain electrode of second transmission transistor is connect with bit line B32.The leakage of the source electrode of first transmission transistor and the first driving transistor
Pole is electrically connected.The source electrode of second transmission transistor is electrically connected with the drain electrode of the second driving transistor.The grid of second driving transistor
Pole D32 is connect with the grid U32 of the second load transistor, and the two connection wordline W32, and wordline W32 connection interconnection lines
H31.The grid D31 of first driving transistor is connect with the grid U31 of the first load transistor, and the two connection wordline W31,
And wordline W31 connection interconnection lines H32.
In the present embodiment, the first driving transistor, the first load transistor, the second driving transistor, the second load crystal
Pipe, the first transmission transistor and the second transmission transistor are fin formula field effect transistor.And the first load transistor and
Two load transistors can be PMOS transistor, and the first driving transistor, the second driving transistor, the first transmission transistor and
Second transmission transistor can be NMOS transistor.The equivalent circuit diagram for the Static RAM that the present embodiment is provided can join
Examine Fig. 2.
Please continue to refer to Fig. 6, in the present embodiment, the grid D31 of the first driving transistor is vertically across the first driving crystal
The fin (not marking) of pipe.The grid D32 of second driving transistor (is not marked) vertically across the fin of the second driving transistor.
The grid U31 of first load transistor (is not marked) vertically across the fin of the first load transistor.Second load transistor
Grid U32 (is not marked) vertically across the fin of the second load transistor.The grid G 31 of first transmission transistor is vertically across
The fin (not marking) of one transmission transistor.The grid G 32 of second transmission transistor is vertically across the fin of the second transmission transistor
Portion (does not mark).
Please continue to refer to Fig. 6, in the present embodiment, the first driving transistor, the first load transistor, the second driving crystal
Pipe, the second load transistor, the first transmission transistor and the second transmission transistor are located at rectangular broken line frame (not marking) institute in Fig. 6
In the rectangular area shown, third direction DR3 is parallel to wherein one side of rectangular area.
Please continue to refer to Fig. 6, for example vertical dotted line of projection in substrate (110) crystal face plane shown in Fig. 6 (is not marked
Note) shown in.The channel length of first driving transistor and the second driving transistor is respectively positioned on first direction DR1, first direction DR1
The substrate (001) crystal face is parallel to, and the angle theta of first direction DR1 and the substrate (110) crystal face is 45 °.It is found that
The angle (not shown) of first direction DR1 and the substrate (100) crystal face is 0 ° at this time.First load transistor and the second load
The channel length of transistor is respectively positioned on second direction DR2, and second direction DR2 is parallel to the substrate (001) crystal face, and second
The angle theta of direction DR2 and the substrate (110) crystal face is 45 °.It is found that second direction DR2 and the substrate (100) are brilliant at this time
The angle (not shown) in face is 0 °.
Since the angle theta of first direction DR1 and the substrate (100) crystal face is 0 °, the electricity of the first driving transistor
Stream driving force and the ratio β of the current driving ability of the first biography elm transistor can be improved to 1.1:1.Likewise, the second driving
The ratio β of the current driving ability of the current driving ability of transistor and the second biography elm transistor can be improved to 1.1:1.It is and entire
The performance of static random access memory cell is codetermined by two phase inverters, in two phase inverters ratio β improve to
1.1:When 1, the performance of static random access memory cell significantly improves, and corresponding Static RAM stability improves, tool
The read noise tolerance (read noise margin) that body shows as Static RAM significantly improves.
Since the included angle of second direction DR2 and the substrate (100) crystal face is 0 °, first passes elm transistor
The ratio γ of the current driving ability of current driving ability and the first load transistor can be improved to 1.4:1, likewise, second passes
The ratio γ of the current driving ability of the current driving ability of elm transistor and the second load transistor can be improved to 1.4:1, and
The performance of entire static random access memory cell is codetermined by two phase inverters, and ratio γ is carried in two phase inverters
Up to 1.4:When 1, the performance of static random access memory cell significantly improves, and corresponding Static RAM stability carries
Height, the noise margin (write noise margin) of writing for being embodied in Static RAM significantly improve.
In addition, in the present embodiment, compared with the prior art for, the channel length direction of the first driving transistor is (i.e.
First direction DR1) it is rotated, the grid D31 of the first driving transistor is caused correspondingly to rotate, the first load crystal
The channel length direction (i.e. second direction DR2) of pipe is rotated, and leads to the grid U31 of the first load transistor also phase
It rotates with answering, but can link together just after grid D31 and grid U31 rotations.Similarly, the second driving crystal
The channel length direction (i.e. first direction DR1) of pipe is rotated, and the grid D32 for leading to the second driving transistor is corresponding
Ground rotates, and the channel length direction (i.e. second direction DR2) of the second load transistor is rotated, and leads to second
The grid U32 of load transistor is also correspondingly rotated, but can be connected just after grid D32 and grid U32 rotations
Together.Therefore, it is such to rotate the area of plane for not increasing entire Static RAM storage unit, i.e., do not increase quiet
The making space (area) of state random access memory.And the area of plane of entire Static RAM storage unit still limits
In the rectangular area similar with Fig. 1, the dense degree and regularity of the arrangement of Static RAM storage unit are maintained.
Please continue to refer to Fig. 6, the equal position of channel length of the channel length of the first transmission transistor and the second transmission transistor
In third direction DR3, third direction DR3 is parallel to (001) crystal face, and third direction DR3 is parallel to the rectangular area
Wherein on one side.
It should be noted that in other embodiments of the invention, first direction DR1 and the substrate (100) crystal face
Angle can be other angles between 0 °~22 ° in addition to 0 °, at this point, ratio β is located at 1.05 accordingly:1~1.1:
Between 1, still meet the corresponding Static RAM storage unit coefficient of stability and still meet requirement.
It should be noted that in other embodiments of the invention, second direction DR2 and the substrate (100) crystal face
Angle can be other angles between 0 °~22 ° in addition to 0 °, at this point, ratio γ is located at 1.2 accordingly:1~1.4:
Between 1, still meet the corresponding Static RAM storage unit coefficient of stability and still meet requirement.
In the present embodiment, first direction DR1 is parallel with second direction DR2, and with the angle of the substrate (100) crystal face
It is 0 °.In this case, the design of simplified corresponding photomask layer in manufacturing process can not only be made, simplify processing procedure, and compare
The value of rate β and the value of ratio γ are optimal value simultaneously.But in other embodiments of the invention, first direction DR1 and
Two direction DR2 are parallel can not also be parallel, and the two can be able to be respectively 0 °~22 ° with the angle of the substrate (100) crystal face
In any angle.
It should be noted that in the present embodiment, first direction DR1 and second direction DR2 and the substrate (100) crystal face
Angle is 0 °~22 °.It but in other embodiments of the invention, can also only second direction DR2 and the substrate
(100) angle of crystal face is 0 °~22 °.
Further embodiment of this invention provides a kind of Static RAM memory cell layout.
Fig. 7 is please referred to, the Static RAM memory cell layout includes the be made on substrate first protrusion
410th, the second protrusion 420,430 and the 4th protrusion 440 of third protrusion, the second protrusion 420 and the 4th protrusion 440 are located at the first protrusion
Between 410 and third protrusion 430, the second protrusion 420 is located between the first protrusion 410 and the 4th protrusion 440.
The substrate is silicon monocrystalline substrate, is specifically as follows Silicon Wafer.The substrate top surface is brilliant for (001) of silicon single crystal
Face, i.e., plane shown in Fig. 7 are parallel to (001) crystal face of the substrate.And the vertical dotted line in Fig. 7 is substrate (110) crystal face
The projection of plane shown in Fig. 7.
Please continue to refer to Fig. 7, the first protrusion 410 includes the first fin 411, and (the first fin 411 surrounds part for dotted line frame
The first protrusion 410, other fins continue to use this representation method), the length of the first fin 411 is located at first direction DR1, first party
Substrate (001) crystal face is parallel to DR1.Second protrusion 420 includes the second fin 421, and the length of the second fin 421 is located at second
Direction (does not mark, in the present embodiment, second direction is parallel to the projection of (110) crystal face plane shown in Fig. 7), and second direction is put down
Row is in substrate (001) crystal face.Third protrusion 430 includes third fin 431, and the length of third fin 431 is located at first direction
DR1.4th protrusion 440 includes the 4th fin 441, and the length of the 4th fin 441 is located at second direction.The forming method of each protrusion
It is well known to those skilled in the art, details are not described herein.
In the present embodiment, the first fin 411 is used to form the first driving transistor, and the second fin 421 is used to form first
Load transistor, third fin 431 are used to form the second driving transistor, and the 4th fin 441 is used to form the second load crystal
Pipe.
Please continue to refer to Fig. 7, in entire Static RAM, the first protrusion 410 further includes the 5th fin 412, the
Five fins 412 are used to form the first transmission transistor.Third protrusion 430 further includes the 6th fin 432, and the 6th fin 432 is used for
Form the second transmission transistor.
Please continue to refer to Fig. 7, in the present embodiment, first direction DR1 and the angle of substrate (100) crystal face are 0 °, i.e. in Fig. 7
The angle of vertical dotted line (i.e. the projection of substrate (110) crystal face plane shown in Fig. 7) is shown in shown first direction DR1 and Fig. 7
45°.In this case, in the perfect crystal pipe subsequently formed in this plane figure, since the first fin 411 is used to form
First driving transistor and third fin 431 is used to form the second driving transistor, therefore, the electric current of the first driving transistor are driven
The ratio β of the current driving ability of kinetic force and the first biography elm transistor can be improved to 1.1:1.Likewise, the second driving crystal
The ratio β of the current driving ability of the current driving ability of pipe and the second biography elm transistor can be improved to 1.1:1.It is entire static with
Ratio β is improved to 1.1 in the performance of machine memory cell:1, i.e. the performance of static random access memory cell significantly improves, accordingly
Static RAM stability improve, the read noise tolerance for being embodied in Static RAM significantly improves.
It should be noted that in other embodiments of the invention, the angle of first direction DR1 and substrate (100) crystal face
Or in addition to 0 °, any angle between 0 °~22 °.
Please continue to refer to Fig. 8, the Static RAM memory cell layout further includes first grid 413, second gate
Pole 422,433 and the 4th grid 442 of third grid.First grid 413 is vertically across the first fin 411, and second grid 422 is vertically
Across the second fin 421, third grid 433 is vertically across third fin 431, and the 4th grid 442 is vertically across the 4th fin
441.And first grid 413 is connect with second grid 422.Third grid 433 is connect with the 4th grid 442.Meanwhile first fin
Portion 411, the second fin 421, third fin 431, the 4th fin 441, first grid 413, second grid 422, third grid 433
It is located in rectangular area (not showing, can refer to Fig. 5) with the 4th grid 442.
Please continue to refer to Fig. 8, in entire Static RAM, the 5th grid 414 and the 6th grid 434 are further included.
5th grid 414 is vertically across the 5th fin 412, and the 6th grid 434 is vertically across the 6th fin 432.5th fin 412,
Six fins 432, the 5th grid 414 and the 6th grid 434 are similarly positioned in above-mentioned rectangular area.
In the present embodiment, compared with the prior art for, the length direction (i.e. first direction DR1) of third fin 431
It is rotated, causes vertically correspondingly to rotate across the third grid 433 of third fin 431.And third grid 433 with
4th grid 442 connects, in order to which the 4th grid 442 is kept not rotate, between 433 and the 4th grid 442 of third grid
Gate material layer rotated twice.
In order to further illustrate rotating twice, by this part, gate material layer is further divided into the first gate material layer 451 and
Two gate material layers 452, as shown in Figure 8.For the first time rotate when, connection the 4th grid 442 the first gate material layer 451 rotation to
First direction DR1 is parallel, and when rotating for the second time, the second gate material layer 452 being connect with the first gate material layer 451 rotates back to Fig. 8
Shown horizontal direction, so as to which the second gate material layer 452 be made to be connect with third grid 433.First grid 413 and second grid
Between 422 it is also the same symmetrically take it is above-mentioned rotate twice, details are not described herein.This spinning solution can ensure entire plane
The area of plane of layout remains unchanged, so as to which the Static RAM storage unit being subsequently formed be made to keep corresponding intensive journey
Degree and regularity.
The Static RAM memory cell layout that the present embodiment is provided subsequently is further used for being formed complete quiet
State random access memory, the Static RAM formed can refer to Fig. 5 and Fig. 5 related contents.
Further embodiment of this invention provides a kind of Static RAM memory cell layout.
Fig. 9 is please referred to, the Static RAM memory cell layout includes the be made on substrate first protrusion
510th, the second protrusion 520,530 and the 4th protrusion 540 of third protrusion, the second protrusion 520 and the 4th protrusion 540 are located at the first protrusion
Between 510 and third protrusion 530, the second protrusion 520 is located between the first protrusion 510 and the 4th protrusion 540.
The substrate is silicon monocrystalline substrate, is specifically as follows Silicon Wafer.The substrate top surface is brilliant for (001) of silicon single crystal
Face, i.e., plane shown in Fig. 9 are parallel to (001) crystal face of the substrate.And the vertical dotted line in Fig. 9 is substrate (110) crystal face
The projection of plane shown in Fig. 9.
Please continue to refer to Fig. 9, the first protrusion 510 includes the first fin 511, and (the first fin 511 surrounds part for dotted line frame
The first protrusion 510, other fins continue to use this representation method), the length of the first fin 511 is located at first direction DR1, first party
Substrate (001) crystal face is parallel to DR1.Second protrusion 520 includes the second fin 521, and the length of the second fin 521 is located at second
Direction DR2, second direction DR2 are parallel to substrate (001) crystal face.Third protrusion 530 includes third fin 531, third fin 531
Length be located at first direction DR1.4th protrusion 540 includes the 4th fin 541, and the length of the 4th fin 541 is located at second party
To DR2.The forming method of each protrusion is well known to those skilled in the art, and details are not described herein.
In the present embodiment, the first fin 511 is used to form the first driving transistor, and the second fin 521 is used to form first
Load transistor, third fin 531 are used to form the second driving transistor, and the 4th fin 541 is used to form the second load crystal
Pipe.
Please continue to refer to Fig. 9, in entire Static RAM, the first protrusion 510 further includes the 5th fin 512, the
Five fins 512 are used to form the first transmission transistor.Third protrusion 530 further includes the 6th fin 532, and the 6th fin 532 is used for
Form the second transmission transistor.
Please continue to refer to Fig. 9, in the present embodiment, first direction DR1 and the angle of substrate (100) crystal face are 0 °, i.e. in Fig. 9
The angle of vertical dotted line (i.e. the projection of substrate (110) crystal face plane shown in Fig. 9) is shown in shown first direction DR1 and Fig. 9
45°.In this case, in the perfect crystal pipe subsequently formed in this plane figure, since the first fin 511 is used to form
First driving transistor and third fin 531 is used to form the second driving transistor, therefore, the electric current of the first driving transistor are driven
The ratio β of the current driving ability of kinetic force and the first biography elm transistor can be improved to 1.1:1.Likewise, the second driving crystal
The ratio β of the current driving ability of the current driving ability of pipe and the second biography elm transistor can be improved to 1.1:1.It is entire static with
Ratio β is improved to 1.1 in the performance of machine memory cell:1, i.e. the performance of static random access memory cell significantly improves, accordingly
Static RAM stability improve, the read noise tolerance for being embodied in Static RAM significantly improves.
Please continue to refer to Fig. 9, in the present embodiment, vertical dotted line (i.e. substrate (110) crystal face shown in second direction DR2 and Fig. 9
The projection of plane shown in Fig. 9) angle be 45 °.In this case, the perfect crystal subsequently formed in this plane figure
Guan Zhong, since the second fin 521 is used to form the first negative crystal pipe and the 4th fin 531 is used to form the second load transistor,
Therefore, the ratio γ of the current driving ability and the current driving ability of the first load transistor of the first biography elm transistor can be improved
To 1.4:1, likewise, second passes the ratio of the current driving ability of elm transistor and the current driving ability of the second load transistor
Rate γ can be improved to 1.4:1, and the performance of entire static random access memory cell significantly improves, corresponding Static RAM
Stability improves, and the noise margin of writing for being embodied in Static RAM significantly improves.
It should be noted that in other embodiments of the invention, the angle of first direction DR1 and substrate (100) crystal face
Or in addition to 0 °, any angle between 0 °~22 °.
Please continue to refer to Figure 10, the Static RAM memory cell layout further includes first grid 513, second gate
Pole 522,533 and the 4th grid 542 of third grid.First grid 513 is vertically across the first fin 511, and second grid 522 is vertically
Across the second fin 521, third grid 533 is vertically across third fin 531, and the 4th grid 542 is vertically across the 4th fin
541.And first grid 513 is connect with second grid 522.Third grid 533 is connect with the 4th grid 542.Meanwhile first fin
Portion 511, the second fin 521, third fin 531, the 4th fin 541, first grid 513, second grid 522, third grid 533
It is located in rectangular area (not showing, can refer to Fig. 6) with the 4th grid 542.
Please continue to refer to Figure 10, in entire Static RAM, the 5th grid 514 and the 6th grid 534 are further included.
5th grid 514 is vertically across the 5th fin 512, and the 6th grid 534 is vertically across the 6th fin 532.5th fin 512,
Six fins 532, the 5th grid 514 and the 6th grid 534 are similarly positioned in above-mentioned rectangular area.
Please continue to refer to Figure 10, the equal position of channel length of the channel length of the first transmission transistor and the second transmission transistor
In third direction DR3, third direction DR3 is parallel to (001) crystal face, and third direction DR3 is parallel to the substrate (110) crystalline substance
Face.
It should be noted that in other embodiments of the invention, first direction DR1 and the substrate (100) crystal face
Angle can be other angles between 0 °~22 ° in addition to 0 °, at this point, ratio β is located at 1.05 accordingly:1~1.1:
Between 1, still meet the corresponding Static RAM storage unit coefficient of stability and still meet requirement.
It should be noted that in other embodiments of the invention, second direction DR2 and the substrate (100) crystal face
Angle can be other angles between 0 °~22 ° in addition to 0 °, at this point, ratio γ is located at 1.2 accordingly:1~1.4:
Between 1, still meet the corresponding Static RAM storage unit coefficient of stability and still meet requirement.
In the present embodiment, compared with the prior art for, the length direction (i.e. first direction DR1) of third fin 531
It is rotated, causes vertically correspondingly to rotate across the third grid 533 of third fin 531.And third grid 533 with
4th grid 542 connects, in order to which the 4th grid 542 is kept not rotate, between 533 and the 4th grid 542 of third grid
Gate material layer 551 rotated.Specifically, this gate material layer 551 is rotated into it is parallel with first direction DR1, so as to make
Connect third grid 533 and the 4th grid 542.It is similarly symmetrically taken between first grid 513 and second grid 522 above-mentioned
It rotates twice, details are not described herein.This spinning solution can ensure that the area of plane of entire plane figure remains unchanged, so as to
The Static RAM storage unit being subsequently formed is made to keep corresponding dense degree and regularity.
In the present embodiment, first direction DR1 is parallel with second direction DR2, and with the angle of the substrate (100) crystal face
It is 0 °.In this case, the design of simplified corresponding photomask layer in manufacturing process can not only be made, simplify processing procedure, and compare
The value of rate β and the value of ratio γ are optimal value simultaneously.But in other embodiments of the invention, first direction DR1 and
Two direction DR2 are parallel can not also be parallel, and the two can be able to be respectively 0 °~22 ° with the angle of the substrate (100) crystal face
In any angle.
It should be noted that in the present embodiment, first direction DR1 and second direction DR2 and the substrate (100) crystal face
Angle is 0 °~22 °.It but in other embodiments of the invention, can also only second direction DR2 and the substrate
(100) angle of crystal face is 0 °~22 °.
The Static RAM memory cell layout that the present embodiment is provided subsequently is further used for being formed complete quiet
State random access memory, the Static RAM formed can refer to Fig. 6 and Fig. 6 related contents.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of Static RAM storage unit, including being made on substrate：
First driving transistor, the first load transistor, the second driving transistor and the second load transistor；
It is characterized in that,
The channel length of first driving transistor and the second driving transistor is located at first direction, and the first direction is parallel
In 001 crystal face of substrate；
The channel length of first load transistor and the second load transistor is located at second direction, and the second direction is parallel
In 001 crystal face of substrate；
In the first direction and the second direction, the angle of at least one direction and 100 crystal face of substrate is 0 °~
22°。
2. Static RAM storage unit as described in claim 1, which is characterized in that the first direction and described
In two directions, at least one direction and the angle of 100 crystal face of substrate are 0 °.
3. Static RAM storage unit as claimed in claim 1 or 2, which is characterized in that the first direction and institute
It is parallel to state second direction.
4. Static RAM storage unit as described in claim 1, which is characterized in that first driving transistor,
First load transistor, the second driving transistor and the second load transistor are located in rectangular area.
5. Static RAM storage unit as claimed in claim 4, which is characterized in that first driving transistor,
First load transistor, the second driving transistor and the second load transistor are fin formula field effect transistor.
6. Static RAM storage unit as claimed in claim 5, which is characterized in that first driving transistor
Gate vertical is across the fin of first driving transistor；The gate vertical of second driving transistor is across described second
The fin of driving transistor；The gate vertical of first load transistor is across the fin of first load transistor；Institute
State fin of the gate vertical across second load transistor of the second load transistor.
7. Static RAM storage unit as described in claim 1, which is characterized in that first driving transistor
Grid is connect with the grid of first load transistor；The grid of second driving transistor and the described second load crystal
The grid connection of pipe.
8. a kind of Static RAM memory cell layout, including being made on substrate：
It is convex that first protrusion, the second protrusion, third protrusion and the 4th protrusion, second protrusion and the 4th protrusion are located at described first
It rises between third protrusion, second protrusion is located between the described first protrusion and the 4th protrusion；
It is characterized in that,
First protrusion includes the first fin, and the length of first fin is located at first direction, and the first direction is parallel
In 001 crystal face of substrate；
Second protrusion includes the second fin, and the length of second fin is located at second direction, and the second direction is parallel
In 001 crystal face of substrate；
The third protrusion includes third fin, and the length of the third fin is located at the first direction；
4th protrusion includes the 4th fin, and the length of the 4th fin is located at the second direction；
In the first direction and the second direction, the angle of at least one direction and 100 crystal face of substrate is 0 °~
22°。
9. Static RAM memory cell layout as claimed in claim 8, which is characterized in that the first direction and institute
It states in second direction, at least one direction and the angle of 100 crystal face of substrate are 0 °.
10. Static RAM memory cell layout as claimed in claim 8 or 9, which is characterized in that the first direction
It is parallel with the second direction.
11. Static RAM memory cell layout as claimed in claim 8, which is characterized in that further include：The first grid
Pole, second grid, third grid and the 4th grid；The first grid is vertically across first fin, the second grid
Vertically across second fin, the third gate vertical is across the third fin, and the 4th gate vertical is across institute
State the 4th fin.
12. Static RAM memory cell layout as claimed in claim 11, which is characterized in that first fin,
Second fin, third fin, the 4th fin, first grid, second grid, third grid and the 4th grid are located at rectangular area
In.
13. Static RAM memory cell layout as claimed in claim 11, which is characterized in that the first grid with
The second grid connection；The third grid is connect with the 4th grid.
14. a kind of Static RAM, have make multiple static random access memory cells on substrate, a plurality of wordline,
Multiple bit lines；Each Static RAM storage unit, including：
First phase inverter has the first driving transistor and the first load transistor；
Second phase inverter has the second driving transistor and the second load transistor；
The output terminal of first phase inverter is connected to the input terminal of second phase inverter；
The input terminal of first phase inverter is connected to the output terminal of second phase inverter；
It is characterized in that,
The channel length of first driving transistor and the second driving transistor is respectively positioned on first direction, and the first direction is put down
Row is in 001 crystal face of substrate；
The channel length of first load transistor and the second load transistor is respectively positioned on second direction, and the second direction is put down
Row is in 001 crystal face of substrate；
In the first direction and the second direction, the angle of at least one direction and 100 crystal face of substrate is 0 °~
22°。
15. Static RAM as claimed in claim 14, which is characterized in that the first direction and the second direction
In, at least one direction and the angle of 100 crystal face of substrate are 0 °.
16. the Static RAM as described in claims 14 or 15, which is characterized in that the first direction and described second
Direction is parallel.
17. Static RAM as claimed in claim 14, which is characterized in that further include：
First transmission transistor is connected between the output terminal of the bit line and first phase inverter, and described first passes
Defeated transistor gate is connect with the wordline；
Second transmission transistor is connected between the output terminal of the bit line and second phase inverter, and described second passes
Defeated transistor gate is connect with the wordline；
The channel length of first transmission transistor and the channel length of the second transmission transistor are respectively positioned on third direction, described
Third direction is parallel to 001 crystal face, and the third direction is parallel to 110 crystal face of substrate.
18. Static RAM as claimed in claim 17, which is characterized in that first driving transistor, first negative
It carries transistor, the second driving transistor, the second load transistor, the first transmission transistor and the second transmission transistor and is located at rectangle
In region, the third direction is parallel to wherein one side of the rectangular area.
19. Static RAM as claimed in claim 18, which is characterized in that first driving transistor, first negative
It is fin to carry transistor, the second driving transistor, the second load transistor, the first transmission transistor and the second transmission transistor
Field-effect transistor.
20. Static RAM as claimed in claim 14, which is characterized in that the grid of first driving transistor with
The grid connection of first load transistor；The grid of the grid of second driving transistor and second load transistor
Pole connects.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1875428A (en) * | 2003-10-27 | 2006-12-06 | 日本电气株式会社 | Semiconductor storage device |
| CN101089425A (en) * | 2007-06-29 | 2007-12-19 | 陈招文 | Improved structure of scroll axle in hand regulating arm of vehicle |
| CN102592660A (en) * | 2012-02-17 | 2012-07-18 | 安徽大学 | Single-ended operation subthreshold memory cell circuit |
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2014
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1875428A (en) * | 2003-10-27 | 2006-12-06 | 日本电气株式会社 | Semiconductor storage device |
| CN101089425A (en) * | 2007-06-29 | 2007-12-19 | 陈招文 | Improved structure of scroll axle in hand regulating arm of vehicle |
| CN102592660A (en) * | 2012-02-17 | 2012-07-18 | 安徽大学 | Single-ended operation subthreshold memory cell circuit |
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