CN105374390A - Static random access memory, storage unit of static random access memory and layout of storage unit - Google Patents
Static random access memory, storage unit of static random access memory and layout of storage unit Download PDFInfo
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- CN105374390A CN105374390A CN201410439751.3A CN201410439751A CN105374390A CN 105374390 A CN105374390 A CN 105374390A CN 201410439751 A CN201410439751 A CN 201410439751A CN 105374390 A CN105374390 A CN 105374390A
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Abstract
The invention discloses a static random access memory, a storage unit of the static random access memory and a layout of the storage unit. The storage unit of the static random access memory comprises a first driving transistor, a first load transistor, a second driving transistor and a second load transistor which are arranged on a substrate, wherein channel lengths of the first driving transistor and the second driving transistor are located in a first direction, and the first direction is parallel to a crystal surface (001) of the substrate; channel lengths of the first load transistor and the second load transistor are located in a second direction, and the second direction is parallel to the crystal surface (001) of the substrate; and an included angle between at least one of the first and second directions and a crystal surface (100) of the substrate is 0-22 degrees. The storage unit of the static random access memory is improved in performance.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of static RAM, static RAM storage unit and layout thereof.
Background technology
Prior art is in semiconductor storage unit, and static RAM (SRAM) device has the advantage of lower power consumption and operating rate faster compared with dynamic RAM (DRAM) device.Static RAM can pass easily through again bitmap testing apparatus and carry out physical location location, the actual effect pattern of research product.
The storage unit of static RAM can be divided into ohmic load static RAM storage unit and complementary metal oxide semiconductor (CMOS) (CMOS) static RAM storage unit.Ohmic load static random access memory cell adopts the resistance of high resistance as load device, and CMOS static random-access memory unit adopts P-channel metal-oxide-semiconductor (PMOS) transistor as load device.Multiple nmos pass transistor and PMOS transistor is comprised in CMOS static random access memory.
The performance of existing CMOS static random access memory is not good.
Summary of the invention
The problem that the present invention solves is to provide a kind of static RAM, static RAM storage unit and layout thereof, to improve the performance of static RAM storage unit, and improves the performance of static RAM simultaneously.
For solving the problem, the invention provides a kind of static RAM storage unit, comprising and be made on substrate:
First driving transistors, the first load transistor, the second driving transistors and the second load transistor;
The channel length of described first driving transistors and the second driving transistors is positioned at first direction, and described first direction is parallel to described substrate (001) crystal face;
The channel length of described first load transistor and the second load transistor is positioned at second direction, and described second direction is parallel to described substrate (001) crystal face;
In described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 ° ~ 22 °.
Optionally, in described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 °.
Optionally, described first direction is parallel with described second direction.
Optionally, described first driving transistors, the first load transistor, the second driving transistors and the second load transistor are arranged in rectangular area.
Optionally, described first driving transistors, the first load transistor, the second driving transistors and the second load transistor are fin formula field effect transistor.
Optionally, the gate vertical of described first driving transistors is across the fin of described first driving transistors; The gate vertical of described second driving transistors is across the fin of described second driving transistors; The gate vertical of described first load transistor is across the fin of described first load transistor; The gate vertical of described second load transistor is across the fin of described second load transistor.
Optionally, the grid of described first driving transistors is connected with the grid of described first load transistor; The grid of described second driving transistors is connected with the grid of described second load transistor.
For solving the problem, present invention also offers a kind of static RAM memory cell layout, comprising and be made on substrate:
First projection, the second projection, the 3rd protruding and the 4th projection, described second projection and the 4th projection are between described first projection and the 3rd projection, and described second projection is between described first projection and the 4th projection;
Described first projection comprises the first fin, and the length of described first fin is positioned at first direction, and described first direction is parallel to described substrate (001) crystal face;
Described second projection comprises the second fin, and the length of described second fin is positioned at second direction, and described second direction is parallel to described substrate (001) crystal face;
Described 3rd projection comprises the 3rd fin, and the length of described 3rd fin is positioned at described first direction;
Described 4th projection comprises the 4th fin, and the length of described 4th fin is positioned at described second direction;
In described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 ° ~ 22 °.
Optionally, in described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 °.
Optionally, described first direction is parallel with described second direction.
Optionally, also comprise: first grid, second grid, the 3rd grid and the 4th grid; Described first grid is vertically across described first fin, and described second grid is vertically across described second fin, and described 3rd gate vertical is across described 3rd fin, and described 4th gate vertical is across described 4th fin.
Optionally, described first fin, the second fin, the 3rd fin, the 4th fin, first grid, second grid, the 3rd grid and the 4th grid are arranged in rectangular area.
Optionally, described first grid is connected with described second grid; Described 3rd grid is connected with described 4th grid.
For solving the problem, present invention also offers a kind of static RAM, there are the multiple static random access memory cells be produced on substrate, many wordline, multiple bit lines; Each static RAM storage unit, comprising:
First phase inverter, has the first driving transistors and the first load transistor;
Second phase inverter, has the second driving transistors and the second load transistor;
The output terminal of described first phase inverter is connected to the input end of described second phase inverter;
The input end of described first phase inverter is connected to the output terminal of described second phase inverter;
The channel length of described first driving transistors and the second driving transistors is all positioned at first direction, and described first direction is parallel to described substrate (001) crystal face;
The channel length of described first load transistor and the second load transistor is all positioned at second direction, and described second direction is parallel to described substrate (001) crystal face;
In described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 ° ~ 22 °.
Optionally, in described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 °.
Optionally, described first direction is parallel with described second direction.
Optionally, described static RAM also comprises:
First transmission transistor, between the output terminal being connected to described bit line and described first phase inverter, and described first transfer transistor gate is connected with described wordline;
Second transmission transistor, between the output terminal being connected to described bit line and described second phase inverter, and described second transfer transistor gate is connected with described wordline;
The channel length of described first transmission transistor and the channel length of the second transmission transistor are all positioned at third direction, and described third direction is parallel to (001) crystal face, and described third direction is parallel to described substrate (110) crystal face.
Optionally, described first driving transistors, the first load transistor, the second driving transistors, the second load transistor, the first transmission transistor and the second transmission transistor are arranged in rectangular area, described third direction be parallel to described rectangular area wherein.
Optionally, described first driving transistors, the first load transistor, the second driving transistors, the second load transistor, the first transmission transistor and the second transmission transistor are fin formula field effect transistor.
Optionally, the grid of described first driving transistors is connected with the grid of described first load transistor; The grid of described second driving transistors is connected with the grid of described second load transistor.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, the channel length of the first driving transistors and the second driving transistors is all positioned at first direction, described first direction is parallel to described substrate (001) crystal face, the channel length of described first load transistor and the second load transistor is all positioned at second direction, and described second direction is parallel to described substrate (001) crystal face.And in described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 ° ~ 22 °.Now meet following two conditions at least one of them:
The angle of condition one, first direction and described substrate (100) crystal face is 0 °, the ratio β that the current driving ability of the first driving transistors and first passes the current driving ability of elm transistor can be increased to more than 1.05:1, the ratio β that in like manner current driving ability and second of the second driving transistors passes the current driving ability of elm transistor can be increased to more than 1.05:1, the stability of static random access memory cell improves, corresponding static RAM stability improves, and the read noise tolerance limit of static RAM improves;
The angle of condition two, second direction and described substrate (100) crystal face is 0 °, the first ratio γ passing the current driving ability of elm transistor and the current driving ability of the first load transistor can be increased to more than 1.2:1, in like manner the second ratio γ passing the current driving ability of elm transistor and the current driving ability of the second load transistor can be increased to more than 1.2:1, the stability of static random access memory cell improves, corresponding static RAM stability improves, and the noise margin of writing of static RAM improves.
Accompanying drawing explanation
Fig. 1 is the floor map of existing static RAM;
Fig. 2 is the circuit diagram of existing static RAM;
Fig. 3 is the floor map of wafer;
Fig. 4 is that the channel region length of nmos pass transistor and PMOS transistor is parallel to substrate (110) crystal face and equivalent mobility curve figure during (100) crystal face respectively;
Fig. 5 is the static RAM floor map that one embodiment of the invention provides;
Fig. 6 is the static RAM floor map that further embodiment of this invention provides;
Fig. 7 to Fig. 8 is the static RAM plane figure schematic diagram that further embodiment of this invention provides;
Fig. 9 to Figure 10 is the static RAM plane figure schematic diagram that further embodiment of this invention provides.
Embodiment
As described in background, the performance of existing static RAM is not good.The plane figure of existing static RAM as shown in Figure 1.It comprises six transistors (all not marking), and plane figure shown in Fig. 1 shows active area (mark) and the grid of six transistors.Usual static RAM storage unit comprises the first driving transistors, the first load transistor, the second driving transistors and the second load transistor, and static RAM storage unit is positioned at rectangular broken line frame institute enclosing region as shown in Figure 1.
It should be noted that, clear in order to what mark, in each accompanying drawing of this instructions, when marking each grid, lead-in wire is drawn from one of them position of grid layer.But it will be appreciated by those skilled in the art that the grid layer being positioned at different active region is different grid, namely each grid is actually a wherein part for grid layer.Such as, in Fig. 1, grid D11 and grid U11 belongs to same grid layer (mark), in described grid layer, the part being positioned at the first driving transistors active region is grid D11, and the part being positioned at the first load transistor active region is grid U11.And it can thus be appreciated that grid D11 is connected with grid U11.
The grid G 11 of the first transmission transistor is connected with bit line WL11, is the channel region of the first transmission transistor below grid G 11.The grid G 11 of the first transmission transistor is connected with wordline WL11, and the source electrode of the first transmission transistor is connected with interconnection line H11, and the drain electrode of the first transmission transistor is connected with bit line B11.
The grid G 12 of the second transmission transistor is connected with bit line WL12, is the channel region of the second transmission transistor below grid G 12.The grid G 12 of the second transmission transistor is connected with wordline WL12, and the source electrode of the second transmission transistor is connected with interconnection line H12, and the drain electrode of the second transmission transistor is connected with bit line B12.
The grid D11 of the first driving transistors (driving transistors also claims pull-down transistor) is connected with the grid U11 of the first load transistor (load transistor also deserves to be called pull transistor).The source electrode of the first driving transistors is connected with the ground wire Vss being in ground level, the source electrode of the first load transistor is connected with power voltage line Vdd, the drain electrode of the first driving transistors is connected with interconnection line H11, and therefore the source electrode of the first transmission transistor is electrically connected with the drain electrode of the first driving transistors.
The grid D12 of the second driving transistors is connected with the grid U12 of the second load transistor.The source electrode of the second driving transistors is connected with the ground wire Vss being in ground level, the source electrode of the second load transistor is connected with power voltage line Vdd, the drain electrode of the second driving transistors is connected with interconnection line H12, and therefore the source electrode of the second transmission transistor is electrically connected with the drain electrode of the second driving transistors.
Please refer to Fig. 2, Fig. 2 is the circuit diagram of static RAM shown in Fig. 1, and its concrete connected mode can content described in reference diagram 1.
Please refer to Fig. 3, Fig. 3 shows wafer 10.Wafer 10 has upper surface 10A, and namely follow-up semiconductor devices is produced on upper surface 10A.The upper surface 10A of wafer 10 is parallel to (001) crystal face usually.When along the alignment notch (not shown) of wafer 10 and the center of circle and perpendicular to upper surface 10A cutting wafer 10, the cutting plane obtained is parallel to (110) crystal face, namely in Fig. 3, along dotted line 11 and perpendicular to after upper surface 10A cutting wafer 10, the tangent plane obtained is parallel to (110) crystal face.That is, (110) crystal face is projected as dotted line 11 on upper surface 10A.In like manner, after along dotted line 12 and perpendicular to upper surface 10A cutting wafer 10, the tangent plane obtained is parallel to (100) crystal face, namely (100) crystal face is projected as dotted line 12 at wafer 10 upper surface 10A, and the angle between dotted line 11 and dotted line 12 is 45 °, namely (110) crystal face and (100) crystal face are 45 ° at the angle of the projection of upper surface 10A.
Please refer to Fig. 4, in TCAD (semiconductor process simulation and device simulation instrument), when the channel length obtaining the PMOS transistor of nmos pass transistor is parallel to different crystal face, the different effective mobilities (effectivemobility) that (raceway groove) reverse-biased layer charge carrier demonstrates.Wherein, the representative of filled circles place curve be effective mobility distribution when being parallel to (110) crystal face of PMOS transistor channel length, the representative of open circles place curve be effective mobility distribution when being parallel to (100) crystal face of PMOS transistor channel length, the representative of closed square place curve be effective mobility distribution when being parallel to (110) crystal face of nmos pass transistor channel length, the representative of hollow square place curve be effective mobility distribution when being parallel to (100) crystal face of nmos pass transistor channel length.
As can see from Figure 4, effective mobility when effective mobility when nmos pass transistor channel length is parallel to (100) crystal face is parallel to (110) crystal face higher than nmos pass transistor channel length, and the ratio of former and later two effective mobilities is about 1.1:1.Effective mobility when effective mobility when PMOS transistor channel length is parallel to (100) crystal face is parallel to (110) crystal face lower than PMOS transistor channel length, and the ratio of former and later two effective mobilities is about 1:1.4.
The content of composition graphs 3 and Fig. 4 is understood that, in prior art, usual selection makes the channel length of whole transistor be parallel to (110) crystal face: because now, although the effective mobility of nmos pass transistor lower (low by about 10% when being parallel to (110) crystal face than channel length), but the effective mobility of PMOS transistor improves a lot (improving about 40% when being parallel to (110) crystal face than channel length), therefore, for whole semiconductor circuit, performance is optimized.
In summary, in existing static RAM, the channel length of each transistor is all positioned at the direction of parallel (110) crystal face, namely in Fig. 1, direction perpendicular to grid G 11 is parallel to (110) crystal face, in other words, in Fig. 1, direction, each transistor channel length place is all parallel to (110) crystal face.
But for static RAM, when the channel length of each transistor is all positioned at the direction of parallel (110) crystal face, its performance is not good.
Originally, the current driving ability of stability by driving transistors and the ratio β of the current driving ability of biography elm transistor of static RAM storage unit, and the ratio γ passing the current driving ability of elm transistor and the current driving ability of load transistor determines.By increasing the value of ratio β and ratio γ, the stability factor of static RAM storage unit can be increased.
In order to make the stability factor of static RAM storage unit reach necessary requirement, usually need to ensure that the value of ratio β is greater than or equal to 1.05:1, or the value of ratio γ is greater than or equal to 1.2:1.
But when the channel length of each transistor is all positioned at the direction of parallel (110) crystal face, the value of obvious ratio β and ratio γ is 1:1, and now the stability factor of static RAM storage unit cannot reach necessary requirement.
For this reason, the embodiment of the present invention provides a kind of static RAM storage unit, comprises the first driving transistors be made on substrate, the first load transistor, the second driving transistors and the second load transistor; The channel length of described first driving transistors and the second driving transistors is positioned at first direction, and described first direction is parallel to described substrate (001) crystal face; The channel length of described first load transistor and the second load transistor is positioned at second direction, and described second direction is parallel to described substrate (001) crystal face; In described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 ° ~ 22 °.
In usual prior art, the angle of first direction and second direction and described substrate (100) crystal face is 45 °, and now the value of ratio β and the value of ratio γ are 1:1.But in the present invention, in first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 ° ~ 22 °, thus reaches at least one in following two conditions: condition one, and the value of ratio β is greater than or equal to 1.05:1; Condition two, the value of ratio γ is greater than or equal to 1.2:1.Now the stability factor of static RAM storage unit reaches necessary requirement, and static RAM performance improves.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
One embodiment of the invention provides a kind of static RAM.
Please refer to Fig. 5, described static RAM has the multiple static random access memory cells be produced on substrate (not shown), many wordline and multiple bit lines.Described substrate is silicon monocrystalline substrate, is specifically as follows Silicon Wafer.Described substrate top surface is (001) crystal face of silicon single crystal, namely the plane shown in Fig. 5 is parallel to (001) crystal face of described substrate, and the projection that the vertical dotted line (mark) in Fig. 5 is described substrate (110) crystal face plane shown in Fig. 5.
Fig. 5 shows one of them static RAM storage unit of this enforcement static RAM and the circuit structure of periphery thereof.Described static RAM storage unit comprises the first driving transistors (mark) be made on above-mentioned substrate, the first load transistor (mark), the second driving transistors (mark) and the second load transistor (mark).The source electrode of the first driving transistors is connected with the ground wire Vss being in ground level.The drain electrode of the first driving transistors is connected with interconnection line H21.The source electrode of the second driving transistors is connected with the ground wire Vss being in ground level.The drain electrode of the second driving transistors is connected with interconnection line H22.The source electrode of the first load transistor is connected with power voltage line Vdd.The drain electrode of the first load transistor is connected with interconnection line H21.The source electrode of the second load transistor is connected with power voltage line Vdd.The drain electrode of the second load transistor is connected with interconnection line H22.
As shown in Figure 5, the static RAM that the present embodiment provides comprises the first phase inverter (mark) and the second phase inverter (mark).First phase inverter comprises the first driving transistors and the first load transistor.Second phase inverter comprises the second driving transistors and the second load transistor.The output terminal of the first phase inverter is connected to the input end of the second phase inverter by interconnection line H21.The input end of the first phase inverter is connected to the output terminal of the second phase inverter by interconnection line H22.
The static RAM that the present embodiment provides also comprises the first transmission transistor (mark) and the second transmission transistor (mark).First transmission transistor is connected between the output terminal of bit line and the first phase inverter, and the first transfer transistor gate is connected with wordline.Second transmission transistor is connected between the output terminal of bit line and the second phase inverter, and the second transfer transistor gate is connected with wordline.
Specifically as shown in Figure 5, be the channel region of the first transmission transistor below the grid G 21 of the first transmission transistor.The grid G 21 of the first transmission transistor is connected with wordline WL21.The source electrode of the first transmission transistor is connected with interconnection line H21.The drain electrode of the first transmission transistor is connected with bit line B21.It is the channel region of the second transmission transistor below the grid G 22 of the second transmission transistor.The grid G 22 of the second transmission transistor is connected with wordline WL22.The source electrode of the second transmission transistor is connected with interconnection line H22.The drain electrode of the second transmission transistor is connected with bit line B22.The source electrode of the first transmission transistor is electrically connected with the drain electrode of the first driving transistors.The source electrode of the second transmission transistor is electrically connected with the drain electrode of the second driving transistors.The grid D22 of the second driving transistors is connected with the grid U22 of the second load transistor, and both connect wordline W22, and wordline W22 connects interconnection line H21.The grid D21 of the first driving transistors is connected with the grid U21 of the first load transistor, and both connect wordline W21, and wordline W21 connects interconnection line H22.
In the present embodiment, the first driving transistors, the first load transistor, the second driving transistors, the second load transistor, the first transmission transistor and the second transmission transistor are fin formula field effect transistor.And the first load transistor and the second load transistor can be PMOS transistor, and the first driving transistors, the second driving transistors, the first transmission transistor and the second transmission transistor can be nmos pass transistor.The equivalent circuit diagram of the static RAM that the present embodiment provides can with reference to figure 2.
Please continue to refer to Fig. 5, in the present embodiment, the grid D21 of the first driving transistors is vertically across the fin (mark) of the first driving transistors.The grid D22 of the second driving transistors is vertically across the fin (mark) of the second driving transistors.The grid U21 of the first load transistor is vertically across the fin (mark) of the first load transistor.The grid U22 of the second load transistor is vertically across the fin (mark) of the second load transistor.The grid G 21 of the first transmission transistor is vertically across the fin (mark) of the first transmission transistor.The grid G 22 of the second transmission transistor is vertically across the fin (mark) of the second transmission transistor.
Please continue to refer to Fig. 5, in the present embodiment, first driving transistors, the first load transistor, the second driving transistors, the second load transistor, the first transmission transistor and the second transmission transistor are arranged in the rectangular area shown in Fig. 5 rectangular broken line frame (mark), third direction DR3 be parallel to rectangular area wherein.
Please continue to refer to Fig. 5, the projection of described substrate (110) crystal face in plane shown in Fig. 5 is as shown in vertical dotted line.The channel length of the first driving transistors and the second driving transistors is all positioned at first direction DR1, first direction DR1 is parallel to described substrate (001) crystal face, and the angle theta of first direction DR1 and described substrate (110) crystal face is 45 °.Known, now the angle (not shown) of first direction DR1 and described substrate (100) crystal face is 0 °.
Because the angle theta of first direction DR1 and described substrate (100) crystal face is 0 °, therefore, the ratio β that the current driving ability of the first driving transistors and first passes the current driving ability of elm transistor can be increased to 1.1:1.Same, the ratio β that the current driving ability of the second driving transistors and second passes the current driving ability of elm transistor can be increased to 1.1:1.And the performance of whole static random access memory cell is determined jointly by two phase inverters, when in two phase inverters, ratio β is all increased to 1.1:1, the performance of static random access memory cell significantly improves, corresponding static RAM stability improves, and the read noise tolerance limit (readnoisemargin) being embodied in static RAM significantly improves.
In addition, in the present embodiment, hinge structure, the direction, channel length place (i.e. first direction DR1) of the first driving transistors there occurs rotation, the grid D21 of the first driving transistors is caused correspondingly to rotate, rotate the partial response that the grid D21 of the first driving transistors is connected with the grid U21 of the first load transistor, thus ensure that grid U21 is still parallel with the grid G 21 of the first transmission transistor.In like manner, the direction, channel length place (i.e. first direction DR1) of the second driving transistors there occurs rotation, the grid D22 of the second driving transistors is caused correspondingly to rotate, rotate the partial response that the grid D22 of the second driving transistors is connected with the grid U22 of the second load transistor, thus ensure that grid U22 is still parallel with the grid G 22 of the second transmission transistor.But such rotation does not increase the area of plane of whole static RAM storage unit, namely do not increase the making space (area) of static RAM.And the area of plane of whole static RAM storage unit is still limited in the rectangular area similar with Fig. 1, maintain dense degree and the regularity of static RAM storage unit arrangement.
Please continue to refer to Fig. 5, the channel length of the first transmission transistor and the channel length of the second transmission transistor are all positioned at third direction DR3, third direction DR3 is parallel to (001) crystal face, and third direction DR3 is parallel to described substrate (110) crystal face.
It should be noted that, in other embodiments of the invention, the angle of first direction DR1 and described substrate (100) crystal face can for except 0 °, other angle between 0 ° ~ 22 °, now, ratio β, accordingly between 1.05:1 ~ 1.1:1, still meets corresponding static RAM storage unit stability factor and still meets the demands.
Further embodiment of this invention provides another kind of static RAM.
Please refer to Fig. 6, described static RAM has the multiple static random access memory cells be produced on substrate (not shown), many wordline and multiple bit lines.Described substrate is silicon monocrystalline substrate, is specifically as follows Silicon Wafer.Described substrate top surface is (001) crystal face of silicon single crystal, namely the plane shown in Fig. 6 is parallel to (001) crystal face of described substrate, and the projection that two vertical dotted lines (mark) in Fig. 6 are described substrate (110) crystal face plane shown in Fig. 6.
Fig. 6 shows one of them static RAM storage unit of this enforcement static RAM and the circuit structure of periphery thereof.Described static RAM storage unit comprises the first driving transistors (mark) be made on above-mentioned substrate, the first load transistor (mark), the second driving transistors (mark) and the second load transistor (mark).The source electrode of the first driving transistors is connected with the ground wire Vss being in ground level.The drain electrode of the first driving transistors is connected with interconnection line H31.The source electrode of the second driving transistors is connected with the ground wire Vss being in ground level.The drain electrode of the second driving transistors is connected with interconnection line H32.The source electrode of the first load transistor is connected with power voltage line Vdd.The drain electrode of the first load transistor is connected with interconnection line H31.The source electrode of the second load transistor is connected with power voltage line Vdd.The drain electrode of the second load transistor is connected with interconnection line H32.
As shown in Figure 6, the static RAM that the present embodiment provides comprises the first phase inverter (mark) and the second phase inverter (mark).First phase inverter comprises the first driving transistors and the first load transistor.Second phase inverter comprises the second driving transistors and the second load transistor.The output terminal of the first phase inverter is connected to the input end of the second phase inverter by interconnection line H31.The input end of the first phase inverter is connected to the output terminal of the second phase inverter by interconnection line H32.
The static RAM that the present embodiment provides also comprises the first transmission transistor (mark) and the second transmission transistor (mark).First transmission transistor is connected between the output terminal of bit line and the first phase inverter, and the first transfer transistor gate is connected with wordline.Second transmission transistor is connected between the output terminal of bit line and the second phase inverter, and the second transfer transistor gate is connected with wordline.
Specifically as shown in Figure 6, be the channel region of the first transmission transistor below the grid G 31 of the first transmission transistor.The grid G 31 of the first transmission transistor is connected with wordline WL31.The source electrode of the first transmission transistor is connected with interconnection line H31.The drain electrode of the first transmission transistor is connected with bit line B31.It is the channel region of the second transmission transistor below the grid G 32 of the second transmission transistor.The grid G 32 of the second transmission transistor is connected with wordline WL32.The source electrode of the second transmission transistor is connected with interconnection line H32.The drain electrode of the second transmission transistor is connected with bit line B32.The source electrode of the first transmission transistor is electrically connected with the drain electrode of the first driving transistors.The source electrode of the second transmission transistor is electrically connected with the drain electrode of the second driving transistors.The grid D32 of the second driving transistors is connected with the grid U32 of the second load transistor, and both connect wordline W32, and wordline W32 connects interconnection line H31.The grid D31 of the first driving transistors is connected with the grid U31 of the first load transistor, and both connect wordline W31, and wordline W31 connects interconnection line H32.
In the present embodiment, the first driving transistors, the first load transistor, the second driving transistors, the second load transistor, the first transmission transistor and the second transmission transistor are fin formula field effect transistor.And the first load transistor and the second load transistor can be PMOS transistor, and the first driving transistors, the second driving transistors, the first transmission transistor and the second transmission transistor can be nmos pass transistor.The equivalent circuit diagram of the static RAM that the present embodiment provides can with reference to figure 2.
Please continue to refer to Fig. 6, in the present embodiment, the grid D31 of the first driving transistors is vertically across the fin (mark) of the first driving transistors.The grid D32 of the second driving transistors is vertically across the fin (mark) of the second driving transistors.The grid U31 of the first load transistor is vertically across the fin (mark) of the first load transistor.The grid U32 of the second load transistor is vertically across the fin (mark) of the second load transistor.The grid G 31 of the first transmission transistor is vertically across the fin (mark) of the first transmission transistor.The grid G 32 of the second transmission transistor is vertically across the fin (mark) of the second transmission transistor.
Please continue to refer to Fig. 6, in the present embodiment, first driving transistors, the first load transistor, the second driving transistors, the second load transistor, the first transmission transistor and the second transmission transistor are arranged in the rectangular area shown in Fig. 6 rectangular broken line frame (mark), third direction DR3 be parallel to rectangular area wherein.
Please continue to refer to Fig. 6, the projection of described substrate (110) crystal face in plane shown in Fig. 6 is as shown in vertical dotted line (mark).The channel length of the first driving transistors and the second driving transistors is all positioned at first direction DR1, first direction DR1 is parallel to described substrate (001) crystal face, and the angle theta of first direction DR1 and described substrate (110) crystal face is 45 °.Known, now the angle (not shown) of first direction DR1 and described substrate (100) crystal face is 0 °.The channel length of the first load transistor and the second load transistor is all positioned at second direction DR2, second direction DR2 is parallel to described substrate (001) crystal face, and the angle theta of second direction DR2 and described substrate (110) crystal face is 45 °.Known, now the angle (not shown) of second direction DR2 and described substrate (100) crystal face is 0 °.
Because the angle theta of first direction DR1 and described substrate (100) crystal face is 0 °, therefore, the ratio β that the current driving ability of the first driving transistors and first passes the current driving ability of elm transistor can be increased to 1.1:1.Same, the ratio β that the current driving ability of the second driving transistors and second passes the current driving ability of elm transistor can be increased to 1.1:1.And the performance of whole static random access memory cell is determined jointly by two phase inverters, when in two phase inverters, ratio β is all increased to 1.1:1, the performance of static random access memory cell significantly improves, corresponding static RAM stability improves, and the read noise tolerance limit (readnoisemargin) being embodied in static RAM significantly improves.
Because the included angle of second direction DR2 and described substrate (100) crystal face is 0 °, therefore, the first ratio γ passing the current driving ability of elm transistor and the current driving ability of the first load transistor can be increased to 1.4:1, same, the second ratio γ passing the current driving ability of elm transistor and the current driving ability of the second load transistor can be increased to 1.4:1, and the performance of whole static random access memory cell is determined jointly by two phase inverters, when in two phase inverters, ratio γ is all increased to 1.4:1, the performance of static random access memory cell significantly improves, corresponding static RAM stability improves, the noise margin (writenoisemargin) of writing being embodied in static RAM significantly improves.
In addition, in the present embodiment, hinge structure, the direction, channel length place (i.e. first direction DR1) of the first driving transistors there occurs rotation, the grid D31 of the first driving transistors is caused correspondingly to rotate, the direction, channel length place (i.e. second direction DR2) of the first load transistor there occurs rotation, cause the grid U31 of the first load transistor also correspondingly to rotate, but grid D31 and grid U31 can link together just after rotating.In like manner, the direction, channel length place (i.e. first direction DR1) of the second driving transistors there occurs rotation, the grid D32 of the second driving transistors is caused correspondingly to rotate, the direction, channel length place (i.e. second direction DR2) of the second load transistor there occurs rotation, cause the grid U32 of the second load transistor also correspondingly to rotate, but grid D32 and grid U32 can link together just after rotating.Therefore, such rotation does not increase the area of plane of whole static RAM storage unit, does not namely increase the making space (area) of static RAM.And the area of plane of whole static RAM storage unit is still limited in the rectangular area similar with Fig. 1, maintain dense degree and the regularity of static RAM storage unit arrangement.
Please continue to refer to Fig. 6, the channel length of the first transmission transistor and the channel length of the second transmission transistor are all positioned at third direction DR3, third direction DR3 is parallel to (001) crystal face, and third direction DR3 be parallel to described rectangular area wherein.
It should be noted that, in other embodiments of the invention, the angle of first direction DR1 and described substrate (100) crystal face can for except 0 °, other angle between 0 ° ~ 22 °, now, ratio β, accordingly between 1.05:1 ~ 1.1:1, still meets corresponding static RAM storage unit stability factor and still meets the demands.
It should be noted that, in other embodiments of the invention, the angle of second direction DR2 and described substrate (100) crystal face can for except 0 °, other angle between 0 ° ~ 22 °, now, ratio γ, accordingly between 1.2:1 ~ 1.4:1, still meets corresponding static RAM storage unit stability factor and still meets the demands.
In the present embodiment, first direction DR1 is parallel with second direction DR2, and is 0 ° with the angle of described substrate (100) crystal face.In this case, the design simplifying corresponding light mask layer in manufacturing process can not only be made, simplify processing procedure, and the value of the value of ratio β and ratio γ reach optimal value simultaneously.But in other embodiments of the invention, first direction DR1 is parallel with second direction DR2 also can be not parallel, both can be respectively in 0 ° ~ 22 ° arbitrarily angled with the angle of described substrate (100) crystal face.
It should be noted that, in the present embodiment, the angle of first direction DR1 and second direction DR2 and described substrate (100) crystal face is 0 ° ~ 22 °.But, in other embodiments of the invention, also the angle of only second direction DR2 and described substrate (100) crystal face 0 ° ~ 22 ° can be.
Further embodiment of this invention provides a kind of static RAM memory cell layout.
Please refer to Fig. 7, described static RAM memory cell layout comprises the first projection 410, second projection 420 be made on substrate, the the 3rd protruding 430 and the 4th projection 440, second projection 420 and the 4th projection 440 are between the first projection 410 and the 3rd projection 430, and the second projection 420 is between the first projection 410 and the 4th projection 440.
Described substrate is silicon monocrystalline substrate, is specifically as follows Silicon Wafer.Described substrate top surface is (001) crystal face of silicon single crystal, and the plane namely shown in Fig. 7 is parallel to (001) crystal face of described substrate.And the projection that the vertical dotted line in Fig. 7 is substrate (110) crystal face plane shown in Fig. 7.
Please continue to refer to Fig. 7, first projection 410 comprises the first fin 411, and (the first fin 411 is the first projection 410 of dotted line frame encirclement part, other fin continues to use this method for expressing), the length of the first fin 411 is positioned at first direction DR1, and first direction DR1 is parallel to substrate (001) crystal face.Second projection 420 comprises the second fin 421, the length of the second fin 421 is positioned at second direction and (does not mark, the projection of crystal face plane shown in Fig. 7 that in the present embodiment, second direction is parallel to (110)), second direction is parallel to substrate (001) crystal face.The length that 3rd projection 430 comprises the 3rd fin the 431, three fin 431 is positioned at first direction DR1.The length that 4th projection 440 comprises the 4th fin the 441, four fin 441 is positioned at second direction.The formation method of each projection is well known to those skilled in the art, and does not repeat them here.
In the present embodiment, the first fin 411 is for the formation of the first driving transistors, and the second fin 421 is for the formation of the first load transistor, and the 3rd fin 431 is for the formation of the second driving transistors, and the 4th fin 441 is for the formation of the second load transistor.
Please continue to refer to Fig. 7, in whole static RAM, the first projection 410 also comprises the 5th fin the 412, five fin 412 for the formation of the first transmission transistor.3rd projection 430 also comprises the 6th fin the 432, six fin 432 for the formation of the second transmission transistor.
Please continue to refer to Fig. 7, in the present embodiment, the angle of first direction DR1 and substrate (100) crystal face is 0 °, and namely shown in DR1 and the Fig. 7 of first direction shown in Fig. 7, vertically the angle of dotted line (i.e. the projection of substrate (110) crystal face plane shown in Fig. 7) is 45 °.In this case, in the follow-up perfect crystal pipe formed in this plane figure, due to the first fin 411 for the formation of the first driving transistors and the 3rd fin 431 for the formation of the second driving transistors, therefore, the ratio β that the current driving ability and first of the first driving transistors passes the current driving ability of elm transistor can be increased to 1.1:1.Same, the ratio β that the current driving ability of the second driving transistors and second passes the current driving ability of elm transistor can be increased to 1.1:1.In the performance of whole static random access memory cell, ratio β is increased to 1.1:1, namely the performance of static random access memory cell significantly improves, corresponding static RAM stability improves, and the read noise tolerance limit being embodied in static RAM significantly improves.
It should be noted that, in other embodiments of the invention, the angle of first direction DR1 and substrate (100) crystal face also can be except 0 °, arbitrarily angled between 0 ° ~ 22 °.
Please continue to refer to Fig. 8, described static RAM memory cell layout also comprises first grid 413, second grid 422, the 3rd grid 433 and the 4th grid 442.First grid 413 is vertical across the first fin 411, and second grid 422 is vertically vertically vertical across the 4th fin 441 across the 3rd fin the 431, four grid 442 across the second fin the 421, three grid 433.And first grid 413 is connected with second grid 422.3rd grid 433 is connected with the 4th grid 442.Meanwhile, the first fin 411, second fin 421, the 3rd fin 431, the 4th fin 441, first grid 413, second grid 422, the 3rd grid 433 and the 4th grid 442 are positioned in rectangular area (do not show, can with reference to figure 5).
Please continue to refer to Fig. 8, in whole static RAM, also comprise the 5th grid 414 and the 6th grid 434.5th grid 414 is vertically vertical across the 6th fin 432 across the 5th fin the 412, six grid 434.5th fin 412, the 6th fin 432, the 5th grid 414 and the 6th grid 434 are arranged in above-mentioned rectangular area equally.
In the present embodiment, hinge structure, the direction, length place (i.e. first direction DR1) of the 3rd fin 431 there occurs rotation, causes vertically correspondingly rotating across the 3rd grid 433 of the 3rd fin 431.And the 3rd grid 433 is connected with the 4th grid 442, in order to keep the 4th grid 442 not rotate, the gate material layer between the 3rd grid 433 and the 4th grid 442 there occurs twice rotation.
In order to further illustrate twice rotation, this part gate material layer is further divided into first grid material layer 451 and second gate material layer 452, as shown in Figure 8.First time is when rotating, the first grid material layer 451 connecting the 4th grid 442 rotates to parallel with first direction DR1, when second time rotates, the second gate material layer 452 be connected with first grid material layer 451 rotates back to the horizontal direction shown in Fig. 8, thus second gate material layer 452 is connected with the 3rd grid 433.Take above-mentioned twice rotation too symmetrically between first grid 413 and second grid 422, do not repeat them here.This spinning solution can ensure that the area of plane of whole plane figure remains unchanged, thus makes the static RAM storage unit of follow-up formation keep corresponding dense degree and regularity.
Follow-up being further used for of the static RAM memory cell layout that the present embodiment provides forms complete static RAM, and the static RAM formed can with reference to figure 5 and Fig. 5 related content.
Further embodiment of this invention provides a kind of static RAM memory cell layout.
Please refer to Fig. 9, described static RAM memory cell layout comprises the first projection 510, second projection 520 be made on substrate, the the 3rd protruding 530 and the 4th projection 540, second projection 520 and the 4th projection 540 are between the first projection 510 and the 3rd projection 530, and the second projection 520 is between the first projection 510 and the 4th projection 540.
Described substrate is silicon monocrystalline substrate, is specifically as follows Silicon Wafer.Described substrate top surface is (001) crystal face of silicon single crystal, and the plane namely shown in Fig. 9 is parallel to (001) crystal face of described substrate.And the projection that the vertical dotted line in Fig. 9 is substrate (110) crystal face plane shown in Fig. 9.
Please continue to refer to Fig. 9, first projection 510 comprises the first fin 511, and (the first fin 511 is the first projection 510 of dotted line frame encirclement part, other fin continues to use this method for expressing), the length of the first fin 511 is positioned at first direction DR1, and first direction DR1 is parallel to substrate (001) crystal face.The length that second projection 520 comprises the second fin 521, second fin 521 is positioned at second direction DR2, and second direction DR2 is parallel to substrate (001) crystal face.The length that 3rd projection 530 comprises the 3rd fin the 531, three fin 531 is positioned at first direction DR1.The length that 4th projection 540 comprises the 4th fin the 541, four fin 541 is positioned at second direction DR2.The formation method of each projection is well known to those skilled in the art, and does not repeat them here.
In the present embodiment, the first fin 511 is for the formation of the first driving transistors, and the second fin 521 is for the formation of the first load transistor, and the 3rd fin 531 is for the formation of the second driving transistors, and the 4th fin 541 is for the formation of the second load transistor.
Please continue to refer to Fig. 9, in whole static RAM, the first projection 510 also comprises the 5th fin the 512, five fin 512 for the formation of the first transmission transistor.3rd projection 530 also comprises the 6th fin the 532, six fin 532 for the formation of the second transmission transistor.
Please continue to refer to Fig. 9, in the present embodiment, the angle of first direction DR1 and substrate (100) crystal face is 0 °, and namely shown in DR1 and the Fig. 9 of first direction shown in Fig. 9, vertically the angle of dotted line (i.e. the projection of substrate (110) crystal face plane shown in Fig. 9) is 45 °.In this case, in the follow-up perfect crystal pipe formed in this plane figure, due to the first fin 511 for the formation of the first driving transistors and the 3rd fin 531 for the formation of the second driving transistors, therefore, the ratio β that the current driving ability and first of the first driving transistors passes the current driving ability of elm transistor can be increased to 1.1:1.Same, the ratio β that the current driving ability of the second driving transistors and second passes the current driving ability of elm transistor can be increased to 1.1:1.In the performance of whole static random access memory cell, ratio β is increased to 1.1:1, namely the performance of static random access memory cell significantly improves, corresponding static RAM stability improves, and the read noise tolerance limit being embodied in static RAM significantly improves.
Please continue to refer to Fig. 9, in the present embodiment, shown in second direction DR2 and Fig. 9, vertically the angle of dotted line (i.e. the projection of substrate (110) crystal face plane shown in Fig. 9) is 45 °.In this case, in the follow-up perfect crystal pipe formed in this plane figure, due to the second fin 521 for the formation of the first negative crystal pipe and the 4th fin 531 for the formation of the second load transistor, therefore, the first ratio γ passing the current driving ability of elm transistor and the current driving ability of the first load transistor can be increased to 1.4:1, same, the second ratio γ passing the current driving ability of elm transistor and the current driving ability of the second load transistor can be increased to 1.4:1, and the performance of whole static random access memory cell significantly improves, corresponding static RAM stability improves, the noise margin of writing being embodied in static RAM significantly improves.
It should be noted that, in other embodiments of the invention, the angle of first direction DR1 and substrate (100) crystal face also can be except 0 °, arbitrarily angled between 0 ° ~ 22 °.
Please continue to refer to Figure 10, described static RAM memory cell layout also comprises first grid 513, second grid 522, the 3rd grid 533 and the 4th grid 542.First grid 513 is vertical across the first fin 511, and second grid 522 is vertically vertically vertical across the 4th fin 541 across the 3rd fin the 531, four grid 542 across the second fin the 521, three grid 533.And first grid 513 is connected with second grid 522.3rd grid 533 is connected with the 4th grid 542.Meanwhile, the first fin 511, second fin 521, the 3rd fin 531, the 4th fin 541, first grid 513, second grid 522, the 3rd grid 533 and the 4th grid 542 are positioned in rectangular area (do not show, can with reference to figure 6).
Please continue to refer to Figure 10, in whole static RAM, also comprise the 5th grid 514 and the 6th grid 534.5th grid 514 is vertically vertical across the 6th fin 532 across the 5th fin the 512, six grid 534.5th fin 512, the 6th fin 532, the 5th grid 514 and the 6th grid 534 are arranged in above-mentioned rectangular area equally.
Please continue to refer to Figure 10, the channel length of the first transmission transistor and the channel length of the second transmission transistor are all positioned at third direction DR3, third direction DR3 is parallel to (001) crystal face, and third direction DR3 is parallel to described substrate (110) crystal face.
It should be noted that, in other embodiments of the invention, the angle of first direction DR1 and described substrate (100) crystal face can for except 0 °, other angle between 0 ° ~ 22 °, now, ratio β, accordingly between 1.05:1 ~ 1.1:1, still meets corresponding static RAM storage unit stability factor and still meets the demands.
It should be noted that, in other embodiments of the invention, the angle of second direction DR2 and described substrate (100) crystal face can for except 0 °, other angle between 0 ° ~ 22 °, now, ratio γ, accordingly between 1.2:1 ~ 1.4:1, still meets corresponding static RAM storage unit stability factor and still meets the demands.
In the present embodiment, hinge structure, the direction, length place (i.e. first direction DR1) of the 3rd fin 531 there occurs rotation, causes vertically correspondingly rotating across the 3rd grid 533 of the 3rd fin 531.And the 3rd grid 533 is connected with the 4th grid 542, in order to keep the 4th grid 542 not rotate, the gate material layer 551 between the 3rd grid 533 and the 4th grid 542 there occurs rotation.Concrete, this gate material layer 551 is rotated into parallel with first direction DR1, thus makes connection the 3rd grid 533 and the 4th grid 542.Take above-mentioned twice rotation too symmetrically between first grid 513 and second grid 522, do not repeat them here.This spinning solution can ensure that the area of plane of whole plane figure remains unchanged, thus makes the static RAM storage unit of follow-up formation keep corresponding dense degree and regularity.
In the present embodiment, first direction DR1 is parallel with second direction DR2, and is 0 ° with the angle of described substrate (100) crystal face.In this case, the design simplifying corresponding light mask layer in manufacturing process can not only be made, simplify processing procedure, and the value of the value of ratio β and ratio γ reach optimal value simultaneously.But in other embodiments of the invention, first direction DR1 is parallel with second direction DR2 also can be not parallel, both can be respectively in 0 ° ~ 22 ° arbitrarily angled with the angle of described substrate (100) crystal face.
It should be noted that, in the present embodiment, the angle of first direction DR1 and second direction DR2 and described substrate (100) crystal face is 0 ° ~ 22 °.But, in other embodiments of the invention, also the angle of only second direction DR2 and described substrate (100) crystal face 0 ° ~ 22 ° can be.
Follow-up being further used for of the static RAM memory cell layout that the present embodiment provides forms complete static RAM, and the static RAM formed can with reference to figure 6 and Fig. 6 related content.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a static RAM storage unit, comprises and is made on substrate:
First driving transistors, the first load transistor, the second driving transistors and the second load transistor;
It is characterized in that,
The channel length of described first driving transistors and the second driving transistors is positioned at first direction, and described first direction is parallel to described substrate (001) crystal face;
The channel length of described first load transistor and the second load transistor is positioned at second direction, and described second direction is parallel to described substrate (001) crystal face;
In described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 ° ~ 22 °.
2. static RAM storage unit as claimed in claim 1, is characterized in that, in described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 °.
3. static RAM storage unit as claimed in claim 1 or 2, it is characterized in that, described first direction is parallel with described second direction.
4. static RAM storage unit as claimed in claim 1, it is characterized in that, described first driving transistors, the first load transistor, the second driving transistors and the second load transistor are arranged in rectangular area.
5. static RAM storage unit as claimed in claim 4, it is characterized in that, described first driving transistors, the first load transistor, the second driving transistors and the second load transistor are fin formula field effect transistor.
6. static RAM storage unit as claimed in claim 5, is characterized in that, the gate vertical of described first driving transistors is across the fin of described first driving transistors; The gate vertical of described second driving transistors is across the fin of described second driving transistors; The gate vertical of described first load transistor is across the fin of described first load transistor; The gate vertical of described second load transistor is across the fin of described second load transistor.
7. static RAM storage unit as claimed in claim 1, it is characterized in that, the grid of described first driving transistors is connected with the grid of described first load transistor; The grid of described second driving transistors is connected with the grid of described second load transistor.
8. a static RAM memory cell layout, comprises and is made on substrate:
First projection, the second projection, the 3rd protruding and the 4th projection, described second projection and the 4th projection are between described first projection and the 3rd projection, and described second projection is between described first projection and the 4th projection;
It is characterized in that,
Described first projection comprises the first fin, and the length of described first fin is positioned at first direction, and described first direction is parallel to described substrate (001) crystal face;
Described second projection comprises the second fin, and the length of described second fin is positioned at second direction, and described second direction is parallel to described substrate (001) crystal face;
Described 3rd projection comprises the 3rd fin, and the length of described 3rd fin is positioned at described first direction;
Described 4th projection comprises the 4th fin, and the length of described 4th fin is positioned at described second direction;
In described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 ° ~ 22 °.
9. static RAM memory cell layout as claimed in claim 8, is characterized in that, in described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 °.
10. static RAM memory cell layout as claimed in claim 8 or 9, it is characterized in that, described first direction is parallel with described second direction.
11. static RAM memory cell layout as claimed in claim 8, is characterized in that, also comprise: first grid, second grid, the 3rd grid and the 4th grid; Described first grid is vertically across described first fin, and described second grid is vertically across described second fin, and described 3rd gate vertical is across described 3rd fin, and described 4th gate vertical is across described 4th fin.
12. static RAM memory cell layout as claimed in claim 11, is characterized in that, described first fin, the second fin, the 3rd fin, the 4th fin, first grid, second grid, the 3rd grid and the 4th grid are arranged in rectangular area.
13. static RAM memory cell layout as claimed in claim 9, it is characterized in that, described first grid is connected with described second grid; Described 3rd grid is connected with described 4th grid.
14. 1 kinds of static RAM, have the multiple static random access memory cells be produced on substrate, many wordline, multiple bit lines; Each static RAM storage unit, comprising:
First phase inverter, has the first driving transistors and the first load transistor;
Second phase inverter, has the second driving transistors and the second load transistor;
The output terminal of described first phase inverter is connected to the input end of described second phase inverter;
The input end of described first phase inverter is connected to the output terminal of described second phase inverter;
It is characterized in that,
The channel length of described first driving transistors and the second driving transistors is all positioned at first direction, and described first direction is parallel to described substrate (001) crystal face;
The channel length of described first load transistor and the second load transistor is all positioned at second direction, and described second direction is parallel to described substrate (001) crystal face;
In described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 ° ~ 22 °.
15. static RAM as claimed in claim 14, is characterized in that, in described first direction and described second direction, the angle of at least one direction and described substrate (100) crystal face is 0 °.
16. static RAM as described in claims 14 or 15, it is characterized in that, described first direction is parallel with described second direction.
17. static RAM as claimed in claim 14, is characterized in that, also comprise:
First transmission transistor, between the output terminal being connected to described bit line and described first phase inverter, and described first transfer transistor gate is connected with described wordline;
Second transmission transistor, between the output terminal being connected to described bit line and described second phase inverter, and described second transfer transistor gate is connected with described wordline;
The channel length of described first transmission transistor and the channel length of the second transmission transistor are all positioned at third direction, and described third direction is parallel to (001) crystal face, and described third direction is parallel to described substrate (110) crystal face.
18. static RAM as claimed in claim 17, it is characterized in that, described first driving transistors, the first load transistor, the second driving transistors, the second load transistor, the first transmission transistor and the second transmission transistor are arranged in rectangular area, described third direction be parallel to described rectangular area wherein.
19. static RAM as claimed in claim 18, it is characterized in that, described first driving transistors, the first load transistor, the second driving transistors, the second load transistor, the first transmission transistor and the second transmission transistor are fin formula field effect transistor.
20. static RAM as claimed in claim 14, is characterized in that, the grid of described first driving transistors is connected with the grid of described first load transistor; The grid of described second driving transistors is connected with the grid of described second load transistor.
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| CN102592660A (en) * | 2012-02-17 | 2012-07-18 | 安徽大学 | Single-ended operation subthreshold memory cell circuit |
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| CN1875428A (en) * | 2003-10-27 | 2006-12-06 | 日本电气株式会社 | Semiconductor storage device |
| CN101089425A (en) * | 2007-06-29 | 2007-12-19 | 陈招文 | Improved structure of scroll axle in hand regulating arm of vehicle |
| CN102592660A (en) * | 2012-02-17 | 2012-07-18 | 安徽大学 | Single-ended operation subthreshold memory cell circuit |
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