CN105355602B - Three-dimensional semiconductor device and method for manufacturing the same - Google Patents

Abstract

A three-dimensional semiconductor device comprising a plurality of memory cells, each comprising: a channel layer distributed along a direction perpendicular to a substrate surface; a bottom gate conductive layer located in a first insulating layer stack and distributed on the side of the channel layer On the wall; the floating gate layer is located on the first insulating layer stack and distributed on the sidewall of the channel layer; a plurality of second insulating layers and a plurality of gate conductive layers are located on the floating gate layer and along the channel Layer sidewalls are stacked alternately; the gate dielectric layer is distributed on the sidewalls of the channel layer; the drain is located on the top of the channel layer; and the source is located in the substrate between two adjacent storage units of multiple storage units . The non-extracted floating gate is embedded inside, and the voltage is induced on the floating gate through the coupling of the voltage on the adjacent extraction gate to assist in completing the channel inversion of the contact area between the SEG and the polysilicon, thereby overcoming the current bottleneck in this area and increasing the channel current. Effectively control the threshold voltage consistency of the floating gate adjacent FETs.

Description

Three-dimensional semiconductor device and manufacturing method thereof

technical field

The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional semiconductor storage device and a manufacturing method thereof.

Background technique

In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate.

Specifically, as shown in Figure 1, a multilayer stacked structure (such as multiple ONO structures alternated with oxides and nitrides) can be deposited on the substrate at first; The structure is etched to form a plurality of channel via holes distributed along the extending direction of the memory cell word line (WL) and perpendicular to the substrate surface (which can directly reach the substrate surface or have a certain over-etching); in the channel via hole Deposit polysilicon and other materials to form a columnar channel; etch the multilayer stack structure along the WL direction to form a trench reaching the substrate, exposing the multilayer stack surrounding the columnar channel; wet removal of a certain type of material in the stack (such as hot phosphoric acid to remove silicon nitride, or HF to remove silicon oxide), leaving a laterally distributed protrusion structure around the columnar channel; depositing a gate dielectric layer (such as a high-k dielectric material) on the sidewall of the protrusion structure in the trench and a gate conductive layer (such as Ti, W, Cu, Mo, etc.) to form a gate stack, for example, including a bottom selection gate line BSG, a dummy gate line DG, word lines WL0˜WL31, and a top selection gate line TSG; Vertical anisotropic etching removes the gate stack beyond the side plane of the protrusion until the gate dielectric layer on the side of the protrusion is exposed; the stacked structure is etched to form source-drain contacts and complete the back-end manufacturing process. At this time, the part of the stack structure left on the sidewall of the columnar channel forms an isolation layer between the gate electrodes (shown as ILD in Figure 1), and the remaining gate stack is sandwiched between multiple isolation layers. as the control electrode. When a voltage is applied to the gate, the fringe electric field of the gate will induce the formation of source and drain regions on the side walls of the columnar channel of polysilicon material, thereby forming a gate array composed of multiple series and parallel MOSFETs to record the stored logic. state.

Among them, in the original storage structure, in order to ensure the consistent performance of each Cell, the L-shaped area where the epitaxial silicon growth (SEG) contacts the polysilicon is generally between the dummy gate line DG of the dummy device and the gate line BSG of the downselect tube. (that is, the bottom of the channel layer CL is higher than the top of the substrate SUB), so the thickness of the insulating layer between the memory cells (such as W1) will be smaller than the thickness of the insulating layer between dummy and BSG (such as W2), so in When the virtual source and drain regions are formed based on the coupled electric field, it is difficult for the SEG and the polysilicon contact region to form inversion, resulting in a decrease in the channel current of the memory string. In addition, the threshold voltage of the dummy cell will be too large due to the asymmetric fringe field (Fringe Field, as shown by the arrow in Figure 1), which is difficult to control.

Contents of the invention

From the above, the object of the present invention is to overcome the above technical difficulties and propose an innovative three-dimensional semiconductor storage device and its manufacturing method.

To this end, the present invention provides a three-dimensional semiconductor device on the one hand, including a plurality of memory cells, each of the plurality of memory cells includes: a channel layer, distributed along a direction perpendicular to the substrate surface; a bottom gate conductive layer, Located in the first insulating layer stack, distributed on the sidewall of the channel layer; the floating gate layer, located on the first insulating layer stack, distributed on the sidewall of the channel layer; a plurality of second insulating layers and a plurality of The gate conductive layer, located on the floating gate layer, is alternately stacked along the sidewall of the channel layer; the gate dielectric layer, distributed on the sidewall of the channel layer; the drain, located on the top of the channel layer; and the source The electrodes are located in the substrate between two adjacent storage units of the plurality of storage units.

Wherein, each memory cell further includes an epitaxial channel layer, located between the first insulating layer stack below the channel layer; preferably, the top of the epitaxial channel layer is equal to or higher than the bottom of the floating gate layer, and lower than the top of the floating gate layer .

Wherein, the floating gate layer is flush with the sidewall of the bottom gate conductive layer, or is extrapolated relative to the channel layer.

Wherein, the cross-sectional shape of the channel layer parallel to the substrate surface includes a shape selected from rectangle, square, rhombus, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon and combinations thereof The geometric shape, as well as a solid geometric figure, a hollow circular geometric figure, or a combined figure of the hollow circular peripheral layer and the center of the insulating layer selected from the evolution of the geometric shape.

Wherein, the gate dielectric layer further includes a tunneling layer, a storage layer, and a blocking layer.

Wherein, the channel layer includes a first channel layer, a second channel layer, and a channel filling layer. Preferably, the material of the first channel layer and/or the second channel layer is selected from group V simple substances, group V compounds, III - Group V compounds, II-VI compound semiconductors, such as single crystal Si, amorphous Si, polycrystalline Si, microcrystalline Si, single crystal Ge, SiGe, Si:C, SiGe:C, SiGe:H, GeSn, Any one of InSn, InN, InP, GaN, GaP, GaSn, GaAs or a combination thereof, preferably the channel filling layer material is air or oxide, nitride; optionally, the gate dielectric layer includes a high-k material; any Optionally, the bottom gate conductive layer or the material of the gate conductive layer is any one of polysilicon, metal, metal nitride, metal silicide or a combination thereof.

Another aspect of the present invention provides a method for manufacturing a three-dimensional semiconductor device, including the steps of: sequentially forming a first insulating layer stack, a floating gate layer, and a second insulating layer stack on a substrate in a memory cell region, wherein the second insulating layer The stack includes a plurality of alternating first material layers and second material layers; etching forms a plurality of deep holes until the substrate is exposed; forms a gate dielectric layer and a channel layer on the sidewalls and bottom of the deep holes; fills the channel The drain is formed on the top of the layer; the second material layer is removed by selective etching, leaving a plurality of lateral grooves and openings that expose the substrate; a gate conductive layer is formed in the plurality of grooves; in the substrate at the bottom of the opening form the source.

Wherein, after forming a plurality of deep holes by etching, it further includes epitaxially growing an epitaxial channel layer on the substrate, preferably, the top of the epitaxial channel layer is equal to or higher than the bottom of the floating gate layer, and lower than the top of the floating gate layer.

Wherein, after forming a plurality of deep holes by etching, it further includes laterally etching the floating gate layer to form a recess extended from the channel layer.

Wherein, while removing the second material layer by selective etching, the intermediate layer of the first insulating layer stack is also at least partially removed to leave a lateral recess, and the bottom gate is formed in the lateral recess while the gate conductive layer is subsequently formed. extremely conductive layer.

According to the three-dimensional semiconductor storage device and its manufacturing method of the present invention, the non-extracted floating gate is embedded inside, and the voltage is induced on the floating gate through the coupling of the voltage on the adjacent extraction gate level, thereby assisting in the completion of the SEG and the polysilicon contact area. Channel inversion, so as to overcome the current bottleneck in this region, increase the channel current, and effectively control the consistency of the threshold voltage of the tubes adjacent to the floating gate.

Description of drawings

Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:

1 is a cross-sectional view of a three-dimensional semiconductor memory device in the prior art;

2A to 2K are cross-sectional views of various steps of a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention;

3 is a cross-sectional view of a three-dimensional semiconductor memory device according to another embodiment of the present invention; and

FIG. 4 is a cross-sectional view of peripheral wiring of a three-dimensional semiconductor memory device according to an embodiment of the present invention.

Detailed ways

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in conjunction with schematic embodiments, and a semiconductor memory device and its manufacture that effectively overcome the current bottleneck, increase the channel current, and effectively control the consistency of the threshold voltage are disclosed. method. It should be pointed out that similar reference numerals represent similar structures, and the terms first, second, upper, lower, etc. used in this application can be used to modify various device structures or manufacturing processes. These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or fabrication processes unless specifically stated.

As shown in FIG. 2A, a first insulating layer stack 2 (including a lower layer 2A, a middle layer 2B, and an upper layer 2C), a floating gate layer 3, and a second insulating layer stack 4 (including a plurality of alternately stacked first insulating layers) are sequentially formed on a substrate 1. A material layer 4A and a plurality of second material layers 4B), the deposition process includes, for example, LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering and the like. A substrate 1 is provided, and its material may include bulk silicon (bulk Si), bulk germanium (bulk Ge), silicon-on-insulator (SOI), germanium-on-insulator (GeOI) or other compound semiconductor substrates, such as SiGe, SiC, GaN , GaAs, InP, etc., and combinations of these substances. In order to be compatible with the existing IC manufacturing process, the substrate 1 is preferably a substrate containing silicon, such as Si, SOI, SiGe, Si:C and the like. In a preferred embodiment of the present invention, the first insulating layer stack 2 includes a stack of oxide and nitride, such as a lower layer 2A of silicon oxide, a middle layer 2B of silicon nitride or silicon oxynitride, and an upper layer 2C of silicon oxide, forming ONO stack structure. In another preferred embodiment of the present invention, the material of the lower layer 2A and the upper layer 2C is the same as the multiple first material layers 4A formed later, and the material of the middle layer 2B is the same as the multiple second material layers 4B formed later, without having to Limited to the ONO structure. Floating gate layer 3 materials are polycrystalline Si, polycrystalline Ge, SiGe, Si:C and other semiconductor materials (preferably doped with N or P-type conductivity), and can also be Ta, Ti, Hf, Zr, Mo, W or Other metal elements, silicides or nitrides of these metals, such as W, Ti, Ta, WSi, TiSi, WN, TiN, TaN, etc. The material of the second insulating layer stack structure 4 is selected from the combination of the following materials and includes at least one insulating medium: such as silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, diamond-like amorphous carbon (DLC), germanium oxide , alumina, etc. and combinations thereof. The first material layer 4A has a first etch selectivity, and the second material layer 4B has a second etch selectivity different from the first etch selectivity. In a preferred embodiment of the present invention, the combination of the stacked structure 4A/4B is, for example, a combination of silicon oxide and silicon nitride, a combination of silicon oxide and polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon and many more. In a preferred embodiment of the present invention, layer 4A and layer 4B have a relatively large etching selectivity ratio (for example, greater than 5:1) under wet etching conditions or oxygen plasma dry etching conditions. As shown in FIG. 2A , the second insulating layer stack 4 includes at least seven first material layers 4A and six second material layers 4B stacked alternately (that is, preferably the top of the second insulating layer stack 4 is the first material layer 4A ), naturally other numbers of material layer stacks can also be provided according to the number of memory cell strings.

As shown in FIG. 2B, an epitaxial channel layer 1E is formed. Select an anisotropic etching process, such as plasma dry etching or RIE using fluorocarbon (C _x H _y F _z constitutes a fluorocarbon) as the etching gas, and etch the second insulating layer stack 4A vertically downward / 4B, the floating gate layer 3 , and the first insulating layer stack 2A/ 2B/ 2C form deep holes or trenches 4G until the substrate 1 is exposed. The cross-sectional shape of the hole 4G cut parallel to the surface of the substrate 1 can be a rectangle, a square, a rhombus, a circle, a semicircle, an ellipse, a triangle, a pentagon, a pentagon, a hexagon, an octagon, etc. various geometric shapes. Subsequently, the epitaxial channel layer 1E is epitaxially formed by MOCVD, MBE, ALD and other processes, and the material and the substrate 1 may be the same, for example, both are Si. In another preferred embodiment of the present invention, the material of the epitaxial channel layer 1E can be different from that of the substrate 1, for example, it is a V group, III-V group or II-VI group compound semiconductor, such as SiGe, Si:C, SiGe:C , Ge, GeSn, InSn, InN, InP, GaN, GaP, GaSn, GaAs, etc. and their combinations to enhance carrier mobility and improve driving ability. As shown in FIG. 2B, preferably, the top of the epitaxial layer 1E is flush with the top of the first insulating layer stack 2 (that is, the top upper layer 2C), flush with the bottom of the floating gate layer 3, or may be further higher than the floating gate layer 3. The bottom and lower than the top of the floating gate layer 3, so as to reduce the influence of the fringe electric field on the future selection gate BSG of the lower layer.

Optionally (that is, this step may not be performed), as shown in FIG. 2C , the floating gate layer 3 is selectively etched to leave a side recess 3R. Since the material of the floating gate layer 3 is semiconductor or metal, metal silicide, or metal nitride, it has high etching selectivity with the upper and lower insulating layers 4 and 2, so an isotropic etching process can be selected for floating gate layer 3. The gate layer 3 is etched laterally to form a recess 3R (the recess 3R may be ring-shaped in a plan view not shown), for example, the depth of the recess is 5-50 nm. The recess 3R will make the subsequently formed gate insulating layer, channel layer and other structures be recessed to the side, which enhances the coupling capability and increases the channel current.

As shown in FIG. 2D , using PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD and other processes, the gate insulating stack 5 and the first channel layer 6A are sequentially deposited in the deep hole 4G. The gate insulating stack 5 includes a plurality of sublayers, for example, at least including a tunneling layer 5C, a storage layer 5B, a barrier layer 5A, the barrier layer 5A directly contacts the second insulating layer stack 4A/4B of the sidewall of the deep hole 4G, and the tunneling layer 5C It is closest to the central axis of the deep hole 4G and contacts the subsequently deposited first channel layer 6A. Wherein the tunneling layer includes SiO ₂ or high-k materials, where high-k materials include but not limited to nitrides (such as SiN, AlN, TiN), metal oxides (mainly subgroup and lanthanide metal element oxides, such as MgO, Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , ZnO, ZrO ₂ , HfO ₂ , CeO ₂ , Y ₂ O ₃ , La ₂ O ₃ ), nitrogen oxides (such as SiON, HfSiON), perovskite phase oxidation substances (such as PbZr _x Ti _1-x O ₃ (PZT), Ba _x Sr _1-x TiO ₃ (BST)), etc., the tunneling layer can be a single-layer structure or a multi-layer stack structure of the above materials. The storage layer is a dielectric material with charge trapping capability, such as SiN, SiON, HfO, ZrO, etc. and combinations thereof, and can also be a single-layer structure or a multi-layer stack structure of the above materials. The barrier layer can be a single-layer structure or a multi-layer stacked structure of dielectric materials such as silicon oxide, aluminum oxide, and hafnium oxide. In an embodiment of the present invention, the gate insulation stack structure 5 is, for example, an ONO structure composed of silicon oxide, silicon nitride, and silicon oxide. The material of the first channel layer 6A can include semiconductor materials such as single crystal silicon, amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal germanium, SiGe, Si:C, SiGe:C, SiGe:H, etc., for subsequent etching The protective layer and the further deposited nucleation layer in the future have a thickness of, for example, 1-10 nm.

As shown in FIG. 2E, the first channel layer 6A and the gate insulating stack 5 at the bottom of the deep hole 4G are vertically anisotropically etched (such as the aforementioned fluorocarbon-based plasma dry etching or RIE) until the epitaxial channel is exposed. Layer 1E. At this time, on the side of the deep hole 4G, due to the protection of the first channel layer 6A (the thickness of the side of the layer 6A can be slightly reduced, for example, 1-4nm is left), the gate insulating stack 5 is not subject to lateral erosion, so The excessive surface defect density between the gate and the future gate is avoided, and the reliability of the device is improved.

As shown in FIG. 2F , the second channel layer 6B is epitaxially grown on the bottom and sidewalls of the deep hole 4G. Epitaxial processes such as MOCVD, MBE, ALD, etc., the material of the second channel layer 6B can be selected from the same materials as the first channel layer 6A, and can also be selected from group V, III-V or II-VI compound semiconductors , such as GeSn, InSn, InN, InP, GaN, GaP, GaSn, GaAs, etc. and combinations thereof. In an embodiment of the present invention shown in FIG. 2F , the deposition method of the second channel layer 6B is to partially fill the sidewall of the hole 4G to form a hollow column with an air gap 6C. In other embodiments not shown in the figures of the present invention, the deposition method of the channel layer 6B is selected to completely or partially fill the hole groove 4G to form a solid column, a hollow ring, or an insulating layer (not shown) filled in the hollow ring. core-shell structure. The shape of the horizontal section of the channel layer 6B is similar to that of the hole groove 4G and is preferably conformal, which can be a solid rectangle, square, rhombus, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon Shape, octagon, etc. various geometric shapes, or hollow annular, barrel-shaped structures evolved from the above geometric shapes (and the interior can be filled with an insulating layer). Preferably, for the hollow columnar channel layer 6B structure, an insulating isolation layer 6C can be further filled inside the channel layer 6B, for example, a layer 6C made of silicon oxide is formed by LPCVD, PECVD, HDPCVD, etc., for supporting, insulating And isolate the channel layer 6B.

Thereafter, a drain region 6D is deposited on top of the second channel layer 6B. Preferably, the material of the channel layer 6B is the same or similar (such as amorphous Si, polycrystalline Si, SiGe, SiC, etc., which are similar to Si, so as to fine-tune the lattice constant and improve the carrier mobility, thereby controlling the unit device. The driving performance) material is deposited on the top of the hole 4G to form the drain region 6D of the memory device unit transistor. Of course, if the channel layer 6B is a fully filled solid structure differently from that shown in FIG. 2F , then the portion of the channel layer 6B on the top of the entire device constitutes the corresponding drain region 6D without an additional drain region deposition step. In other embodiments of the present invention, the drain region 6D may also be metal, metal nitride, or metal silicide, forming a gold half-contact and forming a Schottky device on the top.

Next, a third insulating layer 7 (such as an interlayer dielectric layer, ILD) is formed on the entire device. Forming methods such as spin coating, spray coating, screen printing, CVD deposition, pyrolysis, oxidation, etc., materials such as silicon oxide or low-k materials, low-k materials include but are not limited to organic low-k materials (such as aryl or polycyclic ring-containing organic polymers), inorganic low-k materials (such as amorphous carbon-nitrogen films, polycrystalline boron-nitride films, fluorosilicate glass, BSG, PSG, BPSG), porous low-k materials (such as disilatrioxane (SSQ)-based porous Low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymer). Preferably, CMP planarizes the ILD 7 .

As shown in FIG. 2G, an anisotropic etching process is performed using a photoresist mask pattern (not shown), and the ILD 7, the second insulating layer stack 4A/4B, the floating gate layer 3, the first insulating layer are etched vertically in sequence. The layers are stacked 2A/2B/2C until the substrate 1 is exposed, forming a plurality of vertical openings 7T. In a plan view (not shown), a plurality of vertical openings 7T will surround each vertical channel 6A/6B/6C, for example, each vertical channel has an average of 2-6 vertical openings 7T around the periphery. The cross-sectional shape of the opening 7T may be the same as that of the deep hole 4G.

As shown in FIG. 2H , the second material layer 4B is selectively removed. Using an isotropic etching process, all the second material layers 4B in the second insulating layer stack 4 are removed, leaving only a plurality of first material layers 4A. Depending on the material of the layer 4A/layer 4B, a wet etching solution can be selected to etch and remove the layer 4B isotropically. Specifically, for the material of layer 4B, HF-based etching solution is used for silicon oxide material, hot phosphoric acid etching solution is used for silicon nitride material, and strong alkali etching solution such as KOH or TMAH is used for polycrystalline silicon or amorphous silicon material. In addition, oxygen plasma dry etching can also be used for the layer 4B of carbon-based materials such as amorphous carbon and DLC, so that O and C react to form a gas to be extracted. After removing the layer 4B, a plurality of lateral (horizontal direction parallel to the substrate surface) grooves 4R are left between the first material layers 4A for later formation of control electrodes. In a preferred embodiment of the present invention, the material of the middle layer 2B in the first insulating layer stack 2 is the same as that of the second material layer 4B, for example, both are silicon nitride, so they are also removed together in the process step shown in FIG. 2H , The recessed 2R on the side is exposed. Preferably, through thermal oxidation, chemical oxidation and other processes, an additional insulating isolation layer 2D is formed at the interface of the recess 2R close to the epitaxial channel layer 1E to serve as the gate insulating layer of the bottom selection gate BSG. Control the speed and time of isotropic etching, so that the insulating isolation layer 2D made of the first insulating layer material remains in the middle layer 2B near the interface of the epitaxial layer 1E (that is, the lateral etching depth of the middle layer 2B can be smaller than that of the second material layer 4B, especially when the middle layer 2B is doped with other elements compared with the second material layer 4B, for example, layer 4B is SiN, while layer 2B is SiN:O, SiN:C, SiN:F, etc.).

Subsequently, a common source 1S is formed in the opening 7T in the underlying substrate 1 . For example, an ion implantation process is used to vertically implant the bottom of the substrate 1 to form a plurality of common source 1S, and preferably further form a metal silicide (not shown) on the surface to reduce the surface contact resistance. Metal silicides such as NiSi _2-y , Ni _1-x Pt _x Si _2-y , CoSi _2-y or Ni _1-x Co _x Si _2-y , where x is greater than 0 and less than 1, and y is greater than or equal to 0 and less than 1. The common source region 1S and the substrate have different doping types, and are partially or completely separated by an insulating material, thereby forming different carrier paths for erasing, writing, and reading operations.

As shown in FIG. 2I, gate electrodes 8 are formed in a plurality of grooves 4R. The gate electrode 8 can be polysilicon, polysilicon germanium, or metal, wherein the metal can include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu , Nd, Er, La and other metal elements, or alloys of these metals and nitrides of these metals, the gate electrode 8 can also be doped with C, F, N, O, B, P, As and other elements to adjust the work function . A barrier layer (not shown) of high-k material or nitride is preferably formed between the gate dielectric layer 5 and the gate electrode 8 by conventional methods such as PVD, CVD, and ALD. The nitride material is, for example, M _x N _y , M _x Si _y N _z , M _x Aly _{N z} , _Ma Al _x Si _y N _z , wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements. Likewise, layer 8 may be a single-layer structure or a multi-layer stacked structure. As shown in Figure 2I and Figure 3, the gate electrode 8 wrapped in the first insulating layer stack 2 will be used as the bottom select gate BSG of the bottom device (the channel region of which is the epitaxial channel layer 1E), and in the second insulating layer stack 2 The gate electrode 8 wrapped in the first material layer 4A of the layer stack will serve as the dummy gate DG, the first to i-th and even the 32nd word lines WL0, WLi-1...WL31, and the top select gate TSG, respectively.

As shown in FIG. 2J , the opening 7T is filled with the lead-out structure 9 forming the source region 1S. For example, CVD or oxidation/nitridation process is used to form an insulating material layer, and anisotropic etching is performed to remove the bottom to expose the source electrode 1S to form a spacer wall 9A to avoid short-circuiting with the bit line electrode 8, followed by MOCVD, ALD, evaporation, sputtering Processes such as forming the source lead-out line 9B of metal material, its material such as metal, can include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu , Nd, Er, La and other metal elements, or alloys of these metals, and conductive nitrides or conductive oxides of these metals. Preferably, the CMP planarizes the leads 9A/9B until the ILD 7 is exposed.

As shown in FIG. 2K , the ILD 7 is etched until the drain region 6D is exposed, and a material similar to the lead-out line 9 is filled to form a bit-line lead-out line 10 (BL). The cross-sectional view of the finally realized device is shown in FIG. 2K. A three-dimensional semiconductor device includes a plurality of memory cells, and each of the plurality of memory cells includes: a channel layer 6A/6B/6C, along a direction perpendicular to the surface of the substrate 1 Distribution; the first insulating layer stack 2A/2C sandwiches a bottom gate conductive layer 8: BSG (bottom select gate), on the sidewall of the channel layer; multiple second insulating layers 4A are conductive to multiple gates Layer 8 (8: DG (dummy gate), 8: WL (word line), 8: TSG (top select gate), etc.), alternately stacked along the sidewall of the channel layer; gate dielectric layer 5A/5B /5C, located between the plurality of interlayer insulating layers and the sidewalls of the channel layer; the drain 6D, located on the top of the channel layer; and the source 1S, located between two adjacent memory cells of the plurality of memory cells In the substrate; wherein, a floating gate layer 3 (3: FG) is further included between the first insulating stack and the second insulating layer. Preferably, the substrate 1 has an epitaxial channel layer 1E located between the first insulating layer stacks 2 below the channel layer. Further preferably, the top of the epitaxial channel layer 1E is equal to or higher than the bottom of the floating gate layer 3 and lower than the top of the floating gate layer 3 . Preferably, the floating gate layer 3 is indented outward relative to the vertical axis of the channel layer, that is, the sidewall of the floating gate layer 3 is smaller than the sidewall of the bottom gate layer 8: BSG (or the sidewall of the epitaxial channel layer 1E). away from the vertical axis of the channel layer. The materials and structural features of other layers are as described in the process section, and will not be repeated here.

As shown in FIG. 3, it is a device structure manufactured according to another embodiment of the present invention. It is different from that shown in FIG. 2K only in that the recess of the floating gate layer 3 is not formed by the lateral etching process as shown in FIG. 2C. 3R, that is, the sidewall of the floating gate layer 3 may be flush with the sidewall of the bottom gate layer 8: BSG. In FIG. 3 , each insulating layer 4A, 2A, 2C, 2D, and 7 in FIG. 2K can be formed of the same material, so it can be simplified as 4A, but the gate insulating layer 5 still adopts a multilayer structure. The lead-out structure 9 in FIG. 3 also does not show the details of 9A/9B in FIG. 2K in detail.

As shown in FIG. 4 , it is a cross-sectional view of the peripheral connection line of the device according to the present invention, wherein each gate layer 8 (from the bottom BSG, DG, to the upper WL, TSG, etc.) is connected to the outside by the gate lead-out line 11, The provided floating gate 3 is not connected to the outside.

According to the three-dimensional semiconductor storage device and its manufacturing method of the present invention, the non-extracted floating gate is embedded inside, and the voltage is induced on the floating gate through the coupling of the voltage on the adjacent extraction gate level, thereby assisting in the completion of the SEG and the polysilicon contact area. Channel inversion, so as to overcome the current bottleneck in this region, increase the channel current, and effectively control the consistency of the threshold voltage of the tubes adjacent to the floating gate.

While the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structures or method flows without departing from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (16)

1. a kind of three-dimensional semiconductor device, including multiple storage units, each of multiple storage units include：

Channel layer, along the directional spreding perpendicular to substrate surface；

Bottom grid conductive layer is located in the first stacked dielectric layer, is distributed on the side wall of channel layer；

Floating gate layer is located on the first stacked dielectric layer, is distributed on the side wall of channel layer；

Multiple second insulating layers and multiple grid conducting layers, are located on floating gate layer, alternately laminated along the side wall of channel layer；

Gate dielectric layer is distributed on the side wall of channel layer；

Drain electrode is located at the top of channel layer；And

Source electrode is located in the substrate between the two neighboring storage unit of multiple storage units.

2. three-dimensional semiconductor device as described in claim 1, wherein each storage unit further comprises epi channels layer, Between the first stacked dielectric layer below channel layer.

3. three-dimensional semiconductor device as claimed in claim 2, wherein be equal to or higher than floating gate layer bottom at the top of epi channels layer Portion, and less than at the top of floating gate layer.

4. three-dimensional semiconductor device as described in claim 1, wherein floating gate layer is flushed with bottom grid conductive layer side wall, or Person extrapolates relative to channel layer.

5. three-dimensional semiconductor device as described in claim 1, wherein the cross sectional shape that channel layer is parallel to substrate surface includes Selected from rectangle, diamond shape, circle, semicircle, ellipse, triangle, pentagon, pentagon, hexagon, octagon and combinations thereof Geometry, and include the solid geometric figure to develop selected from the geometry, hollow annular geometric figure or The composite figure of hollow annular perisphere and insulating layer center.

6. three-dimensional semiconductor device as described in claim 1, wherein gate dielectric layer further comprise tunnel layer, accumulation layer, Barrier layer.

7. three-dimensional semiconductor device as described in claim 1, wherein channel layer includes the first channel layer, the second channel layer, ditch Road filled layer.

8. three-dimensional semiconductor device as claimed in claim 7, wherein the first channel layer and/or the second channel layer materials are selected from V Race's simple substance, V compounds of group, III-V compound, II-VI group compound semiconductor.

9. three-dimensional semiconductor device as claimed in claim 8, wherein first channel layer and/or the second channel layer materials Selected from single crystalline Si, amorphous Si, polycrystalline Si, crystallite Si, monocrystalline Ge, SiGe, Si:C、SiGe:C、SiGe:H、GeSn、InSn、InN、 InP, GaN, GaP, GaSn, GaAs's is any or combinations thereof.

10. three-dimensional semiconductor device as claimed in claim 7, wherein raceway groove filling layer material be air or oxide, Nitride.

11. three-dimensional semiconductor device as described in claim 1, wherein the gate dielectric layer includes high-g value.

12. three-dimensional semiconductor device as described in claim 1, wherein the bottom grid conductive layer or grid conducting layer material Matter be polysilicon, metal, metal nitride, metal silicide it is any or combinations thereof.

13. a kind of three-dimensional semiconductor device manufacturing method, including step：

It sequentially forms the first stacked dielectric layer, floating gate layer, second insulating layer on the substrate of memory cell areas to stack, wherein second Stacked dielectric layer includes multiple alternate first material layers and second material layer；

Etching forms multiple deep holes, until exposure substrate；

Gate dielectric layer and channel layer are formed on deep hole side wall and bottom；

It fills and forms drain electrode at the top of channel layer；

Selective etch removes second material layer, leaves the opening of multiple lateral grooves and exposure substrate；

Grid conducting layer is formed in multiple grooves；

Source electrode is formed in the substrate of open bottom.

14. three-dimensional semiconductor device manufacturing method as claimed in claim 13, wherein etching forms laggard the one of multiple deep holes Step includes being epitaxially grown on the substrate epi channels layer, floating gate layer bottom is equal to or higher than at the top of epi channels layer, and be less than At the top of floating gate layer.

15. three-dimensional semiconductor device manufacturing method as claimed in claim 13, wherein etching forms laggard the one of multiple deep holes Step includes lateral etching floating gate layer, forms the recess extrapolated from channel layer.

16. three-dimensional semiconductor device manufacturing method as claimed in claim 13, wherein selective etch removes second material layer While also eliminate the middle layer of the first stacked dielectric layer at least partly and leave lateral recesses, and be subsequently formed grid Bottom grid conductive layer is formed while the conductive layer of pole in lateral recesses.