CN105321494B - A kind of liquid crystal display panel - Google Patents

Abstract

The invention provides a liquid crystal display panel. The liquid crystal display panel is provided with a plurality of grid lines, and a gate driver is attached to one end of the grid lines, and two terminals are connected to the other end of each grid line in the display area. A correction TFT, and three power supply lines are arranged on the outside of the correction TFT: a first power line, a second power line and a third power line, wherein the source of RTx (x is an odd number) is connected to The second power supply wiring, the source of RTx (x is an even number) is connected to the third power supply wiring, the source of FTx is connected to the first power supply wiring, 1≤x≤m. The present invention adds a correction TFT and a power supply line to the remote side of the grid line, and cooperates with the control signal to enhance the remote waveform of the grid line, enhance the turn-on time of the remote gate line and shorten the turn-off time. This signal function can Improve the signal integrity of the remote grid traces, improve the display quality, and can be used in future low-cost, high-resolution and large-size panel applications.

Description

A liquid crystal display panel

technical field

The invention relates to the correction of driving signals of a liquid crystal display, in particular, a liquid crystal display panel with peripheral wiring is designed.

technical background

Existing liquid crystal display panels are getting bigger and bigger, the resolution is getting higher and higher, and the edge of the liquid crystal display panel is required to be small, so the wiring has to be thinner and thinner to improve the power consumption of the liquid crystal display panel. Polar signal distortion, which will cause low display quality of the LCD panel, such as uneven grid blocks, uneven left and right luminance, or insufficient charging.

FIG. 1 is a schematic diagram of the signal distortion caused by the in-plane remote wiring of the gate driver (Gate Driver) of a matrix thin film transistor liquid crystal display. It is assumed that two gate drivers 10 and 20 are provided on one side of the liquid crystal panel 100 (FIG. 1 indicates two gate drivers), the signal of the gate trace 1 far away from the gate driver 10 will be attenuated. Due to the high impedance of the power traces on the glass, the voltage of the first gate driver 10 is different from the voltage of the second gate driver 20, resulting in pixel distortion of the gate traces, so the charge of the liquid crystal pixels cannot be fully obtained. Similarly, this problem will cause unevenness, or even block unevenness.

That is to say, the normal scanning driving signal of the gate driver will gradually reduce the voltage along with the wiring of the liquid crystal panel 100, and the high frequency of the signal waveform will be gradually absorbed and distorted. Uneven block (Tape Mura).

In order to solve the problem of attenuation of the gate traces of the gate driver, a double-sided gate driver drive structure as shown in Figure 2 is adopted, but the cost is high, the edge area is large, and the manufacturing process is long.

Currently, for the distortion of gate traces, a chamfer circuit is generally used, that is, the output signal of the gate driver is distorted, and the end of the de-detection signal after passing through the gate traces is also distorted. The difference between the near-end and remote signal distortion Smaller, improved uniformity. However, there is a problem with this angle-cutting circuit, that is, the shorter the charging time is, the shorter the charging time is, and it is more difficult to implement the angle-cutting circuit for the application of large-size and high-resolution liquid crystal displays.

Contents of the invention

The object of the present invention is to provide a liquid crystal display panel which improves the display uniformity of the liquid crystal display panel and increases the charging time.

The invention provides a liquid crystal display panel. The liquid crystal display panel is provided with a plurality of grid wirings, and the grid wirings located in the display area of the liquid crystal display panel are sequentially: the first grid wiring G1, the second grid wiring Gate lines G2, ..., the m-th gate line Gm, a gate driver is attached to one end of the gate line, and two correction TFTs are connected to the other end of each gate line in the display area, and at the same time Three power supply lines are arranged on the outside of the correction TFT: a first power supply line, a second power supply line and a third power supply line, and multiple correction TFTs are numbered sequentially from top to bottom in the display area of the liquid crystal display panel are RT1, FT2, ..., RT m, FT(m+1), where the source of RTx (x is an odd number) is connected to the second power supply trace, and the source of RTx (x is an even number) is connected to the third power supply Wires, the source of FTx is connected to the first power wire, 1≤x≤m.

Wherein, the non-display area of the liquid crystal display panel also has at least one gate line located at both ends of the display area, labeled as: the 0th gate line G0 and the (m+1)th gate line G(m+ 1), the other end of the 0th gate line G0 is connected to a correction TFT, labeled FT0; the other end of the (m+1) gate line G(m+1) is connected to a correction TFT, labeled as FT(m+1).

Among them, the gate of FT0 is connected to the first gate line G1; the gate of RT1 is connected to the 0th gate line G0, the gate of FT1 is connected to the second gate line G2; the gate of RT2 The pole is connected to the first gate line G1; the gate of FT2 is connected to the third gate line G3; ...; the gate of RTx is connected to the (x-1)th gate line G(x- 1), the gate of FTx is connected to the (x+1)th gate line G(x+1); ...; the gate of RT(m+1) is connected to the mth gate line Gm; FT0 The drain of RT1 is connected to the 0th gate G0; the drain of RT1 and the drain of FT1 are connected to the first gate G1, the drain of RT2 and the drain of FT2 are connected to the second gate Go G2;...; Both the drain of RTx and the drain of FTx are connected to the xth gate and go Gx;...; The drain of RT(m+1) is connected to the (m+1)th gate and go G( m+1).

Wherein, the first power line inputs a first voltage signal, and the voltage amplitude of the first voltage signal is VGL'-VGL; the second power line inputs a second voltage signal, and the voltage amplitude of the second voltage signal is VGH-VGL ; The third power line inputs a third voltage signal, and the voltage amplitude of the third voltage signal is VGH-VGL.

Wherein, the voltage value of VGH>the voltage value of VGL'>the voltage value of VGL.

Wherein, the Duty of the first voltage signal is located between the corresponding gate wiring from the high voltage VGH to the low voltage VGL; the Duty of the second voltage signal and the third voltage signal is located between the corresponding gate wiring from the low voltage VGL to the low voltage VGL. into a high voltage between VGH.

Wherein, the frequency of the first voltage signal is related to the scanning frequency of the gate wiring, and the frequency of the second voltage signal and the frequency of the third voltage signal are both related to half of the scanning frequency of the gate wiring.

Wherein, the voltage of the correcting TFT is controlled by a bit shift circuit, and the control signal of the bit shift circuit is output and controlled by a timing controller, and the timing controller controls the output control signal, and then the control signal is input to the gate of the bit shift circuit. Pole signal, the VGH_VGL voltage amplitude of the gate line is adjusted by both VG_H and VG_L of the bit shift circuit.

Among them, the frequency and Duty of the bit shift circuit are controlled by the gate signal.

The present invention adds a correction TFT and a power supply line to the remote side of the grid line, and cooperates with the control signal to enhance the remote waveform of the grid line, enhance the turn-on time of the remote gate line and shorten the turn-off time. This signal function can Improve the signal integrity of the remote grid traces, improve the display quality, and can be used in future low-cost, high-resolution and large-size panel applications.

Description of drawings

FIG. 1 is a schematic diagram of grid line distortion of an existing liquid crystal display;

FIG. 2 is a schematic structural diagram of a gate bilateral drive of an existing liquid crystal display;

FIG. 3 is a schematic structural view of the first embodiment of the liquid crystal display panel of the present invention;

Fig. 4 shows the structural representation of the second embodiment of the liquid crystal display panel of the present invention

FIG. 5 is a schematic structural view of a third embodiment of a liquid crystal display panel of the present invention;

FIG. 6 is a schematic structural diagram of the above-mentioned driving circuit of FIG. 5 .

Detailed ways

FIG. 3 is a schematic structural view of the first embodiment of the liquid crystal display panel of the present invention. The present invention improves the falling edge of the gate scanning drive signal. The sequence is: the 0th gate line G0, the 1st gate line G1, the 2nd gate line G2, . . . , and so on.

On the right side of the liquid crystal display panel, a correction TFT is arranged on each gate trace, and at the same time, a power supply trace WL is arranged on the right side of the liquid crystal display panel. The size of the TFT needs to be determined according to the characteristics of the liquid crystal display panel. For FT1, FT2, FT3, ... in the 0th gate line G0, the 1st gate line G1, and the 2nd gate line G2, ..., where the gate of FT1 is connected to the first line Gate trace G1; the gate of FT2 is connected to the second gate trace G2; ..., and so on; the drain of FT1 is connected to the 0th gate trace G0; the drain of FT2 is connected to the 1st gate trace G0; Gate trace G1; ..., and so on, the source of FT1, the source of FT2, the source of FT3, ..., are connected to the power trace WL, and the power trace WL inputs a specific voltage signal, this The amplitude VGL'-VGL of the voltage signal is related to the frequency of the gate scan driving signal. When the 1st gate trace is turned on by the gate driver 30, this signal will turn on the FT1 switch at this time, allowing the right voltage signal to be connected to the 0th gate trace, which is helpful for the 0th gate trace off, and so on.

FIG. 4 is a schematic structural view of the second embodiment of the liquid crystal display panel of the present invention, which also improves the rising edge of the gate scanning drive signal. The sequence is: the 0th gate line G0, the 1st gate line G1, the 2nd gate line G2, ..., and so on.

On the right side of the liquid crystal display panel, a correction TFT is arranged on each gate line, and at the same time, a power supply line WO and a power supply line WE are arranged on the right side of the liquid crystal display panel. The size of the correction TFT depends on the characteristics of the liquid crystal display panel Determined, sequentially labeled as RT1, RT2, RT3, ..., etc. in the first gate line G1, the second gate line G2, the third gate line G3, ..., where the gate of RT1 Connect to the 0th gate line G0; the gate of RT2 is connected to the first gate line G1, the gate of RT3 is connected to the second gate line G2, ..., and so on.

The sources of RT1, RT3, RT5, ..., etc. in odd-numbered columns are all connected to the power supply line WO. The power supply line WO inputs a specific voltage signal SO, and the amplitude of the voltage signal SO VGH-VGL, its frequency is related to half of the gate scanning drive signal; the source of the even-numbered RT2, RT4, RT6, etc. are all connected to the power supply line WE, and the power supply line WE needs to input a specific voltage signal SE, and the amplitude VGH-VGL of this voltage signal SE is related to half of the gate scan driving signal. When the 0th gate trace G0 is turned on by the gate driver, this signal will turn on the RT1 switch at this time, so that the voltage signal SO of the right power supply trace WO is connected to the 1st gate trace, which is helpful for the 1st gate trace 1 gate trace is turned on; when the first gate trace G1 is turned on by the gate driver, this signal will turn on the RT2 switch at this time, so that the voltage signal SE of the right power supply trace WE is connected to the second gate The pole trace, G2, helps the second gate trace, G2, to turn on, and so on.

Figure 5 is a schematic structural diagram of the third embodiment of the liquid crystal display panel of the present invention, which is also the technical solution to be protected by the present invention. The third embodiment includes two parts, the first part is the internal wiring configuration of the liquid crystal display panel, and the second Part of the drive circuit part (as shown in Figure 6).

The wiring configuration inside the liquid crystal display panel is shown in FIG. 5 . By combining the first embodiment shown in FIG. 3 and the second embodiment shown in FIG. 4 , a plurality of gate wiring Gs are arranged in the liquid crystal display panel, A general gate driver 30 is mounted on one end of the gate trace (ie: the left side of the gate trace), and the gate traces are in sequence: the 0th gate trace G0, the 1st gate trace Trace G1, the second gate trace G2, ..., the mth gate trace Gm, the (m+1)th gate trace G(m+1), m≥1, wherein, the The 0th gate line G0 and the (m+1)th gate line G(m+1) are located in the non-display area of the liquid crystal display panel, and the middle 1-m gate line is located in the liquid crystal display panel display area.

Of course, the non-display areas at both ends may also have two or more gate lines respectively, which is determined according to the characteristics of the liquid crystal display panel.

The other ends of the 0th grid line G0 and the (m+1)th gate line G(m+1) in the non-display area of the liquid crystal display panel are both connected to a correction TFT, and in the display area of the liquid crystal display panel The other end of each gate trace is connected to two correction TFTs, and three power supply traces are arranged on the outside of the correction TFT: a first power trace WL, a second power trace W0 and a third power trace WE, multiple correction TFTs are labeled FT0, RT1, FT1, RT2, FT2, ..., RT m, FTm, RT(m+1) from top to bottom, where the 0th gate line G0 and the The correction TFTs arranged on the right side of the (m+1) gate lines G(m+1) are respectively FT0 and RT(m+1), and the xth gate line Gx in the display area of the liquid crystal display panel Two correcting TFTs are arranged on the right, respectively RT x and FTx, where 1≤x≤m.

Wherein, the size of the correcting TFT needs to be determined according to the characteristics of the liquid crystal display panel.

Wherein, the first power line WL inputs a specific first voltage signal SL, the voltage amplitude of the first voltage signal SL is VGL'-VGL, its frequency is related to the scanning frequency of the gate line, and its Duty (high voltage VGL 'interval) is adjusted according to the characteristics of the liquid crystal panel, Duty is located between the corresponding gate wiring from high voltage VGH to low voltage VGL; the second power supply wiring WO inputs a specific second voltage signal SO, the second The voltage amplitude of the voltage signal SO is VGH-VGL, and its frequency is related to half of the scanning frequency of the gate line. Its Duty (high voltage VGH interval) is adjusted according to the characteristics of this LCD panel. VGL becomes between the high voltage VGH; the third power line WE inputs a specific third voltage signal SE, the voltage amplitude of this third voltage signal SE is VGH-VGL, and its frequency is related to half of the scanning frequency of the gate line , the Duty (high voltage VGH interval) is adjusted according to the panel characteristics, and the Duty is located between the corresponding gate traces changing from low voltage VGL to high voltage VGH.

Among them, the gate turn-on voltage of the correction TFT (FT0, RT1, FT1, RT2, FT2, ..., RT m, FTm, RT(m+1)) is VGH, and the correction TFT (FT0, RT1, FT1, RT2, FT2, ..., RT m, FTm, RT(m+1)) have gate-off voltage VGL, FTx gate half-off voltage VGL', 1≤x≤m, and the voltage value is: VGH voltage value>VGL' The voltage value of VGL > the voltage value of VGL, wherein the voltage values of VGH, VGL and VGL' are determined according to the characteristics of the correction TFT.

Among them, the gate of FT0 is connected to the first gate line G1; the gate of RT1 is connected to the 0th gate line G0, the gate of FT1 is connected to the second gate line G2; the gate of RT2 The pole is connected to the first gate line G1; the gate of FT2 is connected to the third gate line G3; ...; the gate of RTx is connected to the (x-1)th gate line G(x- 1), the gate of FTx is connected to the (x+1)th gate line G(x+1); ...; the gate of RT(m+1) is connected to the mth gate line Gm.

Among them, the source of FT0 is connected to the first power supply line WL; the source of RT1 is connected to the second power supply line WO, the source of FT1 is connected to the first power supply line WL; the source of RT2 is connected to the third power supply Wire WE, the source of FT2 is connected to the first power wire WL; the source of RT3 is connected to the second power wire WO, the source of FT3 is connected to the first power wire WL; the source of RT4 is connected to the second power wire Three power supply lines WE, the source of FT4 is connected to the first power supply line WL; ...; the source of RTx (x is an odd number) is connected to the second power supply line WO, and the source of RTx (x is an even number) is connected to The source of the third power wire WE, FTx is connected to the first power wire WL.

Among them, the drain of FT0 is connected to the 0th gate G0; the drain of RT1 and the drain of FT1 are connected to the first gate G1, and the drain of RT2 and the drain of FT2 are connected to the 2nd gate. The first gate goes to G2; ...; the drain of RTx and the drain of FTx are connected to the xth gate and goes to Gx; ...; the drain of RT(m+1) is connected to the (m+1)th gate Go G(m+1).

When the gate line G1 is at the low voltage VGL, the VGL voltage will turn off FT1 and RT1 at this time, forming the high impedance characteristics of FT1 and RT1 as if it is an open circuit; when the gate line G0 changes from VGL to VGH, the VGH voltage will be FT1 and RT1 are turned on, the source of FT0 is connected to the first power supply line WL, the drain of FT0 is connected to the gate line G0, the drain of FT0 is connected to the source, and the gate line G0 is connected to the external first line. The voltage value of a power trace WL; the source of RT2 is connected to the third power trace WE, the drain of RT2 is connected to the gate trace G2, the drain of RT2 is connected to the source, and the gate trace G2 is connected To the voltage value of the external third power supply line WE; when the gate line G1 changes from VGH to VGL, the VGL voltage will turn off FT1 and RT1 at this time, forming the high impedance characteristics of FT1 and RT1 like an open circuit; ..., and so on.

FIG. 6 is a schematic structural diagram of the above-mentioned drive circuit in FIG. 5, and the voltages of the corrected TFTs (FT1, RT1, FT2, ..., RT m, FT (m+1)) are all generated by a bit shift circuit 100. The control signal of the bit shift circuit 100 is controlled by the output of the timing controller (TCON), and both the bit shift circuit 100 and the timing controller (TCON) are provided in the source driver of the liquid crystal display panel.

The output control signal is controlled by the timing controller (TCON), and then the control signal is input to the gate signal (Gate Signal) of the bit shift circuit 100. The VGH_VGL voltage amplitude of the gate line is determined by the VG_H and VG_L of the bit shift circuit or to adjust the size, its frequency and Duty (high voltage range) are controlled by the gate signal (Gate Signal).

Firstly, the present invention improves the grid line distortion problem and improves the display uniformity of liquid crystal panels. The present invention is especially applicable to large-size and high-resolution liquid crystal display panels; secondly, the present invention can increase the The opening and closing speed of the gate signal is fast, which improves the charging rate; finally, the opening and closing of the gate signal of the present invention increases the high-current routing path and the number of terminals in contact increases, which improves reliability.

The present invention adds a correction TFT and a power supply line to the remote side of the grid line, and cooperates with the control signal to enhance the remote waveform of the grid line, enhance the turn-on time of the remote gate line and shorten the turn-off time. This signal function can Improve the signal integrity of the remote grid traces, improve the display quality, and can be used in future low-cost, high-resolution and large-size panel applications.

Claims (7)

1. A liquid crystal display panel, the liquid crystal display panel is provided with a plurality of grid lines, and the grid lines positioned in the display area of the liquid crystal display panel are sequentially: the first grid line G1, the second grid line Pole traces G2, ..., m-th gate traces Gm, a gate driver is mounted on one end of the gate traces, and the feature is that two corrections are connected to the other end of each gate trace in the display area TFT, at the same time arrange three power lines on the outside of the correction TFT: a first power line, a second power line and a third power line, multiple correction TFTs are arranged from top to bottom in the display area of the liquid crystal display panel Sequentially labeled as RT1, FT2, ..., RT m, FT(m+1), where the source of RTx (x is an odd number) is connected to the second power supply line, and the source of RTx (x is an even number) is connected to The third power line, the source of FTx is connected to the first power line, 1≤x≤m; the first power line inputs a first voltage signal, and the voltage amplitude of the first voltage signal is VGL'-VGL; The second power line inputs a second voltage signal, and the voltage amplitude of the second voltage signal is VGH-VGL; the third power line inputs a third voltage signal, and the voltage amplitude of the third voltage signal is VGH-VGL; the first voltage The frequency of the signal is related to the scanning frequency of the gate line, and the frequency of the second voltage signal and the frequency of the third voltage signal are both related to half of the scanning frequency of the gate line. 2. The liquid crystal display panel according to claim 1, characterized in that: the non-display area of the liquid crystal display panel also has at least one gate line located at both ends of the display area, and the labels are: the 0th gate line G0 and The (m+1)th gate line G(m+1), the other end of the 0th gate line G0 is connected to a correction TFT, labeled FT0; the (m+1)th gate line G The other end of (m+1) is connected with a correction TFT, labeled as FT(m+1). 3. The liquid crystal display panel according to claim 2, wherein the gate of FT0 is connected to the first gate line G1; the gate of RT1 is connected to the 0th gate line G0, and the gate of FT1 The pole is connected to the second gate line G2; the gate of RT2 is connected to the first gate line G1; the gate of FT2 is connected to the third gate line G3; ...; the gate of RTx is connected to The (x-1)th gate trace G(x-1), the gate of FTx is connected to the (x+1)th gate trace G(x+1);...;RT(m+1) The gate of FT0 is connected to the mth gate line Gm; the drain of FT0 is connected to the 0th gate line G0; the drain of RT1 and the drain of FT1 are connected to the first gate line G1, and the drain of RT2 Both the drain and the drain of FT2 are connected to the second gate G2; ...; the drain of RTx and the drain of FTx are connected to the xth gate Gx; ...; the drain of RT(m+1) The pole is connected to the (m+1)th gate line G(m+1). 4. The liquid crystal display panel according to claim 1, wherein the voltage value of VGH>the voltage value of VGL'>the voltage value of VGL. 5. The liquid crystal display panel according to claim 1, characterized in that: the Duty of the first voltage signal is located between the corresponding gate wiring from the high voltage VGH to the low voltage VGL; the second voltage signal and the third voltage The Duty of the signal is located between the corresponding gate line from the low voltage VGL to the high voltage VGH. 6. The liquid crystal display panel according to claim 5, characterized in that: the voltage of the correcting TFT is controlled by a bit shift circuit, the control signal of the bit shift circuit is output by a timing controller, and the timing controller controls The control signal is output, and then the control signal is input to the gate signal of the bit shift circuit. The VGH_VGL voltage amplitude of the gate line is adjusted by both VG_H and VG_L of the bit shift circuit. 7. The liquid crystal display panel according to claim 6, wherein the frequency and duty of the bit shift circuit are controlled by gate signals.