CN107293267B - Display panel and control method of display panel grid signals - Google Patents
Display panel and control method of display panel grid signals Download PDFInfo
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- CN107293267B CN107293267B CN201710592931.9A CN201710592931A CN107293267B CN 107293267 B CN107293267 B CN 107293267B CN 201710592931 A CN201710592931 A CN 201710592931A CN 107293267 B CN107293267 B CN 107293267B
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000008859 change Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 14
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a display panel and a control method of a display panel grid signal, wherein the display panel comprises: a gate driving substrate; a plurality of gate driving units; the potential shifter is electrically connected with the plurality of grid driving units; the control end of the driving circuit is connected with the output end of the potential shifter and is used for controlling the conduction and the closing of the input end and the output end of the driving circuit, and the output end of the driving circuit is connected with the row pixel units of the grid driving substrate through the grid driving unit; and the output end of the voltage control circuit is connected with the input end of the driving circuit, and the voltage control circuit sets different output voltages to be input into the input end of the driving circuit according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row. When the CK waveforms output by the potential shifter are transmitted to the pixel units in each row, the CK waveforms acquired by the pixel units in each row are basically consistent.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of display, in particular to a display panel and a control method of a display panel grid signal.
[ background of the invention ]
The conventional Display panel mainly includes a Liquid Crystal Display (LCD) Display panel and an Organic Light Emitting Diode (OLED) Display panel. Among them, the OLED display panel has many advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of approximately 180 °, a wide temperature range, and capability of implementing flexible display and large-area full-color display, and is considered as the display panel with the most potential development in the industry.
The Gate On Array (GOA) uses TFT lines inside the TFT-LCD and Level Shifter IC on the CB to generate the required Gate signals, and this method can effectively omit the Gate IC and reduce the cost.
However, this method may suffer from parasitic resistance and capacitance generated by the internal wiring of the IC, and particularly, the resistance at the far end and the resistance at the near end may have great difference, which results in great difference between the far end and the near end of the gate signal finally entering the panel.
[ summary of the invention ]
An object of the present invention is to provide a display panel, which can reduce the difference between the far and near ends of the gate signals inside the panel and has a lower cost.
Another objective of the present invention is to provide a method for controlling gate signals of a display panel, which can reduce the difference between the gate signals inside the display panel at the far end and the near end, and has a lower cost.
To solve the above problems, a preferred embodiment of the present invention provides a display panel including:
the grid driving substrate comprises a pixel array area and a circuit placing area positioned on the side edge of the pixel array area, wherein the pixel array area comprises a plurality of rows of pixel units;
the grid driving units are arranged on the circuit placing area and used for outputting scanning signals to the row pixel units in the pixel array area;
the potential shifter is electrically connected with the plurality of grid driving units and used for outputting control signals;
the driving circuit comprises an input end, an output end and a control end, the control end of the driving circuit is connected with the output end of the potential shifter and is used for controlling the on and off of the input end and the output end of the driving circuit, and the output end of the driving circuit is connected with the row pixel units through the grid driving unit;
the output end of the voltage control circuit is connected with the input end of the driving circuit, and the voltage control circuit sets different output voltages to be input into the input end of the driving circuit according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
In the display panel according to the preferred embodiment of the present invention, the voltage control circuit includes a digital-to-analog converter and an adder, an output terminal of the adder is connected to an input terminal of the driving circuit, a first input terminal of the adder is connected to the reference voltage, and a second input terminal of the adder is connected to the digital-to-analog converter;
and the digital-to-analog converter sets different adjusting voltages according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
In the display panel according to the preferred embodiment of the present invention, the driving circuit includes a PMOS transistor and an NMOS transistor, a control end of the PMOS transistor is connected to an output end of the potential shifter, and an output end of the PMOS transistor is connected to an output end of the driving circuit;
the control end of the NMOS tube is connected with the output end of the potential translator, and the output end of the NMOS tube is connected with the voltage control circuit;
the input end of the PMOS tube is connected with the output end of the voltage control circuit, and/or the input end of the NMOS tube is connected with the output end of the drive circuit, and the PMOS tube and the NMOS tube are used for setting different adjusting voltages according to the row pixel units corresponding to the output signal of the output end of the drive circuit, so that the on-off speed of the PMOS tube and the NMOS tube is increased row by row.
In the display panel of the preferred embodiment of the present invention, the voltage control circuit includes a digital voltage generator, an output terminal of the digital voltage generator is connected to an input terminal of the driving circuit;
and the digital voltage generator sets different output voltages according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
In the display panel according to the preferred embodiment of the present invention, the driving circuit includes a PMOS transistor and an NMOS transistor, a control end of the PMOS transistor is connected to an output end of the potential shifter, and an output end of the PMOS transistor is connected to an output end of the driving circuit;
the control end of the NMOS tube is connected with the output end of the potential translator, and the output end of the NMOS tube is connected with the voltage control circuit;
the digital voltage generator comprises a first output end and a second output end which are respectively connected with the input end of the PMOS tube and the input end of the NMOS tube and used for setting different output voltages according to the row pixel units corresponding to the output signal of the output end of the driving circuit, so that the on-off speed of the PMOS tube and the NMOS tube is increased row by row.
In order to solve the above problems, a preferred embodiment of the present invention further provides a method for controlling a gate signal of a display panel, where the display panel includes a gate driving substrate, a plurality of gate driving units, a potential shifter, and a driving circuit; the gate driving substrate comprises a pixel array area and a circuit placing area positioned on the side edge of the pixel array area, and the pixel array area comprises a plurality of rows of pixel units; the plurality of gate driving units are arranged on the circuit placing area and used for outputting scanning signals to the row pixel units of the pixel array area;
the control method comprises the following steps:
electrically connecting the potential shifter with the plurality of gate driving units for outputting control signals;
connecting the control end of the driving circuit with the output end of the potential translator, controlling the on and off of the input end and the output end of the driving circuit, and connecting the output end of the driving circuit with the row pixel units through a grid driving unit;
and controlling the voltage change of the input end of the driving circuit according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
In the method for controlling a gate signal of a display panel according to a preferred embodiment of the present invention, the method further includes:
inputting a reference voltage into a first input end of an adder, setting an adjusting voltage according to a row pixel unit corresponding to an output signal of an output end of the driving circuit, inputting the adjusting voltage into a second input end of the adder, and connecting an output end of the adder with a control end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased line by line.
In the method for controlling a gate signal of a display panel according to a preferred embodiment of the present invention, the method further includes:
the drive circuit comprises a PMOS tube and an NMOS tube, the control end of the PMOS tube is connected with the output end of the potential translator, and the output end of the PMOS tube is connected with the output end of the drive circuit;
the control end of the NMOS tube is connected with the output end of the potential translator, and the output end of the NMOS tube is connected with the voltage control circuit;
when the PMOS tube is opened, inputting an adjusting voltage which is a negative voltage into a second input end of the adder, wherein the adjusting voltage is gradually reduced;
when the NMOS tube is opened, the adjusting voltage which is positive voltage is input into the second input end of the adder, and the adjusting voltage is gradually increased.
In the method for controlling a gate signal of a display panel according to a preferred embodiment of the present invention, the method further includes:
and setting different input voltages of the driving circuit by using a digital voltage generator according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
In the method for controlling a gate signal of a display panel according to a preferred embodiment of the present invention, the method further includes:
the drive circuit comprises a PMOS tube and an NMOS tube, the control end of the PMOS tube is connected with the output end of the potential translator, and the output end of the PMOS tube is connected with the output end of the drive circuit;
the control end of the NMOS tube is connected with the output end of the potential translator, and the output end of the NMOS tube is connected with the voltage control circuit;
respectively connecting a first output end and a second output end of the digital voltage generator with an input end of the PMOS tube and an input end of the NMOS tube;
when the PMOS tube is opened, controlling the output voltage of the first output end of the digital voltage generator to gradually decrease;
and when the NMOS tube is opened, controlling the output voltage of the second output end of the digital voltage generator to be gradually increased.
Compared with the prior art, the invention has the beneficial effects that: the voltage control circuit sets different output voltages to be input into the input end of the driving circuit according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased line by line. When CK waveforms output by the potential shifter and corresponding to the row pixel units in each row are transmitted to the row pixel units in each row, the CK waveforms acquired by the row pixel units in each row are basically consistent, the voltage of grid signals of the grid driving substrate on the row pixel units in each row is consistent, and the problems of color cast, uneven brightness and the like are solved.
In order to make the aforementioned and other objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below:
[ description of the drawings ]
FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of waveforms generated by the potential shifter according to the embodiment of the present invention;
FIG. 3 is a schematic diagram of the waveform of FIG. 2 after it reaches the panel;
FIG. 4 is a schematic diagram of waveforms controlled by the voltage control circuit according to the embodiment of the present invention;
FIG. 5 is a diagram of a driving circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a voltage control circuit according to an embodiment of the present invention;
FIG. 7 is another schematic diagram of a voltage control circuit according to an embodiment of the present invention;
FIG. 8 is a flowchart illustrating a method for controlling gate signals of a display panel according to an embodiment of the present invention.
[ detailed description ] embodiments
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
In the drawings, elements having similar structures are denoted by the same reference numerals.
A display panel and a manufacturing process thereof according to an embodiment of the invention are described below with reference to fig. 1 to 8.
According to an embodiment of the invention, as shown in fig. 1 to 8, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the invention; FIG. 2 is a schematic diagram of waveforms generated by the potential shifter according to the embodiment of the present invention; FIG. 3 is a schematic diagram of the waveform of FIG. 2 after it reaches the panel; FIG. 4 is a schematic diagram of waveforms controlled by the voltage control circuit according to the embodiment of the present invention; FIG. 5 is a diagram of a driving circuit according to an embodiment of the present invention; FIG. 6 is a schematic diagram of a voltage control circuit according to an embodiment of the present invention; FIG. 7 is another schematic diagram of a voltage control circuit according to an embodiment of the present invention; FIG. 8 is a flowchart illustrating a method for controlling gate signals of a display panel according to an embodiment of the present invention.
As shown in fig. 1, the embodiment of the invention discloses a display panel, which includes a gate driving substrate 100, a plurality of gate driving units 130, a potential shifter 140, a driving circuit 150 and a voltage control circuit 160. Wherein
The gate driving substrate 100 includes a pixel array region 110 and a circuit placement region 120 located at a side of the pixel array region, where the pixel array region 110 includes a plurality of rows of pixel units. A plurality of gate driving units 130 are disposed on the circuit placing region 120 for outputting scanning signals to the row pixel units of the pixel array region 110. The potential shifter 140 is electrically connected to the gate driving units 130, and is configured to output a control signal.
The driving circuit 150 includes an input terminal, an output terminal, and a control terminal, the control terminal of the driving circuit 150 is connected to the output terminal of the potential shifter 140 for controlling the on and off of the input terminal and the output terminal of the driving circuit, and the output terminal of the driving circuit 150 is connected to the row pixel units through the gate driving unit 130.
The output end of the voltage control circuit 160 is connected to the input end of the driving circuit 150, and the voltage control circuit 160 sets different output voltages to be input to the input end of the driving circuit 150 according to the row pixel units corresponding to the output signal of the output end of the driving circuit 150, so that the on-off speed of the input end and the output end of the driving circuit 150 is increased row by row.
The voltage control circuit 160 of this embodiment sets different output voltages to be input to the input terminal of the driving circuit according to the row pixel units corresponding to the output signals of the output terminal of the driving circuit, so that the on-off speeds of the input terminal and the output terminal of the driving circuit are increased row by row. When the CK waveforms output by the potential shifter 140 and corresponding to the row pixel units in each row are transmitted to the row pixel units in each row, the CK waveforms acquired by the row pixel units in each row are basically consistent, so that the gate signal voltages of the gate driving substrate 100 opened by the row pixel units in each row are consistent, and the problems of color cast, uneven brightness and the like are solved.
Taking HD (High Definition) model as an example, 768 pulses, which are required for generating a panel altogether by 4CK, are consistent in waveform as shown in fig. 2. As shown in FIG. 3, the CK waveforms used in each row of the panel have increasingly different pulse waveforms in different rows. It can be seen that the longer the trace is within the panel, i.e., the far end, the more distorted the waveform of CK.
As shown in fig. 4, in the present embodiment, when the CK output is changed from one CK line to another by using the internal compensation function of the Level Shifter (Level Shifter), the impedance matching is adjusted so that the output of the Level Shifter first line substantially matches the waveform actually applied to the panel of the last line.
Wherein the circuit placing region 120 may be disposed at one side or both sides of the pixel array region 110.
As shown in fig. 5 and 6, the voltage control circuit 160 includes a digital-to-analog converter (DAC)162 and an adder 161, an output terminal of the adder 161 is connected to an input terminal of the driving circuit, a first input terminal of the adder 161 is connected to the reference voltage, and a second input terminal of the adder 161 is connected to the digital-to-analog converter 162;
the digital-to-analog converter 162 sets different adjustment voltages according to the row pixel units corresponding to the output signal of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
Further, the driving circuit includes a PMOS transistor and an NMOS transistor, a control end of the PMOS transistor is connected to the output end of the potential shifter 140, and an output end of the PMOS transistor is connected to the output end of the driving circuit;
the control end of the NMOS transistor is connected to the output end of the potential shifter 140, and the output end of the NMOS transistor is connected to the voltage control circuit 160;
the input end of the PMOS tube is connected with the output end of the voltage control circuit 160, and/or the input end of the NMOS tube is connected with the output end of the driving circuit, and the PMOS tube and the NMOS tube are used for setting different adjusting voltages according to the row pixel units corresponding to the output signal of the output end of the driving circuit, so that the on-off speed of the PMOS tube and the NMOS tube is increased row by row.
Different impedance settings can be realized by controlling the Gate voltage of the MOS tube, when pixel units in different rows are opened, different voltages are generated by using the DAC to add Vref reference voltage to generate a required V _ Gate signal, the DAC is in negative pressure for opening the PMOS tube, the opening and closing speed of each row is gradually increased, the opening of the NMOS tube is in positive pressure, and the opening and closing speed of the lower tube is gradually increased.
As shown in fig. 5 and 7, the voltage control circuit 160 includes a digital voltage generator 163, and an output terminal of the digital voltage generator 163 is connected to an input terminal of the driving circuit;
the digital voltage generator 163 sets different output voltages according to the row pixel units corresponding to the output signal of the output terminal of the driving circuit, so that the on-off speed of the input terminal and the output terminal of the driving circuit is increased row by row.
Further, the driving circuit includes a PMOS transistor and an NMOS transistor, a control end of the PMOS transistor is connected to the output end of the potential shifter 140, and an output end of the PMOS transistor is connected to the output end of the driving circuit;
the control end of the NMOS transistor is connected to the output end of the potential shifter 140, and the output end of the NMOS transistor is connected to the voltage control circuit 160;
the digital voltage generator 163 includes a first output terminal and a second output terminal, which are respectively connected to the input terminal of the PMOS transistor and the input terminal of the NMOS transistor, and configured to set different output voltages according to the row pixel units corresponding to the output signal of the output terminal of the driving circuit, so that the turn-on and turn-off speeds of the PMOS transistor and the NMOS transistor are increased row by row.
Setting a 1024(10bits) voltage in the VGH-VGL, and controlling different opening speeds by controlling different bits numbers of the PMOS tube to open, thereby realizing the same compensation effect as the embodiment, namely, when the PMOS tube is opened, the output voltage bit number is gradually reduced, the impedance is reduced, the switching speed is increased, when the NMOS tube is opened, the output bit number is gradually increased, the impedance is also reduced, and the switching speed is increased. Of course, other digital voltage generators 163 with other numbers of bits, such as 9 bits, 11 bits, 12 bits, 15 bits, etc., may be used.
The above embodiment may start with the first row, the switching speed is slow, and then gradually increase the switching speed to make the Gate voltages turned on in each row consistent, by which the problems of color shift, uneven brightness (mura), etc. may be solved.
As shown in fig. 8, an embodiment of the present invention further discloses a method for controlling a gate signal of a display panel, where the display panel includes a gate driving substrate, a plurality of gate driving units, a potential shifter, and a driving circuit; the gate driving substrate comprises a pixel array area and a circuit placing area positioned on the side edge of the pixel array area, and the pixel array area comprises a plurality of rows of pixel units; the plurality of gate driving units are arranged on the circuit placing area and used for outputting scanning signals to the row pixel units of the pixel array area;
the control method includes steps S201 to S203.
S201: electrically connecting the potential shifter with the plurality of gate driving units for outputting control signals;
s202: connecting the control end of the driving circuit with the output end of the potential translator, controlling the on and off of the input end and the output end of the driving circuit, and connecting the output end of the driving circuit with the row pixel units through a grid driving unit;
s203: and controlling the voltage change of the input end of the driving circuit according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
In this embodiment, different output voltages are set to be input to the input terminal of the driving circuit according to the row pixel unit corresponding to the output signal of the output terminal of the driving circuit, so that the on-off speed of the input terminal and the output terminal of the driving circuit is increased row by row. When CK waveforms output by the potential shifter and corresponding to the row pixel units in each row are transmitted to the row pixel units in each row, the CK waveforms acquired by the row pixel units in each row are basically consistent, the voltage of grid signals of the grid driving substrate on the row pixel units in each row is consistent, and the problems of color cast, uneven brightness and the like are solved.
Optionally, the method further includes: inputting a reference voltage into a first input end of an adder, setting an adjusting voltage according to a row pixel unit corresponding to an output signal of an output end of the driving circuit, inputting the adjusting voltage into a second input end of the adder, and connecting an output end of the adder with a control end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased line by line.
Further, the method further comprises: the drive circuit comprises a PMOS tube and an NMOS tube, the control end of the PMOS tube is connected with the output end of the potential translator, and the output end of the PMOS tube is connected with the output end of the drive circuit;
the control end of the NMOS tube is connected with the output end of the potential translator, and the output end of the NMOS tube is connected with the voltage control circuit;
when the PMOS tube is opened, inputting an adjusting voltage which is a negative voltage into a second input end of the adder, wherein the adjusting voltage is gradually reduced;
when the NMOS tube is opened, the adjusting voltage which is positive voltage is input into the second input end of the adder, and the adjusting voltage is gradually increased.
Different impedance settings can be realized by controlling the Gate voltage of the MOS tube, when pixel units in different rows are opened, different voltages are generated by using the DAC to add Vref reference voltage to generate a required V _ Gate signal, the DAC is in negative pressure for opening the PMOS tube, the opening and closing speed of each row is gradually increased, the opening of the NMOS tube is in positive pressure, and the opening and closing speed of the lower tube is gradually increased.
Optionally, the method further includes: and setting different input voltages of the driving circuit by using a digital voltage generator according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
Further, the method further comprises: the drive circuit comprises a PMOS tube and an NMOS tube, the control end of the PMOS tube is connected with the output end of the potential translator, and the output end of the PMOS tube is connected with the output end of the drive circuit;
the control end of the NMOS tube is connected with the output end of the potential translator, and the output end of the NMOS tube is connected with the voltage control circuit;
respectively connecting a first output end and a second output end of the digital voltage generator with an input end of the PMOS tube and an input end of the NMOS tube;
when the PMOS tube is opened, controlling the output voltage of the first output end of the digital voltage generator to gradually decrease;
and when the NMOS tube is opened, controlling the output voltage of the second output end of the digital voltage generator to be gradually increased.
Setting a 1024(10bits) voltage in the VGH-VGL, and controlling different opening speeds by controlling different bits numbers of the PMOS tube to open, thereby realizing the same compensation effect as the embodiment, namely, when the PMOS tube is opened, the output voltage bit number is gradually reduced, the impedance is reduced, the switching speed is increased, when the NMOS tube is opened, the output bit number is gradually increased, the impedance is also reduced, and the switching speed is increased. Of course, other digital voltage generators 163 with other numbers of bits, such as 9 bits, 11 bits, 12 bits, 15 bits, etc., may be used.
Although the present invention has been described with reference to the preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments, and that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention.
Claims (10)
1. A display panel, comprising:
the grid driving substrate comprises a pixel array area and a circuit placing area positioned on the side edge of the pixel array area, wherein the pixel array area comprises a plurality of rows of pixel units;
the grid driving units are arranged on the circuit placing area and used for outputting scanning signals to the row pixel units in the pixel array area;
the driving circuit comprises an input end, an output end and a control end;
the potential translator is electrically connected with the plurality of gate driving units through the driving circuit and used for outputting control signals, wherein the output end of the potential translator is connected with the control end of the driving circuit and used for controlling the on and off of the input end and the output end of the driving circuit, and the output end of the driving circuit is connected with the row pixel units through the gate driving units;
the output end of the voltage control circuit is connected with the input end of the driving circuit, and the voltage control circuit sets different output voltages to be input into the input end of the driving circuit according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
2. The display panel according to claim 1, wherein the voltage control circuit comprises a digital-to-analog converter and an adder, an output terminal of the adder is connected to an input terminal of the driving circuit, a first input terminal of the adder is connected to the reference voltage, and a second input terminal of the adder is connected to the digital-to-analog converter;
and the digital-to-analog converter sets different adjusting voltages according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
3. The display panel according to claim 2, wherein the driving circuit comprises a PMOS transistor and an NMOS transistor, a control terminal of the PMOS transistor is connected to the output terminal of the potential shifter, and an output terminal of the PMOS transistor is connected to the output terminal of the driving circuit;
the control end of the NMOS tube is connected with the output end of the potential translator, and the output end of the NMOS tube is connected with the voltage control circuit;
the input end of the PMOS tube is connected with the output end of the voltage control circuit, and/or the input end of the NMOS tube is connected with the output end of the drive circuit, and the PMOS tube and the NMOS tube are used for setting different adjusting voltages according to the row pixel units corresponding to the output signal of the output end of the drive circuit, so that the on-off speed of the PMOS tube and the NMOS tube is increased row by row.
4. The display panel according to claim 1, wherein the voltage control circuit comprises a digital voltage generator, an output terminal of the digital voltage generator is connected to an input terminal of the driving circuit;
and the digital voltage generator sets different output voltages according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
5. The display panel according to claim 4, wherein the driving circuit comprises a PMOS transistor and an NMOS transistor, a control terminal of the PMOS transistor is connected to the output terminal of the potential shifter, and an output terminal of the PMOS transistor is connected to the output terminal of the driving circuit;
the control end of the NMOS tube is connected with the output end of the potential translator, and the output end of the NMOS tube is connected with the voltage control circuit;
the digital voltage generator comprises a first output end and a second output end which are respectively connected with the input end of the PMOS tube and the input end of the NMOS tube and used for setting different output voltages according to the row pixel units corresponding to the output signal of the output end of the driving circuit, so that the on-off speed of the PMOS tube and the NMOS tube is increased row by row.
6. The control method of the display panel grid signal is characterized in that the display panel comprises a grid driving substrate, a plurality of grid driving units, a potential shifter and a driving circuit; the gate driving substrate comprises a pixel array area and a circuit placing area positioned on the side edge of the pixel array area, and the pixel array area comprises a plurality of rows of pixel units; the gate driving units are arranged on the circuit placing area and used for outputting scanning signals to the row pixel units in the pixel array area; the driving circuit comprises an input end, an output end and a control end;
the control method comprises the following steps:
the potential shifter is electrically connected with a plurality of grid driving units through the driving circuit and is used for outputting control signals,
connecting the output end of the potential translator with the control end of the driving circuit, controlling the on and off of the input end and the output end of the driving circuit, and connecting the output end of the driving circuit with the row pixel units through a grid driving unit;
and controlling the voltage change of the input end of the driving circuit according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
7. The method of claim 6, further comprising:
inputting a reference voltage into a first input end of an adder, setting an adjusting voltage according to a row pixel unit corresponding to an output signal of an output end of the driving circuit, inputting the adjusting voltage into a second input end of the adder, and connecting an output end of the adder with a control end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased line by line.
8. The method of claim 7, further comprising:
the drive circuit comprises a PMOS tube and an NMOS tube, the control end of the PMOS tube is connected with the output end of the potential translator, and the output end of the PMOS tube is connected with the output end of the drive circuit;
the control end of the NMOS tube is connected with the output end of the potential translator, and the output end of the NMOS tube is connected with the voltage control circuit;
when the PMOS tube is opened, inputting an adjusting voltage which is a negative voltage into a second input end of the adder, wherein the adjusting voltage is gradually reduced;
when the NMOS tube is opened, the adjusting voltage which is positive voltage is input into the second input end of the adder, and the adjusting voltage is gradually increased.
9. The method of claim 6, further comprising:
and setting different input voltages of the driving circuit by using a digital voltage generator according to the row pixel units corresponding to the output signals of the output end of the driving circuit, so that the on-off speed of the input end and the output end of the driving circuit is increased row by row.
10. The method of claim 9, further comprising:
the drive circuit comprises a PMOS tube and an NMOS tube, the control end of the PMOS tube is connected with the output end of the potential translator, and the output end of the PMOS tube is connected with the output end of the drive circuit;
the control end of the NMOS tube is connected with the output end of the potential translator, and the output end of the NMOS tube is connected with the voltage control circuit;
respectively connecting a first output end and a second output end of the digital voltage generator with an input end of the PMOS tube and an input end of the NMOS tube;
when the PMOS tube is opened, controlling the output voltage of the first output end of the digital voltage generator to gradually decrease;
and when the NMOS tube is opened, controlling the output voltage of the second output end of the digital voltage generator to be gradually increased.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710592931.9A CN107293267B (en) | 2017-07-19 | 2017-07-19 | Display panel and control method of display panel grid signals |
| PCT/CN2017/109529 WO2019015171A1 (en) | 2017-07-19 | 2017-11-06 | Display panel, and method of controlling gate signal for display panel |
| US15/735,720 US20190114982A1 (en) | 2017-07-19 | 2017-11-06 | Display panel and gate signal control method for display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710592931.9A CN107293267B (en) | 2017-07-19 | 2017-07-19 | Display panel and control method of display panel grid signals |
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| Publication Number | Publication Date |
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| CN107293267A CN107293267A (en) | 2017-10-24 |
| CN107293267B true CN107293267B (en) | 2020-05-05 |
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| CN201710592931.9A Active CN107293267B (en) | 2017-07-19 | 2017-07-19 | Display panel and control method of display panel grid signals |
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| Country | Link |
|---|---|
| US (1) | US20190114982A1 (en) |
| CN (1) | CN107293267B (en) |
| WO (1) | WO2019015171A1 (en) |
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| CN107293267B (en) * | 2017-07-19 | 2020-05-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and control method of display panel grid signals |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103208250A (en) * | 2013-03-26 | 2013-07-17 | 京东方科技集团股份有限公司 | Drive circuit, drive method and display device |
| US9135881B2 (en) * | 2012-12-20 | 2015-09-15 | Shenzhen China Star Optoelectronics Technology Co., Ltd | LCD panel driver circuit, driving method and LCD device |
| CN105321494A (en) * | 2015-11-27 | 2016-02-10 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal display panel |
| CN106504708A (en) * | 2017-01-04 | 2017-03-15 | 昆山工研院新型平板显示技术中心有限公司 | Display device and its gate driver circuit |
| CN106920530A (en) * | 2017-05-11 | 2017-07-04 | 惠科股份有限公司 | Drive circuit, drive method of drive circuit and display device |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7830351B2 (en) * | 2005-10-11 | 2010-11-09 | Au Optronics Corporation | LCD gate driver circuitry having adjustable current driving capacity |
| KR20070064098A (en) * | 2005-12-16 | 2007-06-20 | 삼성전자주식회사 | Driving device and liquid crystal display including the same |
| TWI336461B (en) * | 2007-03-15 | 2011-01-21 | Au Optronics Corp | Liquid crystal display and pulse adjustment circuit thereof |
| TWI357060B (en) * | 2007-06-21 | 2012-01-21 | Chunghwa Picture Tubes Ltd | Gate driving circuit and power control circuit |
| CN101369061A (en) * | 2008-10-15 | 2009-02-18 | 上海广电光电子有限公司 | Method for driving liquid crystal display panel |
| TWI419134B (en) * | 2010-01-21 | 2013-12-11 | Himax Tech Ltd | Gate driver |
| CN102855862B (en) * | 2012-09-29 | 2014-07-30 | 深圳市华星光电技术有限公司 | Driving circuit of liquid crystal panel, liquid crystal panel and liquid crystal display device |
| CN103543567B (en) * | 2013-11-11 | 2016-03-30 | 北京京东方光电科技有限公司 | A kind of array base palte and driving method, display device |
| CN105070243B (en) * | 2015-09-15 | 2017-10-31 | 重庆京东方光电科技有限公司 | Gate turn-on voltage compensation circuit, display panel, driving method and display device |
| CN105139818B (en) * | 2015-09-29 | 2019-02-19 | 南京中电熊猫液晶显示科技有限公司 | A kind of driving method of liquid crystal display panel |
| US9984624B2 (en) * | 2015-12-28 | 2018-05-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, driver IC, and electronic device |
| CN106128408A (en) * | 2016-09-18 | 2016-11-16 | 深圳市华星光电技术有限公司 | The drive circuit of a kind of display panels and display panels |
| CN107293267B (en) * | 2017-07-19 | 2020-05-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and control method of display panel grid signals |
-
2017
- 2017-07-19 CN CN201710592931.9A patent/CN107293267B/en active Active
- 2017-11-06 WO PCT/CN2017/109529 patent/WO2019015171A1/en active Application Filing
- 2017-11-06 US US15/735,720 patent/US20190114982A1/en not_active Abandoned
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9135881B2 (en) * | 2012-12-20 | 2015-09-15 | Shenzhen China Star Optoelectronics Technology Co., Ltd | LCD panel driver circuit, driving method and LCD device |
| CN103208250A (en) * | 2013-03-26 | 2013-07-17 | 京东方科技集团股份有限公司 | Drive circuit, drive method and display device |
| CN105321494A (en) * | 2015-11-27 | 2016-02-10 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal display panel |
| CN106504708A (en) * | 2017-01-04 | 2017-03-15 | 昆山工研院新型平板显示技术中心有限公司 | Display device and its gate driver circuit |
| CN106920530A (en) * | 2017-05-11 | 2017-07-04 | 惠科股份有限公司 | Drive circuit, drive method of drive circuit and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2019015171A1 (en) | 2019-01-24 |
| CN107293267A (en) | 2017-10-24 |
| US20190114982A1 (en) | 2019-04-18 |
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