CN105320463A - Solid state storage device with hybrid storage mode - Google Patents

Abstract

A solid-state storage device with a hybrid storage mode mainly comprises a flash memory and a data processing module in information connection with the flash memory. The flash memory comprises a first storage magnetic area for storing data in a first potential storage mode and a second storage magnetic area for storing data in a second potential storage mode, wherein the physical block address of the first storage magnetic area is P₀To P_M-1The logical block address is L₀To L_M-1And the physical block address of the second storage sector is P_MTo P_M+N-1The logical block address is L_MTo L_M+N-1. The data processing module has a data processing mode for interpreting the logical block address contained in a command and executing a command action corresponding to the physical block address. Accordingly, a solid state storage device with high stability and high data storage capacity is provided.

Description

Solid state storage device with hybrid storage mode

technical field

The invention relates to a solid-state storage device, in particular to a solid-state storage device using the same flash memory to implement more than two potential storage modes.

Background technique

With the maturity of solid-state storage device (Solid-State Drive, SSD) technology, it will gradually replace the existing hard disk device (Hard Disk Drive, HDD). Low power, light weight and other advantages.

Moreover, solid-state storage devices mainly use a floating gate transistor of a flash memory to store data bit data, and can be divided into single-level cell (Single-LevelCell) according to the number of data bits that each transistor can store. , SLC) and multi-level cell (Multi-LevelCell, MLC) and other two potential storage modes. When the single-level cell type is implemented, there are only two voltage changes, that is, each transistor can only store a single data bit, while the multi-level cell type can be stored in each transistor Stores two to three data bits. Therefore, when multi-level cell implementation is used, the number of data bits that each transistor can store is several times that of single-level cell implementation, and the manufacturing cost of flash memory implemented by multi-level cell It is relatively cheap, but the response speed of this implementation is relatively slow for data access, and its lifespan is low. However, although the flash memory implemented as a single-level cell has the advantages of high stability, relatively fast response speed of data access and long service life, its capacity density for storing data is low. making its manufacturing cost relatively high.

Accordingly, various manufacturers have proposed hybrid solid-state storage devices including a single-level cell potential storage mode and a multi-level cell potential storage mode, such as China Taiwan Invention No. I385517 Patent Case, which discloses a storage device, It uses a first flash memory and a second flash memory different from the first flash memory to generate hybrid storage, but the patent needs to purchase two different types of However, the manufacturing cost is still limited by the selling price of the flash memory implemented in the single-level cell potential storage mode, which cannot be effectively reduced.

Contents of the invention

The main purpose of the present invention is to solve the problems of data stability and data storage capacity generated by existing solid-state storage devices that can only be implemented in a single potential storage mode.

To achieve the above purpose, the present invention provides a solid-state storage device with a hybrid storage mode, the solid-state storage device includes a flash memory and a data processing module. Wherein, the flash memory includes a first storage magnetic area for storing data in a first potential storage mode and a second storage magnetic area for storing data in a second potential storage mode different from the first potential storage mode, The first storage magnetic area includes M data blocks, the second storage magnetic area includes N data blocks, each of which corresponds to a physical block address and a logical block address, and the first storage The physical block address of the magnetic zone is P ₀ to _PM-1 , and the logical block address is L ₀ to L _M-1 , and the physical block address of the second storage magnetic zone is _PM to _PM+N-1 , and the logical block address is L _M to L _M+N-1 . The data processing module is connected with the flash memory information, and has a data processing mode of accepting an instruction, interpreting the logical block address included in the instruction, and executing the instruction action at the corresponding physical block address.

In one embodiment, the first potential storage mode is a single-level cell type, and the second potential storage mode is a multi-level cell type. Further, the data processing module has a data modulator that adds a potential modulation command to the command to change the original potential storage method of the command when judging that the logical block address included in the command is L ₀ to L _M-1 model.

In one embodiment, the first potential storage mode is a multi-level cell type, and the second potential storage mode is a single-level cell type. Further, the data processing module has a data for judging that the address of the logic block contained in the instruction is L _M to L _M+N-1 , adding a potential modulation command to the command to change the original potential storage mode of the command modulation mode.

In one embodiment, the data storage capacity of the first storage magnetic zone is different from the data storage capacity of the second storage magnetic zone.

In one embodiment, the data processing module includes a first mapping that records physical block addresses P ₀ to P _M-1 and logical block addresses L ₀ to L _M-1 corresponding to the first storage magnetic zone table, and a second mapping table recording physical block addresses corresponding to the second storage magnetic zone as PM to _PM+N-1 and logical block addresses L _M to L _{M +N-1} .

In one embodiment, the flash memory further includes a third storage magnetic area for storing data in a third potential storage mode different from the first potential storage mode and the second potential storage mode, the third storage magnetic area Including R data blocks, the physical block addresses of the third storage magnetic zone are _PN to _PN+R-1 , and the logical block addresses are L _N to L _N+R-1 . Further, the data processing module includes a first mapping table for recording physical block addresses corresponding to the first storage magnetic zone as P ₀ to _PM-1 and logical block addresses L ₀ to L _M-1 , a record the second mapping table in which the physical block addresses corresponding to the second storage magnetic zone are PM to _PM+N-1 and the logical block addresses L _M to L _{M +N-1} , and record the third The physical block addresses corresponding to the storage magnetic regions are a third mapping table of _PN to _PN+R-1 and logical block addresses L _N to L _N+R-1 .

In one embodiment, the data processing module has a function of finding a recordable block according to the erasing times of each data block of the first storage magnetic area and the second storage magnetic area when the instruction is an action of writing data Averaging algorithm for averaging writes.

Through the above-mentioned embodiment of the present invention, compared with the prior art, it has the following characteristics: the present invention is implemented with the flash memory of the same transistor type, and the flash memory is divided into the first storage magnetic area and the second storage magnetic area The electric potential storage methods used by the first storage magnetic region and the second storage magnetic region are different, so as to provide a solid state storage device with high stability and high data storage capacity.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

FIG. 1 is a unit composition diagram of an embodiment of a solid-state storage device with a hybrid storage mode in the present invention;

FIG. 2 is a schematic diagram of a flash memory of an embodiment of a solid-state storage device with a hybrid storage mode in the present invention;

FIG. 3 is a schematic diagram of a flash memory of another embodiment of a solid-state storage device with a hybrid storage mode according to the present invention.

detailed description

Relating to the detailed description and technical content of the present invention, it is now described as follows in conjunction with the accompanying drawings:

Please refer to FIG. 1 and FIG. 2 , the solid-state storage device 100 with a hybrid storage mode of the present invention mainly includes a flash memory 1 and a data processing module 2 connected to the flash memory 1 . Further, the flash memory 1 of the present invention may be composed of a plurality of chips, each of which has the same type of transistors. In other words, the flash memory 1 of the present invention only has a single potential storage mode, such as Multi-Level Cell (MLC), before it is implemented. Furthermore, the flash memory 1 has a plurality of data blocks 11, each of which corresponds to a physical block address (PhysicalBlockAddress, PBA) and a logical block address (LogicalBlockAddress, LBA), further, In the present invention, the flash memory 1 is divided into a first storage magnetic area 12 and a second storage magnetic area 13 by the logical block address, wherein the first storage magnetic area 12 includes M data blocks 11, and The corresponding physical block addresses are P ₀ to _PM-1 , the logical block addresses are L ₀ to L _M-1 , and the second storage magnetic area 13 includes N data blocks 11, corresponding to the The physical block addresses are PM to _PM+N-1 , and the logical block addresses are L _M to L _{M +N-1} .

It can be seen from the above that the flash memory 1 of the present invention has only a single potential storage mode when it is not implemented, but in the implementation process of the present invention, the potential storage mode of one of the storage magnetic regions is changed by the data processing module 2 to simulate another potential storage mode. The potential storage mode records data. More specifically, the first storage magnetic region 12 of the present invention stores data in a first potential storage mode, and the second storage magnetic region 13 uses a second storage mode different from the first potential storage mode. Two potential storage modes store data. In one embodiment, the first potential storage mode is a single-level cell (Single-Level Cell, SLC), and the second potential storage mode is a multi-level cell type, but the present invention does not As a limit, the first potential storage mode may also be a multi-level cell type, and the second potential storage mode may be a single-level cell type. Moreover, after the flash memory 1 of the present invention distinguishes the first storage magnetic region 12 and the second storage magnetic region 13, since the potential storage modes of the first storage magnetic region 12 and the second storage magnetic region 13 are different, the present invention The data storage capacity of the first storage magnetic zone 12 is different from the data storage capacity of the second storage magnetic zone 13 . For example, when the first potential storage mode of the first storage magnetic region 12 is a single-level cell type, each of the transistors in each data block 11 in the first storage magnetic region 12 can only record one bit The data of the element, so that the data storage capacity of the first storage magnetic region 12 will be smaller than the data storage capacity of the second storage magnetic region 13 in the multi-level cell type for the second potential storage mode.

Continuing from the above, the data processing module 2 of the present invention is connected with the flash memory 1 information, and has an action of receiving a command D1 and interpreting the logical block address included in the command to execute the command corresponding to the physical block address data processing mode. More specifically, the solid-state storage device 100 of the present invention can be connected to a computer device 3 (such as a computer), and the computer device 3 can be used to write or read data to it, and the command D1 referred to in the present invention is It is issued by the computer device 3. When the computer device 3 sends the instruction D1 to the solid-state storage device 100, the data processing module 2 will interpret the data contained in the instruction D1 and request to execute the action after receiving the instruction D1. Logical block address, and read corresponding data according to the logical block address. Further, it can be known from the above that the first potential storage mode of the present invention can be implemented as a multi-level unit. Therefore, the data processing module 2 further has a function for judging that the address of the logical block included in the instruction D1 is from _L0 to When L _M-1 , add a potential modulation command to the command D1 to change the data modulation mode of the original potential storage mode of the command D1. In addition, if in an embodiment of the present invention, when the second potential storage mode is implemented as a multi-level unit, the data modulation mode of the data processing module 2 is aimed at the logic included in the instruction D1 Implemented when the block address is L _M to L _M+N-1 . Continuing from the above, the present invention allows the data processing module 2 to have the data modulation mode to simulate the original multi-level cell potential storage mode into a single-level cell potential storage mode. Also, the level modulation command can be a flag command or a paging command.

Furthermore, please refer to FIG. 2 again, the data processing module 2 of the present invention further includes a record that the physical block addresses corresponding to the first storage magnetic zone 12 are P ₀ to P _M-1 and the logical block address L ₀ The first mapping table T1 to L _M-1 , and a record corresponding to the physical block address of the second storage magnetic zone 13 is _PM to _PM+N-1 and the logical block address L _M to L The second mapping table T2 of _M+N-1 . Thereby, the data processing module 2 can quickly complete the correspondence between each logical block address and each physical block address through the first mapping table T1 and the second mapping table T2. Moreover, the data processing module 2 further includes a method for finding a recordable area according to the erasing times of each data block 11 of the first storage magnetic area 12 and the second storage magnetic area 13 when the instruction D1 is an action of writing data. Averaging algorithm for write averaging of blocks.

In addition, please refer to FIG. 3 , in one embodiment of the present invention, the flash memory 2 includes, in addition to the first storage magnetic region 12 and the second storage magnetic region 13, a The third storage magnetic area 14 for storing data in the first potential storage mode and the third potential storage mode of the second potential storage mode, the third storage magnetic area 14 includes R data blocks 11, the third storage magnetic area 14 The addresses of the physical blocks are from _PN to _PN+R-1 , and the addresses of the logical blocks are from L _N to L _N+R-1 . For example, in this embodiment, the first potential storage mode is a single-level cell type, the second potential storage mode is a multi-level cell type, and the third potential storage mode can be a three-layer storage (TLC ). Furthermore, in this embodiment, the data processing module 2 may include not only the first mapping table T1 and the second mapping table T2, but also a record corresponding to the third storage magnetic zone 14. The physical block addresses are _PN to _PN+R-1 and the third mapping table T3 of the logical block addresses L _N to L _N+R-1 .

To sum up, the solid-state storage device with hybrid storage mode of the present invention mainly includes a flash memory and a data processing module connected to the flash memory. Wherein, the flash memory includes a first storage magnetic area for storing data in a first potential storage mode and a second storage magnetic area for storing data in a second potential storage mode, the physical block address of the first storage magnetic area is P ₀ to _PM-1 , the logical block address is L ₀ to L _M-1 , and the physical block address of the second storage magnetic zone is _PM to _PM+N-1 , and the logical block address is LM to LM _{+N-1 .} The data processing module has a data processing mode for interpreting the logical block address included in an instruction and executing instruction action at the corresponding physical block address. Accordingly, a solid-state storage device with high stability and high data storage capacity is provided.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (10)

1. there is a solid state storage device for mixing storage mode, it is characterized in that, include:

One fast flash memory bank, include one and store magnetic region and to be different from the second storage magnetic region of one second current potential storage mode storage data of this first current potential storage mode with first of one first current potential storage mode storage data, this the first storage magnetic region includes M block, this the second storage magnetic region includes N number of block, each this block is a corresponding physical blocks address and a logical block addresses respectively, and this first physical blocks address storing magnetic region is P ₀to P _m-1, and this logical block addresses is L ₀to L _m-1, this second physical blocks address storing magnetic region is P _mto P _m+N-1, and this logical block addresses is L _mto L _m+N-1; And

One data processing module, is connected with this fast flash memory bank information, has acceptance one instruction and understands this logical block addresses that this instruction comprises and perform the data processing mode of instruction action in this physical blocks address of correspondence.

2. have the solid state storage device of mixing storage mode as claimed in claim 1, it is characterized in that, this first current potential storage mode is single stage unit formula, and this second current potential storage mode is multi-level unit formula.

3. have the solid state storage device of mixing storage mode as claimed in claim 2, it is characterized in that, it is L that this data processing module has this logical block addresses that this instruction of a judgement comprises ₀to L _m-1time the data-modulated pattern that one current potential modulation instruction changes the original current potential storing mode of this instruction is added to this instruction.

4. have the solid state storage device of mixing storage mode as claimed in claim 1, it is characterized in that, this first current potential storage mode is multi-level unit formula, and this second current potential storage mode is single stage unit formula.

5. have the solid state storage device of mixing storage mode as claimed in claim 4, it is characterized in that, it is L that this data processing module has this logical block addresses that this instruction of a judgement comprises _mto L _m+N-1time the data-modulated pattern that one current potential modulation instruction changes the original current potential storing mode of this instruction is added to this instruction.

6. have the solid state storage device of mixing storage mode as claimed in claim 1, it is characterized in that, this first data storage capacities storing magnetic region is different from the data storage capacities of this second storage magnetic region.

7. the solid state storage device with mixing storage mode as described in claim 1,2,4 or 6, is characterized in that, this data processing module includes and records this first to store physical blocks address corresponding to magnetic region be P ₀to P _m-1and logical block addresses L ₀to L _m-1the first corresponding table, and one records this second to store physical blocks address corresponding to magnetic region is P _mto P _m+N-1and logical block addresses L _mto L _m+N-1the second corresponding table.

8. there is the solid state storage device of mixing storage mode as claimed in claim 1, it is characterized in that, this fast flash memory bank more includes one and stores magnetic region with the be different from the 3rd current potential storage mode storage data of this first current potential storage mode and this second current potential storage mode the 3rd, 3rd stores magnetic region includes R block, and the 3rd physical blocks address storing magnetic region is P _nto P _n+R-1, and this logical block addresses is L _nto L _n+R-1.

9. have the solid state storage device of mixing storage mode as claimed in claim 8, it is characterized in that, this data processing module includes and records this first to store physical blocks address corresponding to magnetic region be P ₀to P _m-1and logical block addresses L ₀to L _m-1the first corresponding table, one records this, and second to store physical blocks address corresponding to magnetic region be P _mto P _m+N-1and logical block addresses L _mto L _m+N-1the second corresponding table, and one records the 3rd to store physical blocks address corresponding to magnetic region is P _nto P _n+R-1and logical block addresses L _nto L _n+R-1the 3rd corresponding table.

10. there is the solid state storage device of mixing storage mode as claimed in claim 1, it is characterized in that, this data processing module has one and first stores magnetic region and this second elimination number of times of each this block storing magnetic region according to this and find out one and can record block and to be averaged the average write algorithm of write when this instruction is write data action.