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CN105304500A - N型tft的制作方法 - Google Patents

N型tft的制作方法 Download PDF

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CN105304500A
CN105304500A CN201510703744.4A CN201510703744A CN105304500A CN 105304500 A CN105304500 A CN 105304500A CN 201510703744 A CN201510703744 A CN 201510703744A CN 105304500 A CN105304500 A CN 105304500A
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polysilicon layer
type tft
manufacture method
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CN105304500B (zh
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胡国仁
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/892,572 priority patent/US9698177B1/en
Priority to PCT/CN2015/093109 priority patent/WO2017070868A1/zh
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Abstract

本发明提供一种N型TFT的制作方法，通过对遮光层进行栅格状图案化处理来控制多晶硅层的不同区域形成结晶差异，使得多晶硅层不同区域的结晶晶粒大小不同，进而仅通过一次离子掺杂制程使得多晶硅层不同区域在掺杂浓度相同的条件下由于晶粒大小不同而产生电阻率不同，实现等同于LDD结构的效果，能够使TFT具有较低的漏电流和较高的可靠性；同时由于只需要一次离子注入，能够节省制程时间和制造成本，减少多晶硅层的损伤，缩短活化时间，有利于柔性显示器的制作。

Description

N型TFT的制作方法
技术领域
本发明涉及半导体制作工艺，尤其涉及一种N型TFT的制作方法。
背景技术
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(LiquidCrystalDisplay，LCD)及有机电致发光显示装置(OrganicLightEmittingDisplay，OLED)等。
薄膜晶体管(ThinFilmTransistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开关器件和驱动器件用在诸如LCD、OLED等显示装置上。
按照TFT形成电流时载流子的不同，TFT可分为以N型TFT(以电子为载流子)、与P型TFT(以空穴为载流子)两大类。
其中，N型TFT的漏电流较大，为了提高N型TFT的可靠性，现有技术通常在N型TFT内半导体层的沟道两侧设置轻掺杂漏区(LightlyDopedDrain，LDD)，通过LDD来降低漏电流。
传统的制作具有LDD结构的N型TFT的方法包括以下步骤：
步骤1、如图1所示，提供一基板100，在所述基板100上沉积一遮光层(LightshieldingLayer)，对所述遮光层进行图案化处理，得到一整体式遮光条210。
步骤2、如图2所示，在所述整体式遮光条210及基板100上依次沉积缓冲层200和一非晶硅层，对所述非晶硅层进行脱氢处理，采用准分子激光退火制程将所述非晶硅层转化为多晶硅层300。
如图3所示，经该步骤2获得的多晶硅层300内的晶粒大小基本均匀一致。
步骤3、如图4所示，在多晶硅层300上涂布一光阻层400’，采用一道黄光制程对所述光阻层400’进行曝光、显影，暴露出所述多晶硅层300的两端区域，以所述光阻层400’为遮挡层对多晶硅层300的两端区域进行一次N型重掺杂，然后去除所述光阻层400’；
步骤4、如图5所示，在所述多晶硅层300上沉积栅极绝缘层400；
步骤5、如图6、图7所示，在所述栅极绝缘层400上沉积一层栅极导电薄膜并进行图案化处理，得到栅极导电层500，该栅极导电层500的长度要小于上述步骤3中光阻层400’的长度，以暴露出上述步骤3中未被掺杂的部分多晶硅层300，再以该栅极导电层500为遮挡层进行一次N型轻掺杂，得到N型重掺杂区310、N型轻掺杂区320、及沟道区330。
所述N型轻掺杂区320即构成LDD。
步骤6、继续后续通用的半导体制程，如沉积层间绝缘层并蚀刻层间绝缘层与栅极绝缘层400形成接触孔，沉积并蚀刻金属层形成源极、漏极、栅极等，最终制得具有LDD结构的N型TFT。
上述传统的制作具有LDD结构的N型TFT的方法，分别需要一道光罩来定义重掺杂区与轻掺杂区，而且需要进行两次离子掺杂，制程步骤较多，成本较高，且由于重掺杂区与轻掺杂区在黄光对位方面常常出现偏差，会影响到TFT的均匀性。
现有的制作具有LDD结构的N型TFT的另一种方法是利用一道半色调光罩对栅极先后进行两次蚀刻，以第一次蚀刻后的栅极为遮挡层来进行N型重掺杂，以第二次蚀刻后的栅极为遮挡层来进行N型轻掺杂，从而形成LDD。这种方法虽然可以节省一道光罩，但两次蚀刻的均匀性不易控制。
图8所示为不同晶粒大小的多晶硅电阻率与掺杂浓度的关系，由此图可看出在相同的掺杂浓度下，不同晶粒大小的多晶硅具有不同的电阻率。具体地，在相同的掺杂浓度下，多晶硅晶粒越小电阻率越大。因此，在相同的掺杂浓度下，可以通过控制多晶硅晶粒的大小来实现等同于LDD结构的效果。
发明内容
本发明的目的在于提供一种N型TFT的制作方法，利用相同掺杂浓度下不同晶粒大小的多晶硅具有不同的电阻率的特性，只需一次离子掺杂就能够实现等同于LDD结构的效果，节省制程时间与制造成本。
为实现上述目的，本发明提供一种N型TFT的制作方法，包括以下步骤：
步骤1、提供一基板，在所述基板上沉积一遮光层，对所述遮光层进行栅格状图案化处理，得到多个相互间隔的独立遮光块；
步骤2、在所述多个独立遮光块及基板上依次沉积缓冲层和非晶硅层，并使所述非晶硅层结晶、转化为多晶硅层；
所述多晶硅层对应于多个独立遮光块的第一区域的结晶晶粒最小，对应于每相邻两个独立遮光块之间间隔的第二区域的结晶晶粒最大，剩余的第三区域的结晶晶粒适中；
步骤3、在所述多晶硅层上沉积栅极绝缘层；
步骤4、在所述栅极绝缘层上沉积一层导电薄膜并进行图案化处理，得到栅极导电层；
所述栅极导电层位于所述多个相互间隔的独立遮光块的正上方，其两侧均暴露出所述多晶硅层的第三区域与部分第一区域；
步骤5、以所述栅极导电层为遮挡层，对所述多晶硅层进行一次N型离子掺杂，所述多晶硅层的第三区域经N型离子掺杂后的电阻率小于所述多晶硅层的部分第一区域经N型离子掺杂后的电阻率，所述多晶硅层的部分第一区域经N型离子掺杂后等同于轻掺杂漏区。
所述N型TFT的制作方法，还包括：
步骤6、在所述栅极导电层和栅极绝缘层上沉积一层间绝缘层，对所述层间绝缘层与栅极绝缘层进行图案化处理，形成暴露出所述栅极导电层部分表面的第一接触孔、及分别于所述栅极导电层两侧暴露出经N型离子掺杂后的多晶硅层第三区域的部分表面的第二接触孔、与第三接触孔；
步骤7、在所述层间绝缘层上沉积并图案化金属层，形成经由第一接触孔接触所述栅极导电层的栅极、分别经由第二接触孔、第三接触孔接触经N型离子掺杂后的多晶硅层第三区域的源极与漏极。
所述基板为玻璃基板或塑料基板。
所述步骤2通过对所述非晶硅层进行脱氢处理，采用准分子激光退火制程使所述非晶硅层结晶、转化为多晶硅层。
所述多个相互间隔的独立遮光块的数量为3个或3个以上。
所述步骤1中的遮光层的材料为金属。
所述缓冲层、栅极绝缘层、与层间绝缘层的材料为氧化硅、氮化硅、或二者的组合；所述栅极导电层、栅极、源极、与漏极的材料为钼、钛、铝、铜中的一种或几种的堆栈组合。
所述N型TFT的制作方法适用于制作AMLCD、AMOLED、及柔性显示器件。
本发明的有益效果：本发明提供的一种N型TFT的制作方法，通过对遮光层进行栅格状图案化处理来控制多晶硅层的不同区域形成结晶差异，使得多晶硅层不同区域的结晶晶粒大小不同，进而仅通过一次离子掺杂制程使得多晶硅层不同区域在掺杂浓度相同的条件下由于晶粒大小不同而产生电阻率不同，实现等同于LDD结构的效果，能够使TFT具有较低的漏电流和较高的可靠性；同时由于只需要一次离子注入，能够节省制程时间和制造成本，减少多晶硅层的损伤，缩短活化时间，有利于柔性显示器的制作。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为传统的制作具有LDD结构的N型TFT的方法的步骤1的示意图；
图2为传统的制作具有LDD结构的N型TFT的方法的步骤2的示意图；
图3为图2中多晶硅层的俯视示意图；
图4为传统的制作具有LDD结构的N型TFT的方法的步骤3的示意图；
图5为传统的制作具有LDD结构的N型TFT的方法的步骤4的示意图；
图6为传统的制作具有LDD结构的N型TFT的方法的步骤5的示意图；
图7为图6的俯视示意图；
图8为不同晶粒大小的多晶硅电阻率与掺杂浓度的关系示意图；
图9为本发明N型TFT的制作方法的流程图；
图10为本发明的N型TFT的制作方法的步骤1的示意图；
图11为本发明的N型TFT的制作方法的步骤2的示意图；
图12为图11中多晶硅层的俯视示意图；
图13为本发明的N型TFT的制作方法的步骤3的示意图；
图14为本发明的N型TFT的制作方法的步骤4的示意图；
图15为图14的俯视示意图；
图16为本发明的N型TFT的制作方法的步骤5的示意图；
图17为本发明的N型TFT的制作方法的步骤6的示意图；
图18为本发明的N型TFT的制作方法的步骤7的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图9，本发明提供一种N型TFT的制作方法，包括以下步骤：
步骤1、如图10所示，提供一基板10，在所述基板10上沉积一遮光层，对所述遮光层进行栅格状图案化处理，得到多个相互间隔的独立遮光块21。
具体地，所述基板10为玻璃基板或塑料基板。
所述遮光层的材料为金属。优选的，所述多个相互间隔的独立遮光块21的数量为3个或3个以上，如图10所示，该3个相互间隔的独立遮光块21之间形成2处间隔。
步骤2、如图11所示，在所述多个独立遮光块21及基板10上依次沉积缓冲层30和非晶硅层，对所述非晶硅层进行脱氢处理，采用准分子激光退火制程使所述非晶硅层结晶、转化为多晶硅层40。
由于所述多个相互间隔的独立遮光块21的存在，所述非晶硅层在结晶、转化为多晶硅层40的过程中，不同区域的温度存在差异，多晶硅层40的不同区域形成结晶差异，从而使得多晶硅层40不同区域的结晶晶粒大小不同。结合图11与图12，所述多晶硅层40对应于多个独立遮光块21的第一区域41的结晶晶粒最小，对应于每相邻两个独立遮光块21之间间隔的第二区域42的结晶晶粒最大，剩余的第三区域43的结晶晶粒适中。
具体地，所述缓冲层30的材料为氧化硅(SiOx)、氮化硅(SiNx)、或二者的组合。
步骤3、如图13所示，在所述多晶硅层40上沉积栅极绝缘层50。
具体地，所述栅极绝缘层50的材料为SiOx、SiNx、或二者的组合。
步骤4、如图14、图15所示，在所述栅极绝缘层50上沉积一层导电薄膜并进行图案化处理，得到栅极导电层60。
所述栅极导电层60位于所述多个相互间隔的独立遮光块21的正上方，其两侧均暴露出所述多晶硅层40的第三区域43与部分第一区域41。
具体地，所述栅极导电层60的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或几种的堆栈组合。
步骤5、如图16所示，以所述栅极导电层60为遮挡层，对所述多晶硅层40进行一次N型离子掺杂。
该步骤5中，未被所述栅极导电层60遮挡的多晶硅层40的第三区域43与部分第一区域41进行了相同浓度的N型离子掺杂，但由于第三区域43内多晶硅的结晶晶粒大于第一区域41内多晶硅的结晶晶粒，根据图8所示的在相同的掺杂浓度下，多晶硅晶粒越小电阻率越大的这一特性，所述多晶硅层40的第三区域43经N型离子掺杂后的电阻率小于所述多晶硅层40的部分第一区域41经N型离子掺杂后的电阻率，从而所述多晶硅层40的部分第一区域41经N型离子掺杂后等同于轻掺杂漏区，所述多晶硅层40的第三区域43经N型离子掺杂后等同于N型重掺杂区，未经N型离子掺杂的第二区域42与其余部分第一区域41构成沟道区。
步骤6、如图17所示，在所述栅极导电层60和栅极绝缘层50上沉积一层间绝缘层70，对所述层间绝缘层70与栅极绝缘层50进行图案化处理，形成暴露出所述栅极导电层60部分表面的第一接触孔71、及分别于所述栅极导电层60两侧暴露出经N型离子掺杂后的多晶硅层40第三区域43的部分表面的第二接触孔72、与第三接触孔73。
具体地，所述层间绝缘层70的材料为SiOx、SiNx、或二者的组合。
步骤7、如图18所示，在所述层间绝缘层70上沉积并图案化金属层，形成经由第一接触孔71接触所述栅极导电层60的栅极81、分别经由第二接触孔72、第三接触孔73接触经N型离子掺杂后的多晶硅层40第三区域43的源极82与漏极83。
具体地，所述栅极81、源极82、与漏极83的材料为Mo、Ti、Al、Cu中的一种或几种的堆栈组合。
由上述方法制作的N型TFT具有等同于LDD效果的结构，能够使TFT具有较低的漏电流和较高的可靠性；同时该方法由于只需要一次离子注入，能够节省制程时间和制造成本，减少多晶硅层的损伤，缩短活化时间。
本发明的N型TFT的制作方法适用于制作AMLCD、AMOLED、及柔性显示器件。
综上所述，本发明的N型TFT的制作方法，通过对遮光层进行栅格状图案化处理来控制多晶硅层的不同区域形成结晶差异，使得多晶硅层不同区域的结晶晶粒大小不同，进而仅通过一次离子掺杂制程使得多晶硅层不同区域在掺杂浓度相同的条件下由于晶粒大小不同而产生电阻率不同，实现等同于LDD结构的效果，能够使TFT具有较低的漏电流和较高的可靠性；同时由于只需要一次离子注入，能够节省制程时间和制造成本，减少多晶硅层的损伤，缩短活化时间，有利于柔性显示器的制作。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (8)

1.一种N型TFT的制作方法，其特征在于，包括以下步骤：
步骤1、提供一基板(10)，在所述基板(10)上沉积一遮光层，对所述遮光层进行栅格状图案化处理，得到多个相互间隔的独立遮光块(21)；
步骤2、在所述多个独立遮光块(21)及基板(10)上依次沉积缓冲层(30)和非晶硅层，并使所述非晶硅层结晶、转化为多晶硅层(40)；
所述多晶硅层(40)对应于多个独立遮光块(21)的第一区域(41)的结晶晶粒最小，对应于每相邻两个独立遮光块(21)之间间隔的第二区域(42)的结晶晶粒最大，剩余的第三区域(43)的结晶晶粒适中；
步骤3、在所述多晶硅层(40)上沉积栅极绝缘层(50)；
步骤4、在所述栅极绝缘层(50)上沉积一层导电薄膜并进行图案化处理，得到栅极导电层(60)；
所述栅极导电层(60)位于所述多个相互间隔的独立遮光块(21)的正上方，其两侧均暴露出所述多晶硅层(40)的第三区域(43)与部分第一区域(41)；
步骤5、以所述栅极导电层(60)为遮挡层，对所述多晶硅层(40)进行一次N型离子掺杂，所述多晶硅层(40)的第三区域(43)经N型离子掺杂后的电阻率小于所述多晶硅层(40)的部分第一区域(41)经N型离子掺杂后的电阻率，所述多晶硅层(40)的部分第一区域(41)经N型离子掺杂后等同于轻掺杂漏区。
2.如权利要求1所述的N型TFT的制作方法，其特征在于，还包括：
步骤6、在所述栅极导电层(60)和栅极绝缘层(50)上沉积一层间绝缘层(70)，对所述层间绝缘层(70)与栅极绝缘层(50)进行图案化处理，形成暴露出所述栅极导电层(60)部分表面的第一接触孔(71)、及分别于所述栅极导电层(60)两侧暴露出经N型离子掺杂后的多晶硅层(40)第三区域(43)的部分表面的第二接触孔(72)、与第三接触孔(73)；
步骤7、在所述层间绝缘层(70)上沉积并图案化金属层，形成经由第一接触孔(71)接触所述栅极导电层(60)的栅极(81)、分别经由第二接触孔(72)、第三接触孔(73)接触经N型离子掺杂后的多晶硅层(40)第三区域(43)的源极(82)与漏极(83)。
3.如权利要求1所述的N型TFT的制作方法，其特征在于，所述基板(10)为玻璃基板或塑料基板。
4.如权利要求1所述的N型TFT的制作方法，其特征在于，所述步骤2通过对所述非晶硅层进行脱氢处理，采用准分子激光退火制程使所述非晶硅层结晶、转化为多晶硅层(40)。
5.如权利要求1所述的N型TFT的制作方法，其特征在于，所述多个相互间隔的独立遮光块(21)的数量为3个或3个以上。
6.如权利要求1所述的N型TFT的制作方法，其特征在于，所述步骤1中的遮光层的材料为金属。
7.如权利要求1所述的N型TFT的制作方法，其特征在于，所述缓冲层(30)、栅极绝缘层(50)、与层间绝缘层(70)的材料为氧化硅、氮化硅、或二者的组合；所述栅极导电层(60)、栅极(81)、源极(82)、与漏极(83)的材料为钼、钛、铝、铜中的一种或几种的堆栈组合。
8.如权利要求1所述的N型TFT的制作方法，其特征在于，适用于制作AMLCD、AMOLED、及柔性显示器件。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108417586A (zh) * 2018-03-13 2018-08-17 京东方科技集团股份有限公司 一种阵列基板的制备方法及阵列基板
CN108538860A (zh) * 2018-04-27 2018-09-14 武汉华星光电技术有限公司 顶栅型非晶硅tft基板的制作方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170123384A (ko) * 2016-04-28 2017-11-08 삼성디스플레이 주식회사 표시 장치
WO2018111247A1 (en) * 2016-12-13 2018-06-21 Intel Corporation Passivation dielectrics for oxide semiconductor thin film transistors
CN107369693B (zh) * 2017-08-04 2020-04-21 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN111788663A (zh) * 2018-03-09 2020-10-16 堺显示器制品株式会社 薄膜晶体管及其制造方法
JP2020004859A (ja) * 2018-06-28 2020-01-09 堺ディスプレイプロダクト株式会社 薄膜トランジスタ、表示装置及び薄膜トランジスタの製造方法
US11616057B2 (en) 2019-03-27 2023-03-28 Intel Corporation IC including back-end-of-line (BEOL) transistors with crystalline channel material
KR20220078017A (ko) * 2020-12-02 2022-06-10 삼성디스플레이 주식회사 표시 패널 및 이를 포함하는 표시 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1489181A (zh) * 2002-09-18 2004-04-14 ������������ʽ���� 半导体装置的制造方法
CN1512596A (zh) * 2002-12-16 2004-07-14 ����Sdi��ʽ���� 具有轻掺杂漏区/偏移区（ldd/offset）结构的薄膜晶体管
US20040178452A1 (en) * 2003-02-28 2004-09-16 Seiko Epson Corporation Complementary thin film transistor circuit, electro-optical device, and electronic apparatus
US20140231813A1 (en) * 2011-10-03 2014-08-21 Panasonic Corporation Thin-film device, thin-film device array, and method of manufacturing thin-film device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5548132A (en) * 1994-10-24 1996-08-20 Micron Technology, Inc. Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions
JP2002299632A (ja) * 2001-03-30 2002-10-11 Sanyo Electric Co Ltd 半導体装置及びアクティブマトリクス型表示装置
CN100592534C (zh) * 2002-06-07 2010-02-24 索尼株式会社 显示装置及其制造方法、以及投影型显示装置
US7385223B2 (en) * 2003-04-24 2008-06-10 Samsung Sdi Co., Ltd. Flat panel display with thin film transistor
KR100606450B1 (ko) * 2003-12-29 2006-08-11 엘지.필립스 엘시디 주식회사 주기성을 가진 패턴이 형성된 레이저 마스크 및 이를이용한 결정화방법
US7184106B2 (en) * 2004-02-26 2007-02-27 Au Optronics Corporation Dielectric reflector for amorphous silicon crystallization
KR100839735B1 (ko) * 2006-12-29 2008-06-19 삼성에스디아이 주식회사 트랜지스터, 이의 제조 방법 및 이를 구비한 평판 표시장치
US8426865B2 (en) * 2007-06-22 2013-04-23 The Hong Kong University Of Science And Technology Polycrystalline silicon thin film transistors with bridged-grain structures
KR101860859B1 (ko) * 2011-06-13 2018-05-25 삼성디스플레이 주식회사 박막트랜지스터의 제조 방법, 상기 방법에 의해 제조된 박막트랜지스터, 유기발광표시장치의 제조방법, 및 상기 방법에 의해 제조된 유기발광표시장치
CN103151388B (zh) * 2013-03-05 2015-11-11 京东方科技集团股份有限公司 一种多晶硅薄膜晶体管及其制备方法、阵列基板
TWI653755B (zh) * 2013-09-12 2019-03-11 日商新力股份有限公司 顯示裝置、其製造方法及電子機器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1489181A (zh) * 2002-09-18 2004-04-14 ������������ʽ���� 半导体装置的制造方法
CN1512596A (zh) * 2002-12-16 2004-07-14 ����Sdi��ʽ���� 具有轻掺杂漏区/偏移区（ldd/offset）结构的薄膜晶体管
US20040178452A1 (en) * 2003-02-28 2004-09-16 Seiko Epson Corporation Complementary thin film transistor circuit, electro-optical device, and electronic apparatus
US20140231813A1 (en) * 2011-10-03 2014-08-21 Panasonic Corporation Thin-film device, thin-film device array, and method of manufacturing thin-film device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108417586A (zh) * 2018-03-13 2018-08-17 京东方科技集团股份有限公司 一种阵列基板的制备方法及阵列基板
CN108538860A (zh) * 2018-04-27 2018-09-14 武汉华星光电技术有限公司 顶栅型非晶硅tft基板的制作方法

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