CN105293423B - MEMS single-wafer integration method based on five layers of SOI silicon wafers - Google Patents
MEMS single-wafer integration method based on five layers of SOI silicon wafers Download PDFInfo
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- CN105293423B CN105293423B CN201510769734.0A CN201510769734A CN105293423B CN 105293423 B CN105293423 B CN 105293423B CN 201510769734 A CN201510769734 A CN 201510769734A CN 105293423 B CN105293423 B CN 105293423B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 36
- 239000010703 silicon Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000010354 integration Effects 0.000 title abstract description 6
- 235000012431 wafers Nutrition 0.000 title abstract 8
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000005516 engineering process Methods 0.000 claims abstract description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 238000002161 passivation Methods 0.000 claims abstract description 8
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 239000004411 aluminium Substances 0.000 claims abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000012360 testing method Methods 0.000 claims abstract description 4
- 239000010936 titanium Substances 0.000 claims abstract description 4
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000013459 approach Methods 0.000 claims description 3
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 2
- 238000005260 corrosion Methods 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Micromachines (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an MEMS single-wafer integration method based on five layers of SOI silicon wafers. The MEMS single-wafer integration method comprises the following steps: completing production of an integrated circuit part on a silicon wafer by adopting a standard SOI CMOS process; depositing a passivation layer on the silicon wafer so as to protect the integrated circuit part; performing photoetching at the back of the silicon wafer, etching backside silicon to an insulating layer, and etching the exposed insulating layer; performing photoetching on the front of the silicon wafer, and etching to remove silicon and the insulating layer on an MEMS structural area so as to expose a structural layer; sputtering a titanium layer and an aluminium layer on the front of the silicon wafer, performing photoetching to obtain a metal connection line between the MEMS structure and the integrated circuit; performing photoetching on the front of the silicon wafer, and etching to obtain the MEMS structure; and splitting, packaging and testing. According to the method disclosed by the invention, the problem of electrically isolating the integrated circuit from the MEMS structure in the current MEMS single-wafer integrated technology can be overcome; furthermore, a thick monocrystalline silicon structural layer is obtained by adopting a bulk silicon process; and thus, requirements of high-performance inertial MEMS sensors are satisfied.
Description
Technical field
The invention belongs to microelectromechanical systems micro-processing technology field, the silicon on more particularly to a kind of five layers of insulator
（Silicon on insulator, SOI）Microelectromechanical systems（Micro-electromechanical Systems,
MEMS）Method for integrating monolithic.
Background technology
In recent years, MEMS technology had obtained quick development, all had wide application space in many fields.By MEMS
Structure with drive, detection, signal processing circuit is integrated can reduce signal transmission attenuation on one chip, reduce circuit and make an uproar
Sound, the interference of suppression circuit parasitic capacitance can realize high s/n ratio, improve certainty of measurement, can also effectively reduce power consumption and body
Product.Successfully be integrated on single-chip for circuit and MEMS structure using surface treatment by foreign countries, but surface treatment mass is thick
Degree is small, and membrane stress is big, sacrificial layer structure release is difficult, it is difficult to meet the requirement of high-performance inertial sensor.Bulk silicon MEMS work
Skill mass is big, and structure depth-to-width ratio is high, can realize high performance MEMS sensor, but bulk silicon MEMS technique and CMOS technology collection
Into difficulty, in the world still without the single-chip integration scheme of ripe bulk silicon MEMS and circuit.
Number of patent application is：200410049792.8 patent is " a kind of single chip integrated with bulk silicon MEMS by cmos circuit
Method ", bulk silicon MEMS technique is employed while using Post-CMOS technologies again, can produce larger mass and height
Structure depth-to-width ratio, and can using monocrystalline silicon as MEMS structure material, reduce the stress problem in structure, increased
The inertia mass and detection electric capacity of capacitance type sensor, so as to improve the sensitivity of MEMS sensor, the hair integrated to MEMS
Exhibition and industrialization have great importance.But the above method is used, MEMS structure is relatively difficult with the isolation of circuit, and MEMS
Structural area thickness evenness is difficult control.
Number of patent application is a kind of 201210110743.5 patent " SOI MEMS method for integrating monolithic ", and the method is same
Sample uses Post-CMOS technologies and bulk silicon MEMS technique, can produce larger mass and structure depth-to-width ratio high, but should
Method MEMS structure carries out electrical isolation with circuit using air insulated groove, and the processing of isolation channel is also relatively difficult.
Circuit made by both the above method is identical with the circuit using the making of common monocrystalline silicon piece, it is impossible to utilize SOI
The advantages of material radioresistance, low-power consumption, high temperature resistant in circuit.
The content of the invention
In view of the shortcomings of the prior art, it is mono- it is an object of the invention to provide a kind of MEMS for being based on five layers of soi wafer
Piece integrated approach meets the requirement of high-performance inertial MEMS sensor.
A kind of to be based on five layers of MEMS method for integrating monolithic of soi wafer, the integrated approach is comprised the following steps：
S1, using five layers of soi wafer, the SOI CMOS technologies using standard on soi wafer circuit layer complete integrated electricity
The making on road；
S2, passivation layer is deposited on soi wafer circuit layer to be used to protect the integrated circuit, removes MEMS structure region
Passivation layer；
S3, mask, etching substrate layer silicon, until in exposing soi wafer are formed in soi wafer substrate layer photomask surface
First insulating barrier；
S4, the first insulating barrier that etching soi wafer substrate layer exposes；
S5, the photoetching on the surface of soi wafer circuit layer, etch soi wafer circuit layer silicon and expose second
Insulating barrier, exposes structure sheaf, forms MEMS structure area；
S6, in soi wafer circuit layer surface and the structure sheaf photomask surface for exposing, sputters titanium layer and aluminium lamination, photoetching
Corrosion obtains the metal connecting line between MEMS structure area and integrated circuit；
S7, in soi wafer circuit layer surface and the structure sheaf photomask surface for exposing, defines MEMS structure figure, adopts
DRIE anisotropic etchings are used, etching structure layer obtains MEMS structure；
S8, sliver, encapsulation, test.
Preferably, five layers of soi wafer in the step S1 include circuit layer, structure sheaf, substrate layer, positioned at circuit layer and
The second insulating barrier between structure sheaf and the first insulating barrier between structure sheaf and substrate layer, and monocrystalline silicon in circuit layer
Layer is relatively thin, for making SOI CMOS integrated circuits.
Preferably, silica is included in second insulating barrier and the first insulating barrier.
Technical scheme has the advantages that：
It is proposed by the present invention it is a kind of be based on five layers of MEMS method for integrating monolithic of soi wafer, combine surface Post-CMOS
With bulk silicon MEMS process advantage, using Post-CMOS technologies while employ bulk silicon MEMS technique again, can produce compared with
Big mass and structure depth-to-width ratio high, and can be using monocrystalline silicon as MEMS structure material, in reducing structure
Stress problem, increased the inertia mass and detection electric capacity of capacitance type sensor, so as to improve the sensitivity of MEMS sensor；
By the use of insulating barrier as etching self-stopping technology layer, prior art MEMS structure area thickness evenness shortcoming rambunctious can be overcome, made
Obtain MEMS structure area thickness good with property；Using the insulating barrier between two-layer, facilitate circuit region with MEMS structure area it is electric every
From；Using single one layer making circuit, the structural parameters of this layer disclosure satisfy that the making requirement of SOI CMOS integrated circuits, from
And the advantages of SOI materials radioresistance, low-power consumption, high temperature resistant in circuit can be utilized.In a word, can be overcome using the technology
Difficulty of the circuit with MEMS structure electrical isolation in current MEMS single slice integration techniques, it is possible to use SOI materials resist in circuit
The advantages of radiation, high temperature resistant, and bulk silicon technological can be used, the monocrystal silicon structure layer of thickness is obtained, meet high-performance inertial MEMS
The requirement of sensor.
Brief description of the drawings
Below by drawings and Examples, technical scheme is described in further detail.
Fig. 1 is a kind of the vertical of five layers of SOI materials being based on employed in five layers of MEMS method for integrating monolithic of SOI of the present invention
To structural representation；
Fig. 2 a-2f are work flow schematic diagram of the invention.
Description of reference numerals：1- circuit layers 2- the second insulating barrier 3- structure sheafs 4- the first insulating barrier 5- substrate layers 6-
Integrated circuit 7- passivation layer 8- metal connecting line 9-MEMS structures.
Specific embodiment
In order to have a clear understanding of technical scheme, its detailed structure will be set forth in the description that follows.Obviously, originally
Simultaneously deficiency is limited to the specific details that those skilled in the art is familiar with for the specific execution of inventive embodiments.Preferred reality of the invention
Apply example to be described in detail as follows, except these for describing in detail implement exception, there can also be other embodiment.
The present invention is described in further details with reference to the accompanying drawings and examples.
The material that the present embodiment is used is five layers of soi wafer, the thickness 200nm of circuit layer 1, N-type silicon, the Ω of resistivity 5 ~ 8/
cm；Circuit layer 1 is with the thickness 500nm of insulating barrier 2 between structure sheaf 3；60 μm of Laminate construction thickness, 0.01 ~ 0.1 Ω of resistivity/cm,
<110>Crystal orientation；Structure sheaf 3 is with 1 μm of 4 thickness of insulating barrier between substrate layer 5；300 microns of 4 thickness of substrate layer, N-type silicon.
The method for integrating monolithic, its step includes：
（1）Using five layers of soi wafer, the SOI CMOS technologies using standard on silicon wafer circuitry layer complete integrated circuit 6
Making（As shown in Figure 2 a）；
（2）The deposit protection integrated circuit 6 of passivation layer 7 part, removes the passivation layer 7 in MEMS structure region（Such as Fig. 2 b institutes
Show）；
（3）Mask, etching substrate layer silicon, until exposing SOI silicon are formed in five layers of photomask surface of soi wafer substrate layer 5
Insulating barrier 4 in piece, and etch away the insulating barrier 4 being exposed（As shown in Figure 2 c）；
（4）The photoetching on the surface of soi wafer circuit layer 1, the silicon of etched circuit layer 1 and the insulating barrier 2 for exposing, exposure
Go out structure sheaf 3, obtain MEMS structure area（As shown in Figure 2 d）；
（5）Make the metal connecting line between integrated circuit 6 and MEMS structure 9（As shown in Figure 2 e）：
（a）Sputter 500 titaniums and 8000 aluminium；
（b）Lithographic definition goes out metal connecting line figure；
（c）RIE（Reactive ion etching）Etching or the aluminium of wet etching 8000 and 500 titaniums, remove photoresist, are collected
Into the metal connecting line 8 between circuit 6 and MEMS structure 9；
（6）In five layers of surface of soi wafer circuit layer 1 and the photomask surface of structure sheaf 3 for exposing, MEMS structure figure is defined
Shape, using DRIE anisotropic etchings, etching structure layer 3 obtains MEMS structure 9（As shown in figure 2f）；
（7）Sliver, encapsulation, test.
Five layers of soi wafer in step S1 include circuit layer 1, structure sheaf 3, substrate layer 5, positioned at circuit layer 1 and structure sheaf 3
Between the second insulating barrier 2 and the first insulating barrier 4 between structure sheaf 3 and substrate layer 5, and monocrystalline silicon in circuit layer 1
Layer is relatively thin, for making SOI CMOS integrated circuits；Silica is included in second insulating barrier 2 and the first insulating barrier 4.
In above-described embodiment, original material can be adjusted as needed using five layers of soi wafer, each layer parameter of silicon chip.Splash
The thickness for penetrating titanium and aluminium can also be adjusted as needed.
It is proposed by the present invention it is a kind of be based on five layers of MEMS method for integrating monolithic of soi wafer, combine surface Post-CMOS
With bulk silicon MEMS process advantage, using Post-CMOS technologies while employ bulk silicon MEMS technique again, can produce compared with
Big mass and structure depth-to-width ratio high, and can be using monocrystalline silicon as MEMS structure material, in reducing structure
Stress problem, increased the inertia mass and detection electric capacity of capacitance type sensor, so as to improve the sensitivity of MEMS sensor；
By the use of insulating barrier as etching self-stopping technology layer, prior art MEMS structure area thickness evenness shortcoming rambunctious can be overcome, made
Obtain MEMS structure area thickness good with property；Using the insulating barrier between two-layer, facilitate circuit region with MEMS structure area it is electric every
From；Using single one layer making circuit, the structural parameters of this layer disclosure satisfy that the making requirement of SOI CMOS integrated circuits, from
And the advantages of SOI materials radioresistance, low-power consumption, high temperature resistant in circuit can be utilized.In a word, can be overcome using the technology
Difficulty of the circuit with MEMS structure electrical isolation in current MEMS single slice integration techniques, it is possible to use SOI materials resist in circuit
The advantages of radiation, high temperature resistant, and bulk silicon technological can be used, the monocrystal silicon structure layer of thickness is obtained, meet high-performance inertial MEMS
The requirement of sensor.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention rather than its limitations, to the greatest extent
Pipe has been described in detail with reference to above-described embodiment to the present invention, and those of ordinary skill in the art still can be to this hair
Bright specific embodiment is modified or equivalent, these without departing from spirit and scope of the invention any modification or
Equivalent, is applying within pending claims.
Claims (3)
1. it is a kind of to be based on five layers of MEMS method for integrating monolithic of soi wafer, it is characterised in that the integrated approach includes following step
Suddenly：
S1, using five layers of soi wafer, in soi wafer circuit layer（1）The SOI CMOS technologies of upper use standard complete integrated circuit
（6）Making；
S2, in soi wafer circuit layer（1）Upper deposit passivation layer（7）For protecting the integrated circuit（6）, remove MEMS structure
The passivation layer in region（7）；
S3, in soi wafer substrate layer（5）Photomask surface forms mask, etching substrate layer silicon, until in exposing soi wafer
First insulating barrier（4）；
S4, etches soi wafer substrate layer（5）The first insulating barrier for exposing（4）；
S5, in soi wafer circuit layer（1）Surface on photoetching, etch soi wafer circuit layer（1）Silicon and expose
Two insulating barriers（2）, expose structure sheaf（3）, form MEMS structure area；
S6, in soi wafer circuit layer（1）Surface and the structure sheaf for exposing（3）Photomask surface, sputters titanium layer and aluminium lamination, light
Carve the metal connecting line that corrosion is obtained between MEMS structure area and integrated circuit（8）；
S7, in soi wafer circuit layer（1）Surface and the structure sheaf for exposing（3）Photomask surface, defines MEMS structure figure,
Using DRIE anisotropic etchings, etching structure layer（3）, obtain MEMS structure（9）；
S8, sliver, encapsulation, test.
2. it is according to claim 1 to be based on five layers of MEMS method for integrating monolithic of soi wafer, it is characterised in that the step
Five layers of soi wafer in rapid S1 include circuit layer（1）, structure sheaf（3）, substrate layer（5）, positioned at circuit layer（1）And structure sheaf（3）
Between the second insulating barrier（2）And positioned at structure sheaf（3）And substrate layer（5）Between the first insulating barrier（4）, and circuit layer
（1）Middle monocrystalline silicon layer is relatively thin, for making SOI CMOS integrated circuits.
3. according to any one of claim 1 or 2 based on five layers of MEMS method for integrating monolithic of soi wafer, its feature
It is, second insulating barrier（2）With the first insulating barrier（4）Comprising silica.
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| CN110577185B (en) * | 2019-08-06 | 2021-11-16 | 西人马联合测控（泉州）科技有限公司 | MEMS structure, manufacturing method of MEMS structure and tire pressure sensor |
| CN113916208B (en) * | 2021-10-08 | 2023-03-17 | 中北大学 | A nano-grating three-axis MEMS gyroscope with reduced cross-coupling and crosstalk |
| CN118913491B (en) * | 2024-10-11 | 2025-01-24 | 中国工程物理研究院电子工程研究所 | A piezoresistive pressure sensor and a method for manufacturing the same |
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| US6511859B1 (en) * | 1999-03-12 | 2003-01-28 | California Institute Of Technology | IC-compatible parylene MEMS technology and its application in integrated sensors |
| CN1595633A (en) * | 2004-06-29 | 2005-03-16 | 北京大学 | A method for integrating CMOS circuit and bulk silicon MEMS uniwafer |
| CN102238463A (en) * | 2010-04-30 | 2011-11-09 | 比亚迪股份有限公司 | Method and chip for integrating silicon microphone device with IC (integrated circuit) single chip |
| CN102381681A (en) * | 2011-11-29 | 2012-03-21 | 北京大学 | Micromechanical structure and integrated circuit monolithic integrated processing method |
| CN102649537A (en) * | 2012-04-17 | 2012-08-29 | 中国工程物理研究院电子工程研究所 | SOI MEMS (silicon on insulator micro electro mechanical system) one chip integrating method |
| CN104796832A (en) * | 2015-02-16 | 2015-07-22 | 迈尔森电子（天津）有限公司 | A MEMS microphone and a formation method thereof |
-
2015
- 2015-11-12 CN CN201510769734.0A patent/CN105293423B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6511859B1 (en) * | 1999-03-12 | 2003-01-28 | California Institute Of Technology | IC-compatible parylene MEMS technology and its application in integrated sensors |
| CN1595633A (en) * | 2004-06-29 | 2005-03-16 | 北京大学 | A method for integrating CMOS circuit and bulk silicon MEMS uniwafer |
| CN102238463A (en) * | 2010-04-30 | 2011-11-09 | 比亚迪股份有限公司 | Method and chip for integrating silicon microphone device with IC (integrated circuit) single chip |
| CN102381681A (en) * | 2011-11-29 | 2012-03-21 | 北京大学 | Micromechanical structure and integrated circuit monolithic integrated processing method |
| CN102649537A (en) * | 2012-04-17 | 2012-08-29 | 中国工程物理研究院电子工程研究所 | SOI MEMS (silicon on insulator micro electro mechanical system) one chip integrating method |
| CN104796832A (en) * | 2015-02-16 | 2015-07-22 | 迈尔森电子（天津）有限公司 | A MEMS microphone and a formation method thereof |
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