CN105280134A - Shift register circuit and operation method thereof - Google Patents

Abstract

A shift register circuit and an operation method thereof, the register circuit comprising an input circuit, a first pull-down circuit, a pull-up circuit, a second pull-down circuit and a first compensation circuit. The input circuit is used to output a drive circuit control signal, the first pull-down circuit is electrically coupled to the input circuit, and is used to pull down the drive circuit control signal to a low voltage level, the pull-up circuit is electrically coupled to the input circuit, and is used to output an n-th level gate drive signal according to the drive circuit control signal, the second pull-down circuit is electrically coupled to the pull-up circuit, and is used to pull down the n-th level gate drive signal to a low voltage level, and when the potential of the first end of the first compensation circuit is greater than the potential of the second end of the first compensation circuit, the first compensation circuit generates a first current flowing from the first end to the second end to compensate for the drive circuit control signal.

Description

Shift register circuit and method of operation thereof

technical field

The present invention relates to a shift register circuit, in particular to a shift register circuit applied to an embedded touch display device and an operation method thereof.

Background technique

The existing in-cell touch display device includes a display panel with touch sensing elements and a gate drive circuit, the gate drive circuit also includes a plurality of shift register circuits, and the shift register circuits are used to correctly output a plurality of gate driving signals to drive a plurality of pixel circuits in the display panel. When the in-cell touch display device senses that a touch event has occurred, the in-cell touch display device will enter the touch sensing period for sensing touch events from the display period for normally displaying the display screen. The shift register circuit outputting the gate driving signal will stop outputting the gate driving signal, and the embedded touch display device will stop updating the display screen and perform touch sensing at the same time. At this time, the shift register circuit has received the drive signal but has not yet output the gate drive signal, the drive signal will leak its voltage level due to the leakage path in the shift register circuit, so when the embedded touch display device ends When the touch sensing period returns to the normal display period, the drive signal of the shift register circuit that should output the gate drive signal is reduced due to leakage, which causes the gate drive signal output by the shift register circuit to be inconsistent with the touch sense. The gate drive signal output before the test period has different capabilities, which causes horizontal stripes to appear on the display screen, resulting in a poor viewing effect for the user when watching the display screen.

Contents of the invention

In order to effectively solve the defect that horizontal stripes appear on the display screen of the in-cell touch display device due to leakage of the gate drive signal during the touch sensing period, the present invention proposes an embodiment of a shift register circuit, which includes The input circuit, the first pull-down circuit, the pull-up circuit, the second pull-down circuit and a first compensation circuit, the input circuit is used to output a driving circuit control signal according to the n-1th stage gate driving signal, the first lower The pull-up circuit is electrically coupled with the input circuit, and is used to pull down the control signal of the drive circuit to a low voltage level, and the pull-up circuit is electrically coupled with the input circuit, and is used to output an n-th gate according to the control signal of the drive circuit. pole drive signal, the second pull-down circuit is electrically coupled to the pull-up circuit, and is used to pull down the nth gate drive signal to a low voltage level, the first compensation circuit has a first end and a second end, The first end of the first compensation circuit is electrically coupled to a first compensation circuit control signal, the second end of the first compensation circuit is electrically coupled to the input circuit and the pull-up circuit, and during a touch sensing period, the second end of the first compensation circuit is electrically coupled to the input circuit and the pull-up circuit. The control signal of a compensation circuit is at a high voltage level, the gate driving signal of the nth level is disabled, and when the potential of the first terminal of the first compensation circuit is greater than the potential of the second terminal of the first compensation circuit, the first compensation circuit generates A first current flowing from the first terminal to the second terminal compensates the driving circuit control signal.

In a preferred embodiment of the present invention, the above-mentioned first compensation circuit further includes a first diode and a second diode, and both the first diode and the second diode include an anode terminal and a The negative terminal, the positive terminal of the first diode is electrically coupled to the control signal of the first compensation circuit, the negative terminal of the first diode is electrically coupled to the negative terminal of the second diode, and the second diode The positive end of the body is electrically coupled to the input circuit and the pull-up circuit.

In a preferred embodiment of the present invention, the size of the above-mentioned second diode is larger than that of the first diode.

In a preferred embodiment of the present invention, the above-mentioned first compensation circuit further includes a second input circuit, a first transistor, a second transistor, and a third transistor, and the first transistor has a first terminal, a first Two terminals and a control terminal, the first terminal of the first transistor is electrically coupled to the second input circuit, the control terminal of the first transistor is electrically coupled to a control signal, the second terminal of the first transistor is connected to the low voltage circuit Electrically coupled, the second transistor has a first terminal, a second terminal and a control terminal, the first terminal of the second transistor is used to receive the first compensation circuit control signal, the control terminal of the second transistor is connected to the first terminal The first end of a transistor is electrically coupled, the third transistor has a first end, a second end and a control end, the first end of the third transistor is electrically coupled to the second end of the second transistor, and the third transistor is electrically coupled to the second end of the second transistor. The control terminal of the three transistors is used to receive the control signal of the first compensation circuit, and the second terminal of the third transistor is electrically coupled to the second terminal of the first compensation circuit.

In a preferred embodiment of the present invention, the above-mentioned first compensation circuit further includes a first transistor, a second transistor, a third transistor and a fourth transistor, the first transistor has a first terminal, a second terminal and a control terminal, the first terminal of the first transistor is used to receive a first scan signal, the control terminal of the first transistor is used to receive an n-1th level gate drive signal, and the second transistor has a first One terminal, a second terminal and a control terminal, the first terminal of the second transistor is used to receive a second scan signal, the control terminal of the second transistor is used to receive an n+1th stage gate drive signal, The second terminal of the second transistor is electrically coupled to the second terminal of the first transistor. The third transistor has a first terminal, a second terminal and a control terminal. The first terminal of the third transistor is used to receive the first terminal. A compensation circuit control signal, the control terminal of the third transistor is electrically coupled to the second terminal of the first transistor, the fourth transistor has a first terminal, a second terminal and a control terminal, the first terminal of the fourth transistor Electrically coupled with the second end of the third transistor, the control end of the fourth transistor is used to receive the control signal of the first compensation circuit, the second end of the fourth transistor is electrically coupled with the second end of the first compensation circuit .

In a preferred embodiment of the present invention, the above-mentioned shift register circuit further includes a second compensation circuit, which has a first terminal and a second terminal, and the first terminal of the second compensation circuit is connected to a second compensation circuit The control signal is electrically coupled, and the second end of the second compensation circuit is electrically coupled to the input circuit and the pull-up circuit.

The present invention further proposes an operation method of a shift register circuit. The shift register circuit includes a pull-up circuit and a compensation circuit. The pull-up circuit is used to output an n-th stage gate drive signal according to a drive circuit control signal. The compensation circuit has a first terminal and a second terminal, the first terminal of the compensation circuit is electrically coupled to a compensation circuit control signal, and the second terminal of the compensation circuit is electrically coupled to the pull-up circuit, wherein the shift register circuit The operation method includes: during a touch sensing period, the gate driving signal of the nth stage is disabled, the compensation circuit control signal is at a high voltage level, and the potential of the first end of the first compensation circuit is greater than that of the first compensation circuit The potential of the second end of the compensation circuit generates a first current flowing from the first end to the second end to compensate the driving circuit control signal.

In other embodiments of the present invention, the above-mentioned operation method of the shift register circuit further includes: during a display period, the gate driving signal of the nth stage is enabled during the display period, and the compensation circuit control signal is at a low voltage level , the potential of the second terminal of the first compensation circuit is greater than the potential of the first terminal of the first compensation circuit, and the compensation circuit generates a second current flowing from the second terminal to the first terminal.

The embodiment of the shift register circuit proposed by the present invention has the above-mentioned compensation circuit, so the shift register circuit that should output the gate drive signal can use the current generated by the compensation circuit to compensate the drive circuit during the touch sensing period. Therefore, when the touch sensing period ends, the drive circuit control signal of the shift register circuit that should output the gate drive signal still has the same driving capability as the drive circuit control signal before the touch sensing period, avoiding the The driving ability of the circuit control signal is reduced, and horizontal stripes appear on the display screen.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are described below in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of an embodiment of an in-cell touch display device.

FIG. 2 is a schematic diagram of Embodiment 1 of the shift register circuit of the present invention.

FIG. 3A is a schematic diagram of Embodiment 1 of the compensation circuit of the present invention.

FIG. 3B is a schematic diagram of Embodiment 2 of the compensation circuit of the present invention.

FIG. 4A is a schematic diagram of Embodiment 3 of the compensation circuit of the present invention.

FIG. 4B is a schematic diagram of Embodiment 4 of the compensation circuit of the present invention.

FIG. 4C is a schematic diagram of Embodiment 5 of the compensation circuit of the present invention.

FIG. 5A is a schematic diagram of Embodiment 1 of the second input circuit of the present invention.

FIG. 5B is a schematic diagram of Embodiment 2 of the second input circuit of the present invention.

FIG. 6A is a schematic diagram of Embodiment 6 of the compensation circuit of the present invention.

FIG. 6B is a schematic diagram of Embodiment 7 of the compensation circuit of the present invention.

FIG. 7 is a schematic diagram of a signal timing embodiment of the present invention.

FIG. 8 is a schematic diagram of another signal timing embodiment of the present invention.

FIG. 9 is a schematic diagram of Embodiment 2 of the shift register circuit of the present invention.

FIG. 10 is a schematic diagram of an embodiment of the operation method of the shift register circuit of the present invention.

FIG. 11 is a schematic diagram of another embodiment of the operation method of the shift register circuit of the present invention.

Explanation of reference signs:

10 Embedded touch display device

11 data drive circuit

12 gate drive circuit

121 shift register circuit

1211 input circuit

1212 first pull-down circuit

1213 pull-up circuit

1214 second pull-down circuit

1215 first compensation circuit

1216 second compensation circuit

13 display panel

14 Touch Sensing Circuit

131 pixel unit

132 touch sensing units

40 second input circuit

M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M31, M32 Transistors

Bi input signal

G _n- 5 level n-5 gate drive signal

G _n-4 n-4 level gate drive signal

G _n- 3 level n-3 gate drive signal

G _n- 2 level n-2 gate drive signal

G _n- 1 level n-1 gate drive signal

G _n nth stage gate drive signal

G _n+ 1 level n+1 gate drive signal

CK first clock signal

XCK second clock signal

VGL low voltage level

C1, C2, C3, C4 capacitors

Q _n drive circuit control signal

Reset1 first compensation circuit control signal

Reset2 second compensation circuit control signal

D1 first diode

D2 second diode

V ₁ , V ₂ high voltage level

T ₁ , T ₂ , T ₃ , T _D , T _S period

U2D first scan signal

D2U second scan signal

L _1, L _2, L _n columns

detailed description

1 is an embodiment of an in-cell touch display device 10. The in-cell touch display device 10 includes a data drive circuit 11, a gate drive circuit 12, a display panel 13, a touch sensing circuit 14 and A clock control circuit 15, the display panel 13 includes a plurality of pixel units 131 and a plurality of touch sensing units 132, the data drive circuit 11 is electrically coupled with the plurality of pixel units 131, and is used to provide a plurality of display data to the circuit The plurality of pixel units 131 are electrically coupled, and the touch sensing circuit 14 is electrically coupled to the plurality of touch sensing units 132 for receiving touch sensing signals of the plurality of touch sensing units 132, so as to To determine the position of the touch event, the gate drive circuit 12 also includes a plurality of shift register circuits 121, each shift register circuit 121 is electrically coupled to a corresponding plurality of pixel units 131, and the shift register circuits 121 are used for The plurality of pixel units 131 electrically coupled can be turned on according to the gate driving signal output by the shift register circuit 121, so that the plurality of pixel units 131 can receive a plurality of display data at a correct time period and display accordingly. The pulse control circuit 15 is electrically coupled with the data driving circuit 11, the touch sensing circuit 14 and a plurality of shift register circuits 121, and is used to provide a plurality of clock signals, such as the first clock signal CK, the second clock signal The pulse signal XCK and the compensation circuit control signal Reset are sent to a plurality of shift register circuits 121, and the output clock signal is controlled according to the operation period of the embedded touch display device 10 to the electrically coupled data drive circuit 11 and touch sense Test circuit 14.

FIG. 2 is an embodiment of the shift register 121 of the present invention, and the nth stage shift register 121 is taken as an example. The n-th shift register 121 includes an input circuit 1211 , a first pull-down circuit 1212 , a second pull-down circuit 1214 , a pull-up circuit 1213 and a first compensation circuit 1215 . The input circuit 1211 includes a transistor M4, the transistor M4 includes a first terminal, a control terminal and a second terminal, the first terminal of the transistor M4 is used to receive an input signal Bi, and the control terminal of the transistor M4 is used to receive the above The second terminal of the transistor M4 is used to output a driving circuit control signal Q _n for the n−1th stage gate driving signal G _n−1 outputted by the shift register 121 of one stage. The shift register 121 of the nth stage further includes a capacitor C1. The capacitor C1 includes a first terminal and a second terminal. The first terminal of the capacitor C1 is further electrically coupled to a first clock signal CK.

The first pull-down circuit 1212 includes a transistor M1 , a transistor M2 and a transistor M3 , and is used for pulling down the driving circuit control signal _Qn to a low voltage level VGL. The transistor M1 includes a first terminal, a control terminal and a second terminal. The first terminal of the transistor M1 is used to receive the input signal Bi, and the control terminal of the transistor M1 is used to receive the output from the shift register 121 of the next stage. The gate driving signal Gn ₊₁ of the _n +1th stage, and the second terminal of the transistor M1 is electrically coupled to the driving circuit control signal Qn. The transistor M2 includes a first terminal, a control terminal and a second terminal. The first terminal of the transistor M2 is electrically coupled to the second terminal of the capacitor C1. The control terminal of the transistor M2 is used to receive the driving circuit control signal Q _n , the second terminal of the transistor M2 is electrically coupled to the low voltage level VGL, wherein the low voltage level VGL may be a logic low potential. The transistor M3 includes a first terminal, a control terminal and a second terminal. The first terminal of the transistor M3 _is electrically coupled to the driving circuit control signal Qn, and the control terminal of the transistor M3 is electrically coupled to the second terminal of the capacitor C1. connected, the second end of the transistor M3 is electrically coupled to the low voltage level VGL.

The pull-up circuit 1213 includes a transistor M7, which is used to output an _nth stage gate drive signal _Gn according to the drive circuit control signal Qn. The transistor M7 includes a first terminal, a control terminal and a second terminal. The transistor M7 The first end of the transistor M7 is used to receive the first clock signal CK, the control end of the transistor M7 is used to receive the drive circuit control signal Q _n , and the second end of the transistor M7 is used to output the nth-level gate drive signal G _n , in addition, the gate driving signal Gn of the _nth stage is further electrically coupled to the first end of a capacitor C2, and the second end of the capacitor C2 _is electrically coupled to the driving circuit control signal Qn.

The second pull-down circuit 1214 includes a transistor M5 and a transistor M6, and is used to pull down the gate driving signal G _n of the nth stage to a low voltage level VGL. The transistor M5 includes a first terminal, a control terminal and a second terminal, The first terminal of the transistor M5 is electrically coupled to the gate driving signal Gn of the _nth stage, the control terminal of the transistor M5 is electrically coupled to a second clock signal XCK, and the second terminal of the transistor M5 is electrically coupled to the low-voltage circuit. The flat VGL is electrically coupled. The transistor M6 includes a first terminal, a control terminal, and a second terminal. The first terminal of the transistor M6 is electrically coupled to the gate drive signal Gn of the _nth stage, and the control terminal of the transistor M6 is connected to the second terminal of the capacitor C1. Electrically coupled, the second end of the transistor M6 is electrically coupled to the low voltage level VGL.

A first compensation circuit 1215, which has a first end and a second end, the first end of the first compensation circuit 1215 is electrically coupled to a first compensation circuit control signal Reset1, the second end of the first compensation circuit It _is electrically coupled with the driving circuit control signal Qn.

Please refer to FIG. 3A and FIG. 3B . FIG. 3A and FIG. 3B are embodiments of the above-mentioned first compensation circuit 1215 . Please refer to FIG. 3A first. FIG. 3A is the first embodiment of the above-mentioned first compensation circuit 1215. The first compensation circuit 1215 may include a first diode D1 and a second diode D2. The first diode D1 and the second diode D2 both include a positive terminal and a negative terminal, the positive terminal of the first diode D1 is electrically coupled to the first compensation circuit control signal Reset1, and the negative terminal of the first diode D1 is electrically coupled to the first compensation circuit control signal Reset1. The negative terminal of the second diode D2 is electrically coupled, and the positive terminal of the second diode D2 is electrically coupled to the driving circuit control signal Qn. FIG. 3B is the second embodiment of the above-mentioned first compensation circuit 1215. The first compensation circuit 1215 may include a transistor M31 and a transistor M32. The transistor M31 includes a first terminal, a control terminal and a second terminal. The transistor M32 includes A first terminal, a control terminal and a second terminal, the first terminal of the transistor M31 is electrically coupled to the control terminal of the transistor M31 and the first compensation circuit control signal Reset1, the second terminal of the transistor M31 is connected to the second terminal of the transistor M32 The terminal is electrically coupled, and the first terminal of the transistor M32 is electrically coupled to the control terminal of the transistor M32 and the driving circuit control signal Qn.

Please refer to FIG. 4A. FIG. 4A is a third embodiment of the above-mentioned first compensation circuit 1215, which includes a capacitor C3, a second input circuit 40, a transistor M11, a transistor M8, and a transistor M9. The transistor M11 has a first terminal, a first Two terminals and a control terminal, the first terminal of the transistor M11 is electrically coupled to the second input circuit 40, the control terminal of the transistor M11 is electrically coupled to the _nth stage gate drive signal Gn, and the second terminal of the transistor M11 Electrically coupled to the low voltage level VGL. The transistor M8 has a first terminal, a second terminal and a control terminal. The first terminal of the transistor M8 is electrically coupled to the first compensation circuit control signal Reset1, and the control terminal of the transistor M8 is electrically coupled to the first terminal of the transistor M11. The second end of the transistor M8 is electrically coupled to the capacitor C3. The capacitor C3 has a first terminal and a second terminal, the first terminal of the capacitor C3 is electrically coupled to the second terminal of the transistor M8, and the second terminal of the capacitor C3 is electrically coupled to the control terminal of the transistor M8. The transistor M9 has a first terminal, a second terminal and a control terminal, the first terminal of the transistor M9 is electrically coupled to the second terminal of the transistor M8, the control terminal of the transistor M9 receives the first compensation circuit control signal Reset1, and the transistor M9 The second terminal of M9 is electrically coupled to the driving circuit control signal Qn.

Please refer to FIG. 4B . FIG. 4B is a fourth embodiment of the above-mentioned first compensation circuit 1215 . The difference between FIG. 4B and FIG. 4A is that the control terminal of the transistor M11 is electrically coupled to the first clock signal CK.

Please refer to FIG. 4C. FIG. 4C is the fifth embodiment of the above-mentioned first compensation circuit 1215. The difference between FIG. 4C and FIG. 4A is that FIG. 4C also includes a transistor M12. The transistor M12 has a first terminal, a second terminal and A control terminal, the first terminal of the transistor M12 is electrically coupled to the first terminal of the transistor M11, the control terminal of the transistor M12 is electrically coupled to the first clock signal CK, and the second terminal of the transistor M12 is connected to the low voltage level electrically coupled. Wherein, the transistor M12 is used for maintaining the control terminal of the transistor M8 at the low voltage level VGL according to the first clock signal CK.

Please refer to FIG. 5A, FIG. 5A is the first embodiment of the above-mentioned second input circuit 40, the second input circuit 40 includes a transistor M10, the transistor M10 has a first terminal, a second terminal and a control terminal, the first terminal of the transistor M10 One terminal is electrically coupled to the high voltage level VGH, the control terminal of the transistor M10 receives the n-1th stage gate driving signal Gn _-1 , and the second terminal of the transistor M10 is electrically coupled to the first terminal of the transistor M11 , in addition, the first end of the transistor M10 may also be electrically coupled to the n-1th stage gate driving signal Gn _-1 , as shown in FIG. 5B .

Since the pixel unit 131 of the display panel ₁₃ can _be driven in the direction from column L to _column L as shown in FIG. ₁ , or from column L to column L, the present invention further proposes the following first compensation An embodiment of circuit 1215.

Please refer to FIG. 6A . FIG. 6A is a sixth embodiment of the first compensation circuit 1215 , which includes a capacitor C4 , a transistor M13 , a transistor M14 , a transistor M15 and a transistor M16 . The transistor M13 has a first terminal, a control terminal and a second terminal, the first terminal of the transistor M13 is electrically coupled to a first scanning signal U2D, the control terminal of the transistor M13 is connected to the n-1th stage gate driving signal Gn _-1 is electrically coupled, and the second terminal of the transistor M13 is electrically coupled to the transistor M14. The transistor M14 has a first terminal, a control terminal and a second terminal, the first terminal of the transistor M14 is electrically coupled to a second scanning signal D2U, the control terminal of the transistor M14 is connected to the n+1th stage gate driving signal Gn ₊₁ is electrically coupled, and the second end of the transistor M14 is electrically coupled to the second end of the transistor M13. The transistor M15 has a first terminal, a control terminal and a second terminal. The first terminal of the transistor M15 is electrically coupled to the first compensation circuit control signal Reset1, and the control terminal of the transistor M15 is electrically coupled to the second terminal of the transistor M13. Coupled, the second end of the transistor M15 is electrically coupled to the capacitor C4. The capacitor C4 has a first terminal and a second terminal, the first terminal of the capacitor C4 is electrically coupled to the second terminal of the transistor M15, and the second terminal of the capacitor C4 is electrically coupled to the control terminal of the transistor M15. The transistor M16 has a first terminal, a control terminal and a second terminal, the first terminal of the transistor M16 is electrically coupled to the second terminal of the transistor M15, the control terminal of the transistor M16 is electrically connected to the first compensation circuit control signal Reset1 Coupled, the second end of the transistor M16 is electrically coupled to the driving circuit control signal Qn. Wherein, when the first scanning signal U2D is enabled, the pixel unit 131 of the display panel _{13 is} driven from column L to column L shown in FIG. The pixel unit 131 is driven from column L _n to column L ₁ shown in FIG. 1 , and the enable time and disable time of the first scan signal U2D and the second scan signal D2U are opposite.

Please refer to FIG. 6B . FIG. 6B is a seventh embodiment of the first compensation circuit 1215 . The difference between FIG. 6B and FIG. 6A is that the seventh embodiment of the first compensation circuit 1215 in FIG. 6B also includes a transistor M17 and a transistor M18 . The transistor M17 has a first terminal, a control terminal and a second terminal, the first terminal of the transistor M17 is electrically coupled to the second terminal of the transistor M13, the control terminal of the transistor M17 is connected to the nth stage gate drive signal G _n Electrically coupled, the second end of the transistor M17 is electrically coupled to the low voltage level VGL. The transistor M18 has a first terminal, a control terminal and a second terminal. The first terminal of the transistor M18 is electrically coupled to the second terminal of the transistor M13. The control terminal of the transistor M18 is electrically coupled to the first clock signal CK. connected, the second end of the transistor M18 is electrically coupled to the low voltage level VGL. Wherein, the transistor M17 and the transistor M18 are used to maintain the control terminal of the transistor M15 , that is, the second terminal of the transistor M13 at the low voltage level VGL according to the _nth stage gate driving signal Gn and the first clock signal CK.

Please refer to FIG. 7. FIG. 7 is a signal timing diagram of an embodiment of the shift register 121, which includes the first clock signal CK, the second clock signal XCK, the input signal Bi, the drive circuit control signal Q _n , the nth stage The gate driving signal G _n , the gate driving signal G _n-1 of the n-1th stage, and the gate driving signal G _n+1 of the n+1st stage, wherein the first clock signal CK and the second clock signal XCK The enabling time and disabling time are reversed.

The operation method of the embodiment of the shift register 121 will be described below with reference to FIG. 2 and FIG. 7 when the in-cell touch display device 10 operates in a display period when no touch event occurs and the screen is normally displayed and updated.

Firstly, the gate drive signal G _n-1 of the n-1th stage is at the enable voltage level, for example, a period T ₁ of logic high potential, and at this time the gate drive signal G _n+1 of the n+1-th stage is not The enable voltage level is, for example, a logic low level, the input signal Bi is an enable voltage level, for example, a logic high level, the first clock signal CK is a non-enable voltage level, for example, a logic low level, and the second The clock signal XCK is at an enabling voltage level, such as a logic high level. Therefore, the transistor M4 is turned on, the driving circuit control signal Qn is raised to a high voltage level V ₁ because the transistor M4 is turned on, the transistor M1 is turned off, and the transistor M2 is turned on because the driving circuit control signal Qn is raised to a high voltage level V ₁ is turned on, and the second end of the capacitor C1 is pulled down to the low voltage level VGL, so the transistor M3 and the transistor M6 are turned off, and the transistor M7 is turned on due to the driving circuit control signal Qn, but because the first clock signal CK is currently non- The voltage level is enabled, so the gate driving signal Gn of the _nth stage is logic low potential, and the transistor M5 is turned on to maintain the gate driving signal Gn of the _nth stage at the low voltage level VGL.

Then in the period T ₂ , the gate driving signal Gn _-1 of the n-1th stage, the gate driving signal Gn+1 of the _n+ 1th stage and the second clock signal XCK are logic low potentials, and the input signal Bi and the The first clock signal CK is at logic high potential, at this time, the transistor M4 and the transistor M1 are turned off, the transistor M2 is kept on because of the driving circuit control signal Qn, the transistor M3 and the transistor M6 are kept off, and the transistor M5 is turned on because of the second clock signal XCK. The low potential is off, and at this time, since the first clock signal CK is logic high potential and the transistor M7 remains on, the transistor M7 will output the nth stage gate driving signal Gn of logic high potential, and the _nth stage gate The driving signal G _n increases the driving circuit control signal Qn from the high voltage level V ₁ to the high voltage level V ₂ through the capacitor C2 , further enhancing the driving capability of the transistor M7 .

In the period T3, the n _- 1th stage gate drive signal G _n-1 , the input signal Bi and the first clock signal CK are logic low potentials, the second clock signal XCK and the n+1th stage gate drive The signal Gn ₊₁ is a logic high potential, the transistor M4 is turned off, and the transistor M1 is turned on because of the n+1th stage gate drive signal Gn ₊₁ , and at this time, because the input signal Bi is a logic low potential, the drive circuit controls The signal Qn is pulled down to a logic low potential by the transistor M1. Since the drive circuit control signal Qn is pulled down to a logic low potential, the transistors M2 and M7 are turned off. At this time, the capacitor C1 utilizes the first clock signal stored in the previous period T2 The logic high potential of CK turns on the transistor M3 and the transistor M6, so that the drive circuit control signal Qn and the gate drive signal G _n of the nth stage are maintained at a logic low potential, and the transistor M5 is turned on, and the gate drive signal of the nth stage Gn _is maintained at a logic low level.

According to the above content, it can be known that when the in-cell touch display device 10 operates the display period, after the transistor M7 is turned on by the driving circuit control signal Qn in the period T1, immediately after the period T2, it will be activated according to the first clock signal CK. The gate driving signal Gn of the _nth stage is output, so the driving circuit control signal Qn is less likely to be affected by electric leakage and cause its driving capability to decline.

Please refer to FIG. 8. FIG. 8 is a signal timing diagram of an embodiment of the shift register 121 operating in a touch sensing period, which includes the first clock signal CK, the second clock signal XCK, the n-1th gate pole drive signal G _n-1 , n-2th gate drive signal G _n-2 , n-3th gate drive signal G _n-3 , n-4th gate drive signal G _n-4 , The n-5th level gate driving signal Gn _-5 , the nth level gate driving signal Gn, the _n +1st level gate driving signal Gn ₊₁ , and a first compensation circuit control signal Reset1, wherein the first level The enabling time and disabling time of the first clock signal CK and the second clock signal XCK are opposite.

The operation method of the embodiment of the shift register 121 when the in-cell touch display device 10 operates in the touch sensing period when a touch event occurs will be described below with reference to FIG. 2 and FIG. 8 .

When the in-cell touch display device 10 operates in the above-mentioned display period, that is, the period T _D in FIG. Level n-5 gate drive signal G _n-5 , gate drive signal n-4 level G _n-4 , gate drive signal n-3 level G _n-3 , gate drive signal n-2 level The signal Gn _-2 and the n-1th level gate driving signal Gn _-1 , so the display panel 13 of the in-cell touch display device 10 will update the pixel units 131 of the corresponding row to display the picture. A compensation circuit control signal Reset1 is a low voltage level, such as a logic low level. When a touch event occurs on the in-cell touch display device 10, the in-cell touch display device 10 is operating in the touch sensing period, that is, the period T _S in FIG. A touch event occurs after the bit register circuit 121 outputs the n-1th level gate driving signal G _n-1 , so the control signal Reset1 of the first compensation circuit is converted to a high voltage level, for example, a logic high level, and due to the During the touch sensing period, the in-cell touch display device 10 stops updating the display screen, so it is used to provide a logic high voltage to the transistor M7 to output the first clock signal CK and the second gate driving signal Gn of the _nth stage. The second clock signal XCK is maintained at a logic low level due to the touch sensing period, so that the nth-level shift register 121 that should output the n-level gate driving signal G _n does not output the n-level gate driving signal G _n .

However, at this time, the nth stage shift register 121 has received the n-1th stage gate drive signal Gn _-1 , so the driving circuit control signal Qn has been raised to the above _- mentioned high voltage level V1, but the _nth stage The shift register 121 does not output the gate driving signal Gn of the _nth stage during the touch sensing period, so the driving circuit control signal Qn needs to maintain _a high voltage level V1 until the shift register 121 of the _nth stage outputs the nth stage Gate drive signal G _n . Before outputting the gate driving signal _Gn of the _nth stage, the driving circuit control signal Qn will leak due to the leakage path formed by the transistor M1, the transistor M3 and the transistor M4. Therefore, when the leakage occurs, the first compensation circuit control signal Reset1 The logic high potential of the drive circuit 1215 will be higher than the current voltage level of the drive circuit control signal _Qn , and the first compensation circuit 1215 naturally generates a first current flowing from its first terminal to the second terminal to compensate the drive circuit control signal _Qn , The voltage level of the driving circuit control signal Q _n can be maintained at the high voltage level V ₁ during the touch sensing period when the nth gate driving signal G _n is not output.

When the touch sensing period ends and the in-cell touch display device 10 operates in the display period again, the first compensation circuit control signal Reset1 is converted to a low voltage level, and the first clock signal CK is restored to a logic high level so that The nth stage shift register 121 can continue to output the _nth stage gate driving signal Gn, the second clock signal XCK is at a logic low level relative to the first clock signal CK, and the driving circuit control signal Qn will be _affected by the capacitance C2 is boosted to the high voltage level V ₂ by the _nth gate driving signal Gn, as shown in FIG. 7 , so the in-cell touch display device 10 continues to update the display screen normally.

The operation modes of different embodiments of the first compensation circuit 1215 are described below with illustrations.

Please take FIG. 3A, FIG. 3B and FIG. 8 as an example. When the in-cell touch display device 10 operates in the above-mentioned touch sensing period, the first compensation circuit coupled to the anode of the first diode D1 The control signal Reset1 is converted to a high voltage level, and the first diode D1 whose positive terminal is electrically coupled with the first compensation circuit control signal Reset1 is turned on, and the electrical properties of the current electronic components cannot be idealized due to technical problems. The second diode D2 still has current flowing through it. Therefore, when the first compensation circuit control signal _Reset1 is higher than the voltage level of the current drive circuit control signal Qn, the first embodiment of the first compensation circuit 1215 is naturally generated by A first current flowing from the first terminal to the second terminal compensates the driving circuit control signal Q _n . When the in-cell touch display device 10 ends the touch sensing period and operates in the above-mentioned display period, the first compensation circuit control signal _Reset1 is converted to a low voltage level, so the voltage level of the driving circuit control signal Qn will be higher than the first compensation circuit control signal Reset1, at this time the second diode D2 is turned on, because the electrical properties of electronic components cannot be idealized, the first diode D1 will have current flowing through it, so the first compensation The circuit 1215 will generate a second current flowing from the second end to the first end, and in order to reduce the leakage of the driving circuit control signal Q _n through the first compensation circuit 1215 during the display period, the second diode of the first compensation circuit 1215 The size of D2 or transistor T2 can be larger than that of the first diode D1 or transistor T1, so that the second current is smaller than the above-mentioned first current, and the current amount of the second current can be effectively reduced.

Next, take FIG. 4A, FIG. 4B, FIG. 4C, FIG. 5A, FIG. 5B, and FIG. 8 as examples. First, when the in-cell touch display device 10 operates in the above-mentioned display period and the n-1th level gate driving signal G When _n-1 is a logic high potential, the first compensation circuit control signal Reset1 is a low voltage level, and the transistor M10 is turned on because the n-1th stage gate drive signal Gn _-1 is a logic high potential, so that the control terminal and The transistor M8 electrically coupled to the second terminal of the transistor M10 is also turned on, and since the shift register 121 of the current stage has not yet output the gate driving signal G _n of the nth stage, the transistor M11 is turned off, and the control terminal is electrically coupled to the first stage The transistor M9 of a compensation circuit control signal Reset1 is also turned off. Next, when the in-cell touch display device 10 operates in the above-mentioned touch sensing period, the first compensation circuit control signal Reset1 is converted from a low voltage level to a high voltage level, and the n-1th stage gate drive signal G _n-1 is a logic low potential, the transistor M10 and the transistor M11 are therefore turned off, and the transistor M8 is kept on, and since the first compensation circuit control signal Reset1 is at a high voltage level at this time, the capacitor C3 is electrically coupled to the transistor Between the second terminal of M8 and the control terminal, the transistor M8 has better driving capability because the capacitor C3 compensates the high voltage level of the first compensation circuit control signal Reset1 to the control terminal of the transistor M8. The transistor M9 is turned on because the first compensation circuit control signal Reset1 is converted to a high voltage level, so at this time the first compensation circuit 1215 naturally generates a first current flowing from its first terminal to the second terminal to compensate the driving circuit control signal Q _n .

When the shift register 121 of the current stage outputs the gate driving signal Gn of the _nth stage, that is, when the in-cell touch display device 10 is operating again in the above-mentioned display period, the first compensation circuit control signal Reset1 is converted to a low voltage level, so the transistor M9 is turned off, and the transistor M11 is turned on because of the gate drive signal Gn of the _nth stage, and the control terminal of the transistor M8 is pulled down to a low voltage level, so the transistor M8 is turned off, and at this time due to the drive circuit control signal The voltage level of Q _n is higher than the low voltage level of the first compensation circuit control signal Reset1, so due to the unidealization of electronic components, the flow from the second terminal to the first terminal of the first compensation circuit 1215 will naturally occur. second current. Wherein, since the first clock signal CK is at a logic high potential, the gate drive signal Gn of the _nth stage is also at a logic high potential, and the first clock signal CK is at a logic low potential during the touch sensing period, so the transistor M11 can also be The transistor M8 is turned off according to the control of the first clock signal CK. In addition, by adding the transistor M12, the control terminal of the transistor M8 can be maintained at a low voltage level in the correct time period, so as to prevent the transistor M8 from being turned on at a wrong time, causing the driving circuit control signal _Qn to leak a lot through the transistor M15 .

The operation of the first compensation circuit 1215 will be described below by taking FIG. 6A , FIG. 6B and FIG. 8 as examples. First, take the enabling of the first scanning signal U2D as an example, that is, the pixel unit 131 of the display panel ₁₃ is driven from the L1 column to the _Ln column shown in FIG. When the device 10 is operating in the above-mentioned display period and the gate drive signal Gn _-1 of the n-1th level is logic high potential, the transistor M13 is turned on, so the transistor M15 is also turned on accordingly, and at this time due to the control of the first compensation circuit The signal Reset1 is at a low voltage level, so the transistor M16 is turned off, and no current flows from the first terminal to the second terminal of the first compensation circuit 1215 at this time.

Next, when the in-cell touch display device 10 operates in the above-mentioned touch sensing period, the first compensation circuit control signal Reset1 is at a high voltage level, and the n-1th stage gate driving signal Gn _-1 is logic low. Potential, so the transistor M13 is off, but the transistor M15 is still on at this time, so the first compensation circuit control signal Reset1 coupled to the first end of the transistor M15 can be transmitted to the first end of the transistor M16, and the transistor M15 is more due to the capacitance C4 compensates the high voltage level of the first compensation circuit control signal Reset1 to the control terminal of the transistor M15 to have a better driving capability. At this time, the transistor M16 is turned on because of the first compensation circuit control signal Reset1, and the first compensation circuit controls The high voltage level of the signal _Reset1 is higher than the voltage level of the driving circuit control signal Qn, so the first compensation circuit 1215 generates a first current flowing from the first terminal to the second terminal at this time.

When the shift register 121 of the current stage outputs the gate driving signal Gn of the _nth stage, that is, when the in-cell touch display device 10 is operating again in the above-mentioned display period, the first compensation circuit control signal Reset1 is converted to a low voltage level, so the transistor M16 is turned off. Since the voltage level of the drive circuit control signal Qn _is higher than the low voltage level of the first compensation circuit control signal Reset1 at this time, the second end of the first compensation circuit 1215 generates The second current flowing through the first terminal. And when the gate drive signal Gn ₊₁ of the n+1th stage is logic high voltage, the transistor M14 is turned on. At this time, because the second scan signal D2U is disabled, for example, it is logic low potential, so the control terminal of the transistor M15 is turned on. Reset to logic low level, transistor M15 is off. In other embodiments, the transistor M15 can be turned off through the transistor M17 and the transistor M18, so as to prevent the transistor M15 from continuing to be turned on at a wrong time, resulting in a large leakage of the driving circuit control signal Q _n through the transistor M15, as shown in FIG. 6B . In addition, when the first scanning signal U2D is disabled, the second scanning signal D2U is kept enabled, and the pixel unit 131 of the display panel 13 is driven from the L _n column to the L ₁ column shown in FIG. 1 , the transistor M15 is It is turned on by the n+1th stage gate driving signal Gn ₊₁ of the previous stage.

According to the above content, since the transistor M8 in FIG. 4A, FIG. 4B and FIG. 4C, the transistor M15 in FIG. 6A and FIG. The pole drive signal G _n-1 or the gate drive signal G _n+1 of the n+1th stage will be turned on, so when the shift register of this stage does not need to compensate the drive circuit control signal Q _n shift register, the transistor M8 or transistor M15 will not be turned on, so it will not be affected by the high voltage level of the first compensation circuit control signal Reset1, and through the circuit structure of Figure 4A, Figure 4B, Figure 4C, Figure 6A and Figure 6B, the first compensation circuit 1215 has a lower second current, effectively increasing the ratio of the first current to the second current, and preventing the output capability of the shift register 121 from being reduced due to excessive leakage current of the drive circuit control signal _Qn .

Please refer to FIG. 9. FIG. 9 is another embodiment of the shift register 121 of the present invention. The difference between FIG. 9 and FIG. The control signal Reset2 is electrically coupled, and its second end _is electrically coupled to the drive circuit control signal Qn. The first compensation circuit 1215 and the second compensation circuit 1216 can operate at different times, for example, a frame (Frame) For example, the first compensation circuit 1215 and the second compensation circuit 1216 operate alternately in different frames.

According to the above content, an embodiment of the operation method of a shift register circuit is further _compiled , please refer to FIG. The gate drive signal of the nth stage of the shift register 121 is disabled, the first compensation circuit control signal Reset1 is at the above-mentioned high voltage level, and the potential of the first terminal of the first compensation circuit 1215 is greater than that of the first compensation circuit 1215 The potential of the second terminal, the first compensation circuit 1215 generates a first current flowing from the first terminal to the second terminal to compensate the driving circuit control signal Q _n (step 101 ).

In other embodiments, the operation method of the shift register circuit further includes that during the above-mentioned display period, that is, during the period _TD in FIG. Reset1 is a low voltage level, the potential of the second terminal of the first compensation circuit 1215 is greater than the potential of the first terminal of the first compensation circuit 1215, and the first compensation circuit 1215 generates a second current flowing from the second terminal to the first terminal , wherein the second current may be smaller than the first current to reduce the leakage of the driving circuit control signal Q _n through the first compensation circuit 1215 during the display period (step 102 ), as shown in FIG. 11 .

To sum up, the shift register circuit embodiment proposed by the present invention has the above-mentioned compensation circuit, so the shift register circuit 121 of the nth stage can utilize the output generated by the first compensation circuit 1215 during the touch sensing period. current to compensate the driving circuit control signal Q _n , so when the touch sensing period ends, the driving circuit control signal Q _{n of the nth shift register circuit 121 is still the same as the driving circuit control signal Q n before} the touch sensing period, For example, the driving circuit control signal Qn _-1 of the _n -1th shift register circuit 121 has the same driving capability, so as to avoid horizontal stripes on the display screen due to the decrease of the driving capability of the driving circuit control signal Qn.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall prevail as defined by the paid claims.

Claims (13)

1. a shift-register circuit, is characterized in that, comprising:

One input circuit is in order to export one drive circuit control signal according to one (n-1)th grade of gate drive signal;

One first pull-down circuit, with this input circuit electric property coupling, is in order to this driving circuit control signal is pulled down to a low voltage level;

One pull-up circuit, with this input circuit electric property coupling, is in order to export one n-th grade of gate drive signal according to this driving circuit control signal;

One second pull-down circuit, with this pull-up circuit electric property coupling, is in order to this n-th grade of gate drive signal is pulled down to this low voltage level; And

One first compensating circuit, it has a first end and one second end, this first end of this first compensating circuit and one first compensating circuit control signal electric property coupling, this second end of this first compensating circuit and this input circuit and this pull-up circuit electric property coupling, in a touch-control sensing period, this the first compensating circuit control signal is a high-voltage level, n-th grade of gate drive signal is forbidden energy, when the current potential of this first end of this first compensating circuit is greater than the current potential of this second end of this first compensating circuit, this first compensating circuit produces one first electric current that flowed from this first end toward this second end to compensate this driving circuit control signal.

2. shift-register circuit as claimed in claim 1, wherein, this first compensating circuit also comprises one first diode and one second diode, this first diode and this second diode all comprise a positive terminal and a negative pole end, this positive terminal of this first diode and this first compensating circuit control signal electric property coupling, this negative pole end of this first diode and this negative pole end electric property coupling of this second diode, this positive terminal of this second diode body and this input circuit and this pull-up circuit electric property coupling.

3. shift-register circuit as claimed in claim 2, wherein, the size of this second diode is greater than this first diode.

4. shift-register circuit as claimed in claim 1, wherein, this first compensating circuit also comprises a first transistor and a transistor seconds, this the first transistor has a first end, one second end and a control end, this transistor seconds has a first end, one second end and a control end, this first end of this first transistor and this control end of this first transistor and this first compensating circuit control signal electric property coupling, this the second end of this first transistor and this second end electric property coupling of this transistor seconds, this first end of this transistor seconds and this control end of this transistor seconds, this input circuit and this pull-up circuit electric property coupling.

5. shift-register circuit as claimed in claim 1, wherein, this first compensating circuit also comprises:

One second input circuit;

One the first transistor, there is a first end, one second end and a control end, this first end of this first transistor and this second input circuit electric property coupling, this control end of this first transistor and a control signal electric property coupling, this second end of this first transistor and this low voltage level electric property coupling;

One transistor seconds, has a first end, one second end and a control end, and this first end of this transistor seconds receives this first compensating circuit control signal, this control end of this transistor seconds and this first end electric property coupling of this first transistor; And

One third transistor, there is a first end, one second end and a control end, this first end of this third transistor and this second end electric property coupling of this transistor seconds, this control end of this third transistor receives this first compensating circuit control signal, this second end of this third transistor and this second end electric property coupling of this first compensating circuit.

6. shift-register circuit as claimed in claim 5, wherein, this first compensating circuit also comprises:

One the 4th transistor, there is a first end, one second end and a control end, this first end of 4th transistor and this first end electric property coupling of this first transistor, this control end of 4th transistor receives a clock signal, this second end of the 4th transistor and this low voltage level electric property coupling.

7. shift-register circuit as claimed in claim 5, wherein, this second input circuit comprises:

One the 4th transistor, there is a first end, one second end and a control end, this first end of 4th transistor and a high-voltage level electric property coupling, this control end of 4th transistor receives one (n-1)th grade of gate drive signal, this second end of the 4th transistor and this first end electric property coupling of this first transistor.

8. shift-register circuit as claimed in claim 5, wherein, this second input circuit comprises:

One the 4th transistor, there is a first end, one second end and a control end, this first end of 4th transistor and this control end receive one (n-1)th grade of gate drive signal, this second end of the 4th transistor and this first end electric property coupling of this first transistor.

9. shift-register circuit as claimed in claim 5, wherein, this control signal is this n-th grade of gate drive signal or a clock signal.

10. shift-register circuit as claimed in claim 1, wherein, this first compensating circuit also comprises:

One the first transistor, has a first end, one second end and a control end, and this first end of this first transistor receives one first sweep signal, and this control end of this first transistor receives one (n-1)th grade of gate drive signal;

One transistor seconds, there is a first end, one second end and a control end, this first end of this transistor seconds receives one second sweep signal, this control end of this transistor seconds receives one (n+1)th grade of gate drive signal, this second end of this transistor seconds and this second end electric property coupling of this first transistor;

One third transistor, has a first end, one second end and a control end, and this first end of this third transistor receives this first compensating circuit control signal, this control end of this third transistor and this second end electric property coupling of this first transistor; And

One the 4th transistor, there is a first end, one second end and a control end, this first end of 4th transistor and this second end electric property coupling of this third transistor, this control end of 4th transistor receives this first compensating circuit control signal, this second end of the 4th transistor and this second end electric property coupling of this first compensating circuit.

11. shift-register circuits as claimed in claim 10, wherein, this first compensating circuit also comprises:

One the 5th transistor, there is a first end, one second end and a control end, this first end of 5th transistor and this second end electric property coupling of this transistor seconds, this control end of 5th transistor receives this n-th grade of gate drive signal, this second end of the 5th transistor be in order to this low voltage level electric property coupling; And

One the 6th transistor, there is a first end, one second end and a control end, this first end of 6th transistor and this second end electric property coupling of this transistor seconds, this control end of 6th transistor receives a clock signal, this second end of the 6th transistor and this low voltage level electric property coupling.

12. shift-register circuits as claimed in claim 1, wherein, this shift-register circuit also comprises one second compensating circuit, it has a first end and one second end, this first end of this second compensating circuit and one second compensating circuit control signal electric property coupling, this second end of this second compensating circuit and this input circuit and this pull-up circuit electric property coupling.

13. shift-register circuits as claimed in claim 1, wherein, in a display time interval, this first compensating circuit control signal is a low voltage level, and this n-th grade of gate drive signal is enabled in this display time interval.