KR102135928B1 - A shift register and method for manufacturing the same, and an image display device using the shift register - Google Patents

Abstract

According to the present invention, even if the driving control signals input from the outside are distorted or an error occurs, each stage of the shift register is stably driven to prevent display defects and improve reliability. Regarding an image display apparatus using a shift register, in a shift register in which a plurality of stages are connected to each other, each of the plurality of stages is a set node according to a scan pulse from a start pulse or a previous stage and a scan pulse from a rear stage. And a node control unit controlling charge/discharge states of each of the first and second reset nodes; And a scan pulse output unit controlled according to the voltage of each of the set node and the first and second reset nodes to output the current stage scan pulse, and the node control unit provided with at least one stage of the plurality of stages A first switching element that charges the set node by connecting a charging voltage source to the set node according to the scan pulse from the front stage, and is formed in an asymmetrically different size from the first switching element from the rear stage And a second switching element that discharges the set node by connecting a discharge voltage source to the set node according to the scan pulse of.

Description

Shift register and manufacturing method thereof, and image display device using shift register {A SHIFT REGISTER AND METHOD FOR MANUFACTURING THE SAME, AND AN IMAGE DISPLAY DEVICE USING THE SHIFT REGISTER}

According to the present invention, even if the driving control signals input from the outside are distorted or an error occurs, each stage of the shift register is stably driven to prevent display defects and improve reliability. It relates to a video display device using a shift register.

In order to sequentially drive the gate lines of the image display device, a shift register that sequentially supplies scan pulses to these gate lines is required. The shift register is composed of multiple stages that output scan pulses, and each stage sequentially outputs one scan pulse. The scan pulses are sequentially supplied to each gate line of the image display panel to sequentially scan the gate lines.

Each of the plurality of stages connected to each other is a node control unit that controls the charge/discharge state of an enable node and a disable node, a scan pulse or a scan pulse according to each charge/discharge state of the enable node and the disable node. It has a pull-up and pull-down switching element for outputting the discharge voltage, respectively.

The node control unit of each stage receives the driving control signal input from the outside, for example, at least one clock pulse sequentially supplied, and scan pulses from the previous and subsequent stages, and thus enables and disables the node. Are alternately charged and discharged. Accordingly, when the enable node is in the charged state, the scan pulse from the pull-up switching element is output to the corresponding gate line, and when the disable node is in the charged state, the discharge voltage from the pull-down switching element is output to the corresponding gate line.

In the conventional shift register, scan pulses can be sequentially output without any problem when the drive control signals from the outside are normally input. However, driving control signals supplied to the shift register also have to be supplied unstablely during a period in which the driving state, such as a start period when the system power is supplied (ON) and a driving frequency change, is unstable. When the driving control signals are supplied unstable, the operation of the shift register is also unstable, and the result is a poor image display.

More specifically, for example, when a graphic system that supplies driving control signals to a shift register or an external scaler supplies driving control signals from a point in time when power is supplied, all the resolutions of the first frame are not supplied. When the drive control signals of the next frame are supplied again, a drive error of the shift register occurs. In addition, when the driving control signals of the shift register are supplied by the graphics system or the external scaler, and when the driving control signals of the next frame are not supplied at the time of changing the frequency, the shift register driving error Will occur.

As described above, when the drive control signals for displaying the next frame are supplied in a state in which the operation of the shift register is not accurately completed every frame, the enable nodes and disable nodes of the stages that have been sequentially driven from the previous stages are provided. It cannot be charged or discharged normally. In this case, since the node for enabling of the lower stages including the dummy stage is not normally discharged, the scan pulse is output at the same timing as the upper stages. Accordingly, various image display defects such as the image on the top displayed on the image display panel are displayed identically on the bottom, thereby lowering the reliability of the product.

The present invention is to solve the above problems, even if the driving control signals from the outside are distorted or an error occurs, each stage of the shift register is stably driven to prevent display defects and improve reliability. An object of the present invention is to provide a shift register, a manufacturing method thereof, and an image display device using the shift register.

The shift register according to an embodiment of the present invention for achieving the above object is a shift register in which a plurality of stages are connected to each other, each of the plurality of stages from a start pulse or a scan pulse from a front stage and a rear stage. A node control unit controlling a charge/discharge state of each of the set node and the first and second reset nodes according to a scan pulse of; And a scan pulse output unit controlled according to the voltage of each of the set node and the first and second reset nodes to output the current stage scan pulse, and the node control unit provided with at least one stage of the plurality of stages A first switching element that charges the set node by connecting a charging voltage source to the set node according to the scan pulse from the front stage, and is formed in an asymmetrically different size from the first switching element from the rear stage And a second switching element that discharges the set node by connecting a discharge voltage source to the set node according to the scan pulse of.

In the second switching element of the node control unit provided in the at least one stage, at least one of a magnitude, a turn-on/off threshold voltage magnitude, and a turn-on/off current amount ratio is formed differently from the first switching element. It is characterized by.

The second switching element is smaller than at least one of a magnitude, a turn-on/off threshold voltage magnitude, and a turn-on/off current amount ratio than the first switching element, so that the set node is compared to the discharge current amount of the set node. It characterized in that the amount of charge current is maintained larger.

The second switching element is formed by making at least one of the width between the source-drain electrodes of the first switching element and the width of the source-drain electrodes smaller, so that the size of the second switching element, the turn-on/off threshold voltage, and It is characterized in that at least one of the turn-on/off current amount ratio is formed smaller than the first switching element.

At least one of the size of the second switching element, the turn-on/off threshold voltage size, and the turn-on/off current amount ratio of the last stage among the plurality of stages is formed smaller than the first switching element. do.

In addition, a method of manufacturing a shift register according to an embodiment of the present invention for achieving the above object is a method of manufacturing a shift register in which a plurality of stages are mutually connected to each other, the step of manufacturing each of the plurality of stages is Forming a node control unit to control charging/discharging states of the set node and the first and second reset nodes according to the start pulse or the scan pulse from the front stage and the scan pulse from the rear stage, and the set node and And forming a scan pulse output unit to be output according to a voltage of each of the first and second reset nodes to output a current stage scan pulse, wherein the step of forming a node control unit of at least one stage of the plurality of stages comprises the front end. Forming a first switching element to charge the set node by connecting a charging voltage source to the set node according to the scan pulse from the stage; and asymmetrically different from the first switching element to form a different size from the rear stage And a second switching element forming step of discharging the set node by connecting a discharge voltage source to the set node according to the scan pulse of.

In the second switching element of the node control unit provided in the at least one stage, at least one of a magnitude, a turn-on/off threshold voltage magnitude, and a turn-on/off current amount ratio is formed differently from the first switching element. Is done.

The second switching element is smaller than at least one of a magnitude, a turn-on/off threshold voltage magnitude, and a turn-on/off current amount ratio than the first switching element, so that the set node is compared to the discharge current amount of the set node. It characterized in that the amount of charge current is maintained larger.

The second switching element is formed by making at least one of the width between the source-drain electrodes of the first switching element and the width of the source-drain electrodes smaller, so that the size of the second switching element, the turn-on/off threshold voltage, and It is characterized in that at least one of the turn-on/off current amount ratio is formed smaller than the first switching element.

At least one of the size of the second switching element, the turn-on/off threshold voltage size, and the turn-on/off current amount ratio of the last stage among the plurality of stages is formed smaller than the first switching element. do.

In addition, the image display device according to an embodiment of the present invention for achieving the above object is provided with a plurality of pixel areas, an image display panel for displaying an image; A gate driver driving gate lines of the image display panel; A data driver driving data lines of the image display panel; And a timing controller for aligning the image data input from the outside to be suitable for driving the image display panel and supplying it to the data driver, and generating a gate and data control signal to control the gate and data driver. At least one of the data drivers is characterized by having a shift register having various technical features described above to generate and output a plurality of scan pulses that are sequentially shifted.

The shift register according to an embodiment of the present invention having various technical features as described above, a method for manufacturing the same, and an image display device using the shift register, each of the shift register even if the driving control signals input from the outside are distorted or an error occurs By stably driving the stages, it is possible to prevent display defects and improve reliability.

1 is a block diagram showing a shift register according to an embodiment of the present invention.
2 is a waveform diagram showing a signal supplied to the shift register of FIG. 1;
3 is a diagram showing a circuit configuration of one stage shown in FIG. 1;
4 is a circuit diagram specifically illustrating a structure in which the n-th stage and the dummy stage of FIG. 1 are connected to each other.
5 is a configuration diagram illustrating a liquid crystal display device to which a shift register according to an embodiment of the present invention is applied.

Hereinafter, a shift register according to an embodiment of the present invention having the above characteristics, a manufacturing method thereof, and an image display device using the shift register will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a shift register according to an embodiment of the present invention.

The shift register shown in FIG. 1 is composed of n stages ST1 to STn and one dummy stage STn+1 connected to each other.

Each of the stages (ST1 to STn, where n is any natural number greater than or equal to 2) outputs one scan pulse (Vout1 to Voutn+1) during one frame period, wherein the dummy stage STn from the first stage ST1 The scan pulses Vout1 to Voutn are sequentially output up to +1).

The scan pulses Vout1 to Voutn output from the above stages ST1 to STn except for the dummy stage STn+1 are sequentially supplied to gate lines of a display panel (not shown) displaying an image, Each gate line of the display panel is sequentially scanned. Specifically, when the first stage ST1 outputs the first scan pulse Vout1, the second stage ST2 outputs the second scan pulse Vout2, and then the third stage ST3 outputs the first scan pulse Vout1. 3 outputs the scan pulse Vout3, and finally, the nth stage STn outputs the nth scan pulse Voutn. Meanwhile, after the n-th stage STn outputs the n-th scan pulse Voutn, the dummy stage STn+1 outputs the n-th scan pulse Voutn+1, where the dummy stage STn+ The n+1 scan pulse Voutn+1 output from 1) is not supplied to the gate line, but is supplied only to the previous n-th stage STn.

As described above, each stage ST1 to STn drives a gate line connected to itself using the scan pulses Vout1 to Voutn+1, and ends from itself using the scan pulses Vout1 to Voutn+1. Controls the operation of the stage located at and the stage located at the front end from itself.

Specifically, the kth scan pulse Voutk from any one kth stage STk (where k is any natural number) is supplied to the kth gate line, and the kth scan pulse Voutk from the kth stage STk. ) Is supplied to the previous k-1 stage STk-1 and the subsequent k+1 stage STk+1. The k+1 stage STk+1 is set by the kth scan pulse Voutk, and the kth-1 stage STk-1 is reset by the kth scan pulse Voutk.

The kth scan pulse Voutk from the kth stage STk may be supplied to the kth gate line, and may also be supplied to the kth stage STk-2 and the k+2 stage STk+2. have. In this case, the kth+2 stage STk+2 is set by the kth scan pulse Voutk, and the kth-2 stage STk-2 is reset by the kth scan pulse Voutk. The shift register of the present invention may be embedded in the non-display portion of the display panel.

FIG. 2 is a waveform diagram showing a signal supplied to the shift register of FIG. 1.

Referring to FIG. 2, each stage (ST1 to STn+1) of the shift register is at least one charging voltage source (VDD, VDD_o, VDD_e) that is converted to the same or different levels according to a display period and a non-display period of an image ), the discharge voltage source VSS and at least one clock pulse among the plurality of clock pulses CLK1 to CLK4 circulating with sequential phase differences are respectively applied. Here, the number of clock pulses CLK1 to CLK4 supplied to each stage ST1 to STn+1 may be varied according to the circuit configuration of each stage ST1 to STn+1.

Among the stages ST1 to STn+1, the first stage ST1 includes first and second charging voltage sources VDD, VDD_o, discharge voltage sources VSS, and a plurality of clock pulses input at the same or different levels. The start pulse Vst is further supplied with at least one clock pulse among the CLK1 to CLK4). In addition, the odd-numbered stages ST3, ST5, ... STn+1 other than the first stage ST1 are the first and second charging voltage sources VDD, VDD_o, and the discharge voltage source except the start pulse Vst. (VSS), at least one clock pulse among the plurality of clock pulses CLK1 to CLK4 is supplied. On the other hand, the even-numbered stages ST2, ST4, ... STn exclude the start pulse Vst, the first and third charging voltage sources VDD, VDD_e, the discharge voltage source VSS, and the plurality of clock pulses CLK1 to At least one clock pulse among CLK4) is supplied.

As described above, the plurality of charging voltage sources VDD, VDD_o, and VDD_e are divided and supplied into a first charging voltage source VDD, a second charging voltage source VDD_o, and a third charging voltage source VDD_e, respectively. Each of the charging voltage sources VDD, VDD_o, and VDD_e is converted and supplied to the gate high voltage level vgh and the gate low voltage level in units of a display frame and a non-display period of the image. The gate high voltage level vgh can charge at least one set and reset node provided in each stage ST1 to STn+1, that is, a set and reset node of each stage ST1 to STn+1. It is set to turn on the switching elements connected to the. In addition, the gate low voltage level vgl is set so that at least one set and reset node provided in each stage ST1 to STn+1 can be discharged, that is, a set and reset of each stage ST1 to STn+1. It is configured to turn off switching elements connected to the set node.

Meanwhile, the first to fourth clock pulses CLK1 to CLK4 may be periodically generated to have the amplitudes of the gate low voltage level vgl1 and the gate high voltage level vgl. The first to fourth clock pulses CLK1 to CLK4 are generated to maintain an active state (high period) simultaneously for a predetermined period between clock pulses generated adjacent to each other, and are supplied to the shift register to be circulated with each other.

More specifically, in the case of the second clock pulse CLK2, a phase delay is generated by 1/2 to 2/3 pulse width from the first clock pulse CLK1, and the third clock pulse CLK3 is It is generated by phase delay by 1/2 to 2/3 pulse widths from the 2 clock pulses CLK2, and the fourth clock pulse CLK4 is phased by 1/2 to 2/3 pulse widths from the third clock pulse CLK3. It is delayed. Each of these clock pulses CLK1 to CLK4 has the same pulse width and duty rate. In addition, the first clock pulse CLK1 is output with a phase delay of 1/2 to 2/3 pulse width than the fourth clock pulse CLK4. Accordingly, clock pulses output in adjacent periods are kept high at the same time for a period of time. For example, the pulse width (the pulse width in the high state) of the first clock pulse CLK1 and the pulse width (the pulse width in the high state) of the second clock pulse CLK2 are the same, and the first clock pulse CLK1 The second half portion overlaps the first half portion of the second clock pulse CLK2. At this time, the overlapping period between the pulse width of the first clock pulse CLK1 and the pulse width of the second clock pulse CLK2 corresponds to about 1/3 to 1/2 pulse width period.

Next, the configuration of each stage ST1 to STn+1 provided in the shift register of the present invention receiving the signals as described above will be described.

FIG. 3 is a diagram showing a circuit configuration of one stage shown in FIG. 1.

In one stage shown in FIG. 3, for example, the k-th stage is a set node according to the start pulse Vst or the scan pulse Voutk-2 from the previous stage and the scan pulse Voutk+2 from the rear stage. A node control unit NC that controls the voltage states of the Q and the first and second reset nodes QB1 and QB2, respectively; And a scan pulse output unit CO that is controlled according to voltages of the set node Q and the first and second reset nodes QB1 and QB2 and outputs a scan pulse Voutk.

The node control unit NC includes first to tenth switching elements.

The first switching element Tr1 is turned on or off according to the scan pulse Voutk-2 from the k-2 stage STk-2 that is the front end, and when turned on, the first charging voltage source VDD It is connected between the supply line and the set node (Q). Upon turn-on of the first switching element Tr1, the set node Q is charged to the gate high level of the first charging voltage source VDD. Here, a scan pulse Voutk-2 from the k-2 stage may be supplied to the drain terminal (or source terminal) of the first switching element Tr1 instead of the first charging voltage source VDD.

The second switching element Tr2 is turned on or off according to the scan pulse Voutk+2 from the rear stage k+2 stage STk+2, and the supply of the discharge voltage source VSS at turn-on The line is connected between the set node Q. Upon turn-on of the second switching element Tr2, the set node Q is discharged to the gate low level of the discharge voltage source VSS.

The size of each of the first and second switching elements Tr1 and Tr2 charging or discharging the set node Q in the node control unit NC of each stage ST1 to STn, the turn-on/off threshold voltage magnitude, and The turn-on/off amperage ratios may be formed symmetrically to each other. However, the first and second switching elements Tr1 and Tr2 of the node control unit provided in at least one of the stages ST1 to STn have a size, a turn-on/off threshold voltage level, and a turn-on At least one of the on/off current amount ratios may be formed asymmetrically different from each other. In other words, the second switching element Tr2 of the node control unit provided in at least one of the stages ST1 to STn has at least one of a magnitude, a turn-on/off threshold voltage magnitude, and a turn-on/off current amount ratio. One may be formed asymmetrically different from the first switching element Tr1.

The third switching element Tr3 is turned on or off according to the voltage of the first reset node QB1, and when turned on, connects the set node Q and the supply line of the discharge voltage source VSS. .

The fourth switching element Tr4 is turned on or off according to the voltage of the second reset node QB2, and when turned on, connects between the set node Q and the supply line of the discharge voltage source VSS. .

The fifth switching element Tr5 is turned on or off according to the voltage level from the line to which the second charging voltage source VDD_o is supplied, and when turned on, the supply line of the second charging voltage source VDD_o and the first Common nodes CN1 are connected.

The sixth switching element Tr6 is turned on or off according to the voltage of the first common node CN1, and when turned on, between the second charging voltage source VDD_o supply line and the first reset node QB1 Connect.

The seventh switching element Tr7 is turned on or off according to the voltage of the set node Q, and when turned on, connects the first common node CN1 and the discharge voltage source VSS supply line.

The eighth switching element Tr8 is turned on or off according to the scan pulse of the front or rear stage or the clock pulse supplied to the low or rear stage, and when turned on, the first common node CN1 and the discharge voltage source ( VSS) Connect between supply lines.

The ninth switching element Tr9 is turned on or off according to the voltage of the set node Q, and when turned on, connects the first reset node QB1 and the discharge voltage source VSS supply line.

The tenth switching element Tr10 is turned on or off according to the voltage of the set node Q, and when turned on, connects the second reset node QB2 and the discharge voltage source VSS supply line.

The scan pulse output unit CO provided in the k-th stage STk includes a pull-up switching element Uc, a first pull-down switching element Dc1, and a second pull-down switching element Dc2.

The pull-up switching element Uc is turned on or off according to the voltage of the set node Q, and when turned on, a clock supplied to the clock transmission line by connecting one of the clock transmission lines and the scan pulse output terminal The pulse CLKk is output as a scan pulse Voutk.

The first pull-down switching element Dc1 is turned on or off according to the voltage of the first reset node QB1, and when turned on, the scan pulse output terminal is electrically connected to the discharge voltage source VSS.

The second pull-down switching element Dc2 is turned on or off according to the voltage of the second reset node QB2, and when turned on, the scan pulse output terminal is electrically connected to the discharge voltage source VSS.

As described above, first to fourth clock pulses CLK1 to CLK4 are periodically supplied to the image display period Frame for each stage ST1 to STn+1 configured and operated as well as the gate high voltage level. The first charging voltage source VDD and the second charging voltage source VDD_o are supplied to maintain (vgh). In addition, the third charging voltage source VDD_e may be supplied at the same or different level as the second charging voltage source VDD_o. On the other hand, during the non-display period of the image, the first to fourth clock pulses CLK1 to CLK4 and the first to third charging voltage sources VDD, VDD_e, VDD_o are supplied to maintain the gate low voltage level vgl. do. Accordingly, in the non-image display period, a threshold of a plurality of switching elements connected to the set node Q and the second reset node QB2, that is, the pull-up switching element Uc and the second pull-down switching element Dc2, etc. As the voltage is lowered, it can be operated more stably during the image display period.

Each stage (ST1 to STn+1) configured and operated as described above is sequentially scanned without any problem if the start pulse (Vst) and the first to fourth clock pulses (CLK1 to CLK4) are normally input. The pulses Vout1 to Voutn could be output. However, the start pulse (Vst) and the first to fourth clock pulses (CLK1 to CLK4) supplied to the shift register during a period in which the driving state is unstable such as a start period during which the system power is supplied (ON) and a period during which the driving frequency is changed Also, it had to be supplied unstable. For example, the first to fourth clock pulses CLK1 to CLK4 are sequentially supplied, and then the start pulse Vst and the first to fourth clock pulses of the next frame in a state in which all the resolutions of the current frame are not supplied ( When the CLK1 to CLK4) are supplied again, there is a case in which the set node Q of at least one stage is not charged and maintains only the discharge state. Even if the operation is performed for a predetermined frame period, the n-th stage STn of the last stage is continuously supplied with a dummy scan pulse from the dummy stage so that the set node Q maintains only the discharge state. Then, some stages of the previous stage including the n-1 stage STn-1 are not reset, and the set node Q is not reset, and the upper image is simultaneously displayed.

However, as in the present invention, the size of the second switching element Tr2 compared to the first switching element Tr1 of the node control unit provided in at least one of the stages ST1 to STn, the turn-on/off threshold When at least one of the voltage magnitude and the turn-on/off current amount ratio is formed asymmetrically with each other, it is possible to prevent a defective operation in which the set node Q is not charged and maintains only the discharge state. In this case, by forming at least one of the width between the source-drain electrodes and the width of the source-drain electrodes of the second switching element Tr2 compared to the first switching element Tr1, the second switching compared to the first switching element Tr1 At least one of the size of the device Tr2, the turn-on/off threshold voltage size, and the turn-on/off current amount ratio may be formed smaller.

The size of the second switching element Tr2 discharging the set node Q compared to the first switching element Tr1 charging the set node Q of the node controller NC, the turn-on/off threshold voltage magnitude, and If at least one of the turn-on/off current amount ratio is formed smaller, the set node Q input through the first switching element Tr1 compared to the discharge current amount of the set node Q through the second switching element Tr2 Since the charge current amount of is larger, the set node Q is not charged and it is possible to prevent a defective operation in which only the discharge state is maintained.

The size of the second switching element Tr2 compared to the first switching element Tr1 of the n-stage STn of the last stage having a high probability of bad operation among the plurality of stages, the turn-on/off threshold voltage magnitude, and the turn- If at least one of the on/off current amount ratio is formed smaller, a defective operation in which the set node Q of the last n-th stage STn is not charged and maintains only the discharge state can be prevented. Accordingly, the set node Q of the stages of the previous stage is also normally set or reset to prevent a bad operation. If the second switching element Tr2 is designed and formed smaller than the first switching element Tr1, the discharge characteristics of the set node Q may be deteriorated, but in the case of the n-th stage STn, the dummy stage STn+1 ) Since the scan pulse (Voutn+1) that is not affected by the RC time constant (resistance) of the image display panel is continuously supplied, it is possible to keep the discharge characteristics from deteriorating.

4 is a circuit diagram specifically illustrating a structure in which the n-th stage and the dummy stage of FIG. 1 are connected to each other.

Clock pulses having different phase differences are supplied to two adjacent stages STk and STk+1. For example, the n-th stage STn is supplied with an n-th clock pulse, and the dummy stage is supplied with an n+1 clock pulse.

The node control unit NC provided in the n-th stage STn includes first to tenth switching elements Tr1 to Tr10 as illustrated in FIGS. 3 and 4.

The first switching element Tr1 is turned on or off according to the scan pulse Voutn-2 from the n-2 stage STn-2, which is the front end, and when turned on, the first charging voltage source VDD Connect between supply line and set node (Q). Upon turn-on of the first switching element Tr1, the set node Q is charged to the gate high level of the first charging voltage source VDD.

The second switching element Tr2 is turned on or off according to the scan pulse Voutn+1 from the dummy stage STn+1, which is the rear stage, and when it is turned on, the supply line and set of the discharge voltage source VSS are set. Connects between nodes Q. Upon turn-on of the second switching element Tr2, the set node Q is discharged to the gate low level of the discharge voltage source VSS.

The n-th stage STn, which is maintained even when the possibility of a bad operation is large during a period in which the driving state is unstable, is the size of the second switching element Tr2 compared to the first switching element Tr1, the turn-on/off threshold voltage magnitude, and It is desirable to form at least one of the turn-on/off amperage ratios smaller. When the size of the second switching element Tr2 is smaller than that of the first switching element Tr1 in the n-th stage STn, the set node Q of the n-th stage STn is not charged and maintains only the discharge state. Bad operation can be prevented. Accordingly, the set node Q of the stages of the previous stage may also be normally set or reset to prevent a bad operation. In the case of the n-th stage STn, since the scan pulse Voutn+1, which is not affected by the RC time constant (resistance) of the image display panel from the dummy stage STn+1, is continuously supplied, the discharge characteristics are not deteriorated. I can do it. In this case, by forming at least one of the width between the source-drain electrodes and the width of the source-drain electrodes of the second switching element Tr2 compared to the first switching element Tr1, the first switching element Tr1 is compared to the first switching element Tr1. 2 At least one of the size of the switching element Tr2, the turn-on/off threshold voltage size, and the turn-on/off current amount ratio may be formed smaller.

The rest of the third to tenth switching elements Tr3 to Tr10 and the configuration of the scan pulse output unit CO are the same as those of FIG. 3, so the description of FIG. 3 will be replaced. However, as illustrated in FIG. 4, the first reset node QB1 of the current stage and the second reset node QB2 of the next stage are electrically connected to each other, and the second reset of the current stage is performed. The node QB2 and the first reset node QB1 of the next stage are also electrically connected to each other. This allows the first and second reset nodes QB1 and QB2 to be alternately driven in units of predetermined periods, thereby being driven according to the voltage state of the first and second reset nodes QB1 and QB2. This is to prevent deterioration of the third and fourth switching elements Tr3 and Tr4 and the first and second pull-down switching elements Dc1 and Dc2.

The above-described shift register of the present invention can stably drive each stage of the shift register even if the driving control signals inputted from the outside are distorted or an error, thereby preventing display defects and improving reliability. The shift register of the present invention can be applied to various video display devices. For example, a liquid crystal display device, a plasma display panel device, a field emission display device (FED), an organic light emitting diode display device It is applicable to a gate driving circuit driving a video display panel, a data driving circuit, or the like.

5 is a configuration diagram illustrating an example of a liquid crystal display device to which a shift register is applied according to an embodiment of the present invention.

The liquid crystal display device illustrated in FIG. 5 includes a liquid crystal panel 2 having a plurality of pixel areas to display an image; A gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2; A data driver 4 driving the data lines DL1 to DLm of the liquid crystal panel 2; And supplying the image data RGB input from the outside to the data driver 4 by properly aligning the driving of the liquid crystal panel 2 and generating gate and data control signals DCS, GCS. A timing controller 8 for controlling the drivers 6 and 4 is provided.

The shift register described in detail with reference to FIGS. 1 to 4 may be applied to a gate driver 6 or a data driver 4 that needs to generate a plurality of scan pulses Vout1 to Voutn sequentially shifted. For example, a shift register may be applied to the gate driver 6 driving the gate lines GL1 to GLn of the liquid crystal panel 2, and the shift register applied to the gate driver 6 includes a plurality of scan pulses Vout1. To Voutn) sequentially. Then, the gate lines GL1 to GLn can be sequentially driven by supplying them to the gate lines GL1 to GLn of the liquid crystal panel 2. The detailed description of the shift register will be replaced with the description provided through FIGS. 1 to 4 above.

The liquid crystal panel 2 is a thin film transistor (TFT) formed in each sub-pixel (R, G, B) region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. ), and a liquid crystal capacitor (Clc) connected to the TFT. The liquid crystal capacitor Clc is composed of a pixel electrode connected to a TFT and a common electrode facing the pixel electrode and the liquid crystal. The TFT supplies an image signal from each of the data lines DL1 to DLm to the pixel electrode in response to the scan pulses from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc implements gradation by charging the difference voltage between the image signal supplied to the pixel electrode and the reference common voltage supplied to the common electrode, and adjusting the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage. . In addition, the storage capacitor Cst is connected to the liquid crystal capacitor Clc in parallel so that the image signal charged in the liquid crystal capacitor Clc is maintained until the next image signal is supplied.

The data driver 4 uses the source start pulse and the source shift clock among the data control signals DCS from the timing controller 8 to convert the image data RGB aligned from the timing controller 8 to an analog voltage, that is, data. Convert to voltage. Specifically, the data driver 4 latches the image data RGB input according to the source shift clock among the data control signals DCS in units of horizontal lines, and then, at least one horizontal period in response to the source output enable signal. Data voltage for one horizontal line is supplied to each data line DL1 to DLm.

The gate driver 6 responds to the gate control signal GCS from the timing controller 8, for example, the start pulse Vst and the plurality of clock pulses CLK1 to CLK4, and the plurality of scan pulses Vout1 to Voutn. Is sequentially generated, and sequentially supplied to the gate lines GL1 to GLn. Specifically, the gate driver 6 shifts the start pulses Vst from the timing controller 8 according to a plurality of clock pulses CLK1 to CLK4 that circulate with a sequential phase difference from each other, thereby sequentially sequentially scanning a plurality of scan pulses ( Vout1 to Voutn). Also, the gate lines GL1 to GLn may be driven by sequentially supplying a plurality of scan pulses Vout1 to Voutn to the gate lines GL1 to GLn. Meanwhile, the gate-off voltage is supplied during a period in which the gate-on voltage is not supplied to the gate lines GL1 to GLn.

The timing controller 8 supplies image data RGB from the outside to the data driver 4 by properly aligning the size and resolution of the liquid crystal panel 2. In addition, the timing controller 8 generates a gate control signal GCS and a data control signal DCS using synchronization signals DCLK, DE, Hsync, and Vsync from the outside. Then, the gate and data drivers 6 and 4 are controlled by supplying the gate control signal GCS and the data control signal DCS to the gate driver 6 and the data driver 4, respectively.

As described above, the shift register according to an embodiment of the present invention can be applied to various image display devices such as a liquid crystal display, and according to the shift register according to the present invention, the input driving control signals are distorted or Even if an error occurs, by stably driving each stage of the shift register, it is possible to prevent display defects and improve reliability.

Through the above description, those skilled in the art will appreciate that various changes and modifications are possible without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the scope of the claims.

Claims (11)

In a shift register in which a plurality of stages are connected to each other dependently,
Each of the plurality of stages may include a node control unit that controls charge/discharge states of the set node and the first and second reset nodes according to a start pulse or a scan pulse from a front stage and a scan pulse from a rear stage; And
And a scan pulse output unit controlled according to the voltage of each of the set node and the first and second reset nodes to output the current stage scan pulse,
The node control unit provided with at least one stage of the plurality of stages
A first switching element that charges the set node by connecting a charging voltage source to the set node according to the scan pulse from the front end stage, and
And a second switching element that discharges the set node by connecting a discharge voltage source to the set node according to the scan pulse from the rear stage.
In the second switching element, at least one of a size of the first switching element, a turn-on/off threshold voltage size, and a turn-on/off current amount ratio is formed smaller, so that the set compared to the discharge current amount of the set node A shift resistor that allows the node to maintain a larger charge current. delete delete According to claim 1,
The second switching element
A shift resistor in which at least one of a width between a source-drain electrode and a width of a source-drain electrode of the first switching element is formed smaller. The method of claim 4,
A shift resistor in which at least one of the size of the second switching element, the turn-on/off threshold voltage size, and the turn-on/off current amount ratio of the last stage of the plurality of stages is formed smaller than the first switching element . delete delete delete delete delete An image display panel having a plurality of pixel areas to display an image;
A gate driver driving gate lines of the image display panel;
A data driver driving data lines of the image display panel; And
A timing controller is provided to align the image data input from the outside to the driving of the image display panel and supply it to the data driver, and to generate gate and data control signals to control the gate and data driver.
The gate driver
An image display device comprising a shift register having the technical characteristics of at least one of claims 1 and 4 to 5 to generate and output a plurality of scan pulses sequentially shifted.

Images