CN1052094C - serially accessed memory device - Google Patents

Abstract

The serial access memory device provided by the present invention has a first data terminal and a memory cell array, and the memory cell array has a plurality of addresses. The serial access memory device includes a shift register and an address decoding circuit. In response to an address clock pulse signal, the shift register stores the first address value of a memory serial access operation. The address decoding circuit, in response to an access control signal, the first address value, the address clock pulse signal and a clock pulse signal, accesses the values in the plurality of addresses in a serial manner.

Description

serially accessed memory device

The invention relates to a memory device, especially a serial access integrated circuit memory device.

In order to meet the demands of recent multimedia computer systems, integrated circuit storage devices have recently been used to store large amounts of data, such as audio or video data. Voice or video data has the characteristic of data continuity. In other words, this type of data is accessed sequentially or serially in most cases.

There are two ways to deal with digital voice storage in traditional related technologies. The first way uses a chip to integrate the voice controller and voice memory into an integrated circuit. This design lacks system compatibility. For example, the minimum memory capacity required for a 12-inch voice recording and playback system is not the same as that required for a 6-inch system. In this case, although the controller part in the chip can still meet the needs of users, the entire chip must be replaced due to insufficient capacity of the memory itself.

The second method adopts a solution of two chips, as shown in FIG. 1 . The first chip 13 is in charge of the voice control function, while the second chip 11 is in charge of the voice storage function. This method is obviously more compatible than the first method. But this approach still has many disadvantages. The first disadvantage is that too many output/input pins are required. Taking 256K static memory (SRAM) as an example, the required interface pins include at least A0~A14 address lines, D0~D7 data lines, memory read (RD) and write (WR) control lines, chip select (CS) line, Vdd and Vss lines. A second disadvantage is the possibility of memory expansion. When expanding from 256K to 1M, the chip 11 needs to add two address lines A15 and A16. A third disadvantage is the I/O pin requirement of the first chip 13 . When the memory chip 11 is accessed, the controller 13 must know when the end point of the memory is reached, so the controller 13 needs at least one selection signal line M1, M2. According to the input value of M1, M2, the controller 13 knows The capacity of the memory 11 used.

In order to overcome the above-mentioned disadvantages of the prior art, it is a first object of the present invention to provide a serial access memory which requires fewer I/O pins than the prior art.

The second object of the present invention is to provide a serial access memory, which only needs one data line, one address clock pulse line, one clock pulse line and one access control line to perform serial access .

A third object of the present invention is to provide a serial access memory whose number of I/O pins is independent of its memory capacity.

The fourth object of the present invention is to provide a serial access memory. When performing serial access to this memory, only the first address value of the memory access needs to be obtained by the controller.

To achieve the purpose of the present invention, the serial access memory device among the present invention has a first data terminal and a memory cell array, the memory cell array has a plurality of addresses, and the memory device includes:

A shift register, which responds to an address clock pulse signal, stores the first address value of a serial access operation of the memory device, and the shift register has a first input terminal connected to the first data terminal ;

An address decoding circuit, which responds to an access control signal, the first address value, the address clock signal and a clock signal, and performs serial access operations on a plurality of addresses in the storage cell array .

Graphical summary description:

FIG. 1 is a schematic diagram of a voice recording and playback system in the prior art.

Fig. 2 is a schematic diagram of a voice recording and playback system in the present invention.

Fig. 3 is a shift sequence diagram of the first address value during memory access in the present invention.

Fig. 4 is a detailed functional block diagram of the serial access memory in the present invention.

FIG. 5 is a timing diagram of related signals for memory writing in the present invention.

FIG. 6 is a detailed electrical diagram of the edge detector in FIG. 4. FIG.

FIG. 7 is a circuit diagram for generating a write signal and a read signal.

FIG. 8 is a detailed functional block diagram of the second embodiment of the present invention.

FIG. 9 is a detailed circuit diagram of the “0” setting circuit in FIG. 8 .

FIG. 10 is a timing diagram of the signals in FIG. 9 .

Fig. 11 is another circuit diagram having both the function of setting "0" and the function of edge detection.

As shown in FIG. 2 , the serial access storage device 21 of the present invention is connected with a voice recording and playback controller 23 . The interface therebetween comprises a clock pulse line (CLK) 230, an address clock pulse (ADD CLK) 210, a bidirectional data line (DATA) 220, a memory read/write (WR/RD) line 240, a chip select ( CS) line 250 and end of memory (EOM) line 260. Memory read/write lines 240 are used for memory access control.

The memory device 21 has a plurality of addresses, and the values therein can be accessed serially via the data line 220 . The data input terminal (DATA) of the memory device 21 inputs the first address value of a serial access operation of the memory device in a first period in a serial manner, and makes an address value in a serial manner in a remaining period of time. Data shift. The time sequence of shifting the first address value on the data line 220 during memory access is shown in FIG. 3 .

As shown in FIG. 4 , the memory device 21 has a shift register 42 which responds to an address clock pulse signal 210 to store the first address value of a serial access operation of the memory device. The shift register has a first input end connected with a first data end (DATA). Memory device 21 has an address decoding circuit 44, which responds to read (READ) signal 242, write (WRITE) signal 241, first address value signal 421 and address clock pulse signal 210, to memory cell array 46 Several addresses in the serial access operation. Both the read signal 242 and the write signal 241 are related to the clock pulse signal 230 and the memory read/write control signal 240 , and the detailed relationship will be described in detail later, as shown in FIG. 7 .

The shift register 42 has N data registers 420 which are connected in series to form the shift register 42 . Each of the N data registers has a data output terminal (Q), a clock pulse input terminal (CLK) and a data input terminal (D), and the data input terminal of the first data register is the first data input terminal of the shift register 42 An input terminal is connected with the data input terminal (DATA). The address clock pulse signal 210 is input to the clock pulse terminal of each data register 420 .

Address decoding circuit 44 has an address latch/counter 442, and it has N input ends, and each input end is connected with the data output end (Q) of a corresponding data register 420, so that respond to a loading (Load) signal 448, The first address value is latched, and the access address value is increased step by step in response to an increment signal 446 . The address decoding circuit 44 has an EOM terminal, and when the last address of the memory cell array 46 is accessed, it outputs a memory end (End of Memory) signal 260.

The address decoding circuit 44 further includes an edge detector 444 responsive to the access control signal 240 , the clock signal 230 and the address clock signal 210 to generate a load signal 448 and an increment signal 446 .

The serial access memory device 21 has a data buffer 48 which is connected with the data input terminal (DATA) and the memory cell array 46 respectively, and responds to the access control signal 240 and the clock pulse signal 230, and is used in a serial manner. The data is shifted.

The present invention shows the signal sequence when writing the memory into Figure 5, from which it can be seen that when the value in the last memory address is accessed, the memory end (End of Memory) signal 260 is activated (asserted). In the signal of FIG. 5, when the access control signal 240 becomes high level under the action of the controller 23, it is a memory write operation, and when the access signal 240 becomes low level under the action of the controller 23, the memory read action.

In FIG. 6, an embodiment of the edge detector 444 is shown. It has a NAND gate 60 , a first NOR gate 62 , a second NOR gate 64 , a NOT gate 66 , a delay circuit 67 and an AND gate 68 . The NAND gate 60 has two input terminals for inputting a read signal 242 and a write signal 241 , and has an output terminal for generating an incremental signal 446 . The first NOR gate 62 has a first input terminal, a second input terminal and a first output terminal. The first input terminal inputs an incremental signal 446 . The second NOR gate 64 has a third input terminal, a fourth input terminal and a second output terminal. The third input terminal inputs the address clock pulse signal 210, the fourth input terminal is connected with the first output terminal of the first NOR gate 62, and the second output terminal is connected with the second input terminal of the first NOR gate 62 and generates a The second output signal 641 . The NOT gate 66 has a fifth input terminal and a third output terminal, the fifth input terminal is connected to the second output terminal of the second NOR gate 64 , and the third output terminal generates a third output signal 661 . The AND gate 68 generates a load signal 448 in response to the second output signal 641 and the third output signal 661 .

It can be seen from FIG. 7 that the write signal 241 is generated by the NAND operation of the clock signal 230 and the memory access control signal 240 . The read signal 242 is generated by the NAND operation of the clock pulse signal 230 and the memory access control signal 240 .

As can be seen from the description of the first embodiment of the above-mentioned invention, this case has the following advantages:

First, one data (DATA) line 220 and one address clock pulse line 210 are sufficient for serial access to the memory cell array 46, and the speed is not too slow.

Second, all the interface signal lines between the controller 23 and the storage device 21 do not need to be changed, regardless of the capacity of the storage device 21, such as 256K or 1M or the like.

Thirdly, the address latch/counter 442 in the storage device 21 outputs a signal 260 to the controller 23 when all data is stored in the memory. Therefore, there is no need for selection signals M1, M2 to inform the capacity of the memory used.

Fourth, storage devices 21 of different forms or capacities can cooperate with the same controller 23 without any modification to the storage device 21 itself or the controller 23 .

The inability of the memory device 21 of the first embodiment of the present invention to handle variable word length addresses is its only disadvantage.

Because once the memory device 21 is manufactured, the number of data registers 420 therein is fixed. For example, for a 1M static access memory (SRAM), there are 20 data registers 420 . The address clock signal 210 must have 20 clock pulses to access the memory cell array 46 correctly. If the controller 23 sends more than 20 clock pulses on the address clock pulse line 210, then the shift register 420 can only hold the last 20 values. Therefore, its access action is limited by the capacity of the memory 21 itself. On the contrary, if the controller 23 sends less than 20 clock pulses, the first address value to be accessed will generate an error due to the influence of the remaining values of some higher bits in the shift register 42 . Therefore, in order to overcome this small shortcoming, the present invention further provides a second embodiment as shown in FIG. 8 .

The second embodiment, as shown in FIG. 8 , has the same shift register 42 , address latch/counter 442 , memory cell array 46 , edge detector 444 , and data buffer 48 as the first embodiment. The functions and operation modes of these components are the same as those described in the first embodiment, and reference may be made to the relevant descriptions in the first embodiment, and details are not repeated here.

The "0" setting circuit 450 in FIG. 8 responds to the address clock pulse signal 210, the read signal 242 or the write signal 241, and generates a "0" setting signal 452 to set the shift register 42 to "0". A preferred embodiment of a set "0" circuit 450 is shown in FIG.

As shown in Figure 9, setting "0" circuit 450 has a NAND gate 90, a first NOR gate 92, a second NOR gate 94, a NOT gate 96, a delay circuit 97 and a NOR gate 98 . The NAND gate 90 has two input terminals respectively input a read signal 242 and a write signal 241 , and has an output terminal. The first NOR gate 92 has a first input terminal, a second input terminal and a first output terminal. The first input terminal is connected with the output terminal of the NOT gate 90 . The second NOR gate 94 has a third input terminal, a fourth input terminal and a second output terminal. The third input terminal inputs the address clock pulse signal 210, and the fourth input terminal is connected with the first output terminal of the first NOR gate 92, and the second output terminal is connected with the second input terminal of the first NOR gate 92 and generates a Second output signal 941 . The NOT gate 96 has a fifth input terminal and a third output terminal, the fifth input terminal is connected with the second output terminal of the second NOR gate 94 , and the third output terminal generates a third output signal 961 . The NOR gate 98 generates a “0” signal 452 in response to the second output signal 941 and the third output signal 961 .

The timing relationship of the signals in FIG. 9 is shown in FIG. 10 . Similarly, the write signal 241 and the read signal 242 are generated by the circuit in FIG. 7 .

Because the first address clock pulse signal 210 after the last read signal 242 or write signal 241 was deasserted (deasserted), an action is set to a "0" signal 452, and the shift register 42 is then set to "0", so that the correct ground stores the first address value that is clocked in by the data line 220 next. If the number of address values is less than the number of data registers 420, no error will occur.

Claims (10)

1, a kind of memory device of serial access has one first data terminal and a memory cell array, and this memory cell array has most addresses; With a shift register, its response is stored first address value of a memory device one serial access action from an address clock pulse signal of control device, and this shift LD utensil one first input end and described first data terminal link, it is characterized in that, also comprise:

One address decoding circuitry, its response is carried out the serial access action from an access control signal of control device, described first address value, described address clock pulse signal and a clock pulse signal from control device to most addresses in the described memory cell array.

2, memory device as claimed in claim 1 wherein also comprises:

One data input pin was imported first address value of memory device one serial access action with serial mode in one first period, and transmitted data in a residue period in a tandem mode;

One data buffer, it links with data input pin and memory cell array respectively, and responds a described access control signal and a described clock pulse signal, transmits described data with serial mode.

3, a kind of serial access memory device with variable address word length ability has one first data terminal and a memory cell array, and this memory cell array has most addresses;

With a shift register, it responds an address clock pulse signal from control device, and first address value of a memory device one serial access action is stored, and this shift LD utensil one first input end and described first data terminal link, it is characterized in that, also comprise:

One address decoding circuitry, its response one access control signal from control device, described first address value, described address clock pulse signal and a time clock signal carry out the serial access action to most addresses in the described memory cell array; And

One reset circuit, it responds described access control signal, described clock pulse signal and described address clock pulse signal, produces a reset signal so that described shift register reset.

4, memory device as claimed in claim 2 further comprises:

One shift register, it responds a described address clock pulse signal, and first address value of memory device one serial access action is stored, and this shift LD utensil one first input end and described first data terminal link;

One address decoding circuitry, it responds a described access control signal, described first address value, described address clock pulse signal and a described clock pulse signal, and the serial access action is carried out in most addresses in the described memory cell array.

5, as claim 1 or 3 or 4 described memory devices, wherein this shift register has the mutual serial connection of N data register to constitute described shift register, each data register in N data register has an output terminal (Q), a time clock input end (CLK) and a data input pin (D), the data input pin (D) of first data register in N data register is the first input end of shift register, and the clock pulse input terminal of each data register is imported described address clock pulse signal.

6, memory device as claimed in claim 5, wherein this address decoding circuitry comprises one address latch/counter, it has N input end, each input end links with the data input pin (Q) of a corresponding data register, its response one signal of packing into latchs described first address value, and its response one increment signal is with the increase one by one of access address value.

7, memory device as claimed in claim 1, wherein this address decoding circuitry has EOM end, and its value in a FA final address of this memory cell array is exported a memory terminal point (End of Memory) signal during by access.

8, memory device as claimed in claim 6, wherein this address decoding circuitry further comprises:

One edge detecting device, its input end are imported described access control signal, described address clock pulse signal and described clock pulse signal respectively, export described signal and the increment signal of packing into.

9, memory device as claimed in claim 8, wherein edge detector comprises:

One Sheffer stroke gate, its tool two input ends are imported one respectively and are read (read) signal and and write (write) signal, and tool one output terminal is exported described increment signal;

One first rejection gate, its tool one first input end, one second input end and one first output terminal, first input end is imported described increment signal;

One second rejection gate, its tool 1 the 3rd input end, a four-input terminal and one second output terminal, the 3rd input end is imported described address clock pulse signal, first output terminal of the four-input terminal and first rejection gate links, and second input end binding of second output terminal and first rejection gate is also exported one second output signal;

One not gate, its tool 1 the 5th input end and one the 3rd output terminal, second output terminal of the 5th input end and second rejection gate links, and the 3rd output terminal is exported one the 3rd output signal;

One with the door, its input end is imported described second, third output signal respectively, exports the described signal of packing into.

10, memory device as claimed in claim 3, wherein the reset circuit comprises:

One Sheffer stroke gate, its tool two input ends are imported one respectively and are read (read) signal and and write (write) signal, and tool one output terminal;

One first rejection gate, its tool one first input end, one second input end and one first output terminal, the output terminal of first input end and Sheffer stroke gate is connected;

One second rejection gate, its tool 1 the 3rd input end, a four-input terminal and one second output terminal, the 3rd input end is imported described address clock pulse signal, first output terminal of the four-input terminal and first rejection gate links, and second input end binding of second output terminal and first rejection gate is also exported one second output signal;

One not gate, its tool 1 the 5th input end and one the 3rd output terminal, second output terminal of the 5th input end and second rejection gate links, and the 3rd output terminal is exported one the 3rd output signal;

One rejection gate, its two input end is imported described second, third output signal respectively, exports described reset signal.

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