KR900008517A - Dynamic semiconductor memory device and its functional test device and test method - Google Patents

Abstract

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Description

Dynamic semiconductor memory device and its functional test device and test method

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1 is a block diagram showing the configuration of a dynamic semiconductor memory device according to one embodiment of the present invention;

5A and 5B are views showing the configuration of a logic output circuit of a three-valued output method that simultaneously performs a functional test of a dynamic semiconductor memory device on a plurality of bits of memory cells, and displays the truth table thereof;

5A shows an example of a specific configuration of this logic operation circuit.

5B shows the truth table of the input / output relationship.

Claims (12)

A dynamic type semiconductor memory device including a memory cell array each consisting of a plurality of memory cells for storing information, wherein the semiconductor memory device simultaneously selects a predetermined number of bits of memory cells of the memory cell array A test mode in which information is simultaneously written into a predetermined number of memory cells, and after this writing, information stored in the predetermined number of memory cells is simultaneously read and the quantity / defect of the semiconductor memory device is determined based on the read information. And means for generating a signal indicative of the test mode, activated in response to the test mode indication signal, and means for receiving write data from outside, and means for receiving the write data. Coupled to at least one of the selected number of memory cells Means for writing data inverting a pre-write data value and writing data having the same value as the write data in the remaining memory cells of the selected predetermined number of memory cells, accessing the selected predetermined number of memory cells Means for inverting and reading the stored data of the written memory cell of the inverted data and reading out the stored data of the remaining memory cells as they are, and activated in response to the test mode instruction signal, to the reading means. And a means for outputting a logic value corresponding to the received data. 2. The memory cell array of claim 1, wherein the memory cell array includes a plurality of bit bands, each of the plurality of bit line bands transmitting a first bit line for transmitting data of a selected memory cell and complementary data for the first bit line. A second bit line, wherein the input means and the read means include a plurality of internal data transmission line for transmitting an internal complementary data band, and simultaneously provide the internal data transmission line provided by a number corresponding to the number of selected memory cells. Means for connecting to each of said internal data transmission table and said plurality of bit lines, said connecting means for distinguishing a connection means between at least one of the selected plurality of bit lines and said internal data transmission line, and the remaining bit line; A dynamic semiconductor memory device comprising a connecting means between the remaining internal data transmission line. 2. The memory cell array of claim 1, wherein the memory cell array has a plurality of sub-array blocks, each sub-block has a plurality of bit line bands, each bit line band having a first bit line for transmitting data of a selected memory cell, and the first bit line. Said selecting means comprising a second bit line for transferring data complementary to data relating to the line, said means for selecting one memory cell in each of said sub-array blocks, and a plurality of first internal data transfers; The writing means, at least one provided in each of the sub-array blocks, an I internal data transmission table for transmitting a complementary internal write data band, and a bit line band and first internal data in at least one of the sub-array blocks. The I in the bit line in the corresponding sub array block so that the connecting means between the transmission bands is different from the connecting means between the remaining sub blocks. Means for connecting a data transmission line, a plurality of second internal data transmission lines, at least one provided to the sub-array block, and each of the second internal data transmission lines for transmitting a complementary internal read-out data line. The corresponding sub array block such that the means for reading and the connecting means between at least one bit line of the sub array block and the second internal data transmission line differ from the connecting means between the bit line of the remaining sub array block and the second internal data transmission line. And a means for connecting the second internal data transmission line to the bit line of the second line. A memory cell array having a plurality of memory cells, each of which stores information, includes a process comprising: generating a signal specifying the functional test mode, simultaneously selecting from the memory cell array, a memory corresponding to an externally provided address; A predetermined number of cells and the remainder of the predetermined number of memory cells that accept and write the data to accept the externally given write data and write data inverted from the value of the write data in at least a predetermined number of selected memory cells. The predetermined value of the memory cell selected to write data at the same value as that of the written data in the memory cell and to invert and read the memory data of at least one memory cell for recording the inverted data in response to the test indication signal. Accesses the number and indicates the test mode Functional testing method for the dynamic semiconductor memory device receiving all the read data for output in response to a call to output the logic value corresponding to the received data. The functional test of claim 4, wherein the memory cell array is divided into a plurality of sub-array blocks, and the selecting of the memory cell arrays comprises selecting a 1-bit memory cell from each of the sub-array blocks. Way. The method of claim 4, wherein the output step includes a step of judging whether the read data is the same. Means for simultaneously selecting a predetermined number of memory cells in response to an externally given address; and a plurality of internal data transfer mechanisms for transferring data to be written or read; Means for connecting a plurality of internal data transmission lines, such as a selected memory cell, and a plurality of memory cells simultaneously with the plurality of memory cells in response to an externally given address; and all memory cells simultaneously selected for the remaining memory cells. A dynamic semiconductor memory device having connecting means connected inversely with at least one. In a memory test in which a group memory cell is accessed as a writing unit of data and is accessed as a reading unit of a group of memory cells during at least a test of the plurality of memory cells and the memory cells, an input connection to at least one cell of the group is performed. Reversed to complement at least one corresponding bit of the data written into the cells of the group and an output connection to at least one cell of the group corresponds inversely to complement the corresponding one bit of data read from the cells of the group A functional test device for a dynamic semiconductor memory device. 10. The apparatus of claim 8, wherein a set of input / output lines are used as input and output data to said cell and said inverted input connection and inverted output connection to one cell of said input / output line in said group of cells. A functional test device for a dynamic semiconductor memory device including a connection. The functional test apparatus of a dynamic semiconductor memory device according to claim 8, wherein test data of a common logic state is written to all the memory cells of the group during the test. And having a plurality of parallel datapaths comprising the step of establishing a datapath of a group including the function of the plurality of datapaths in which digital data is inverted twice between an input and an output, wherein the plurality of data selected from the group datapath Applying a normal logic level signal to the input of the selected one of the plurality of datapaths, not less than all selected ones of the path, evaluating a signal appearing at the output of the selected one of the plurality of datapaths, and if the evaluation step 10. A method of functional testing of a dynamic semiconductor memory device for testing digital electronic circuitry for determining whether the selection of the plurality of datapaths is functional when determining that it is a normal logic level. 12. The method according to claim 11, wherein said input signal storage step comprises mediating each of the selected inputs and outputs of said datapath and mediating said inversion in said group datapath. A functional test method for a dynamic semiconductor memory device stored at a logic level different from a normal logic level. ※ Note: The disclosure is based on the initial application.