CN105206677A - Oxide semiconductor thin film transistor and manufacturing method thereof - Google Patents

Abstract

An oxide semiconductor thin film transistor includes a patterned oxide semiconductor layer, a patterned gate dielectric layer, a gate electrode, a hydrogen diffusion control layer, a hydrogen source layer, a source electrode and a drain electrode. The patterned oxide semiconductor layer is disposed on a substrate. The patterned gate dielectric layer is disposed on the patterned oxide semiconductor layer. The gate is disposed on the patterned gate dielectric layer. The hydrogen diffusion control layer is disposed on the gate electrode and the patterned oxide semiconductor layer, and the hydrogen diffusion control layer covers the gate electrode and the patterned gate dielectric layer. The hydrogen source layer is disposed on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, the source and drain electrodes are disposed on the hydrogen source layer, and the hydrogen content of the hydrogen source layer is greater than the hydrogen content of the hydrogen diffusion control layer.

Description

Oxide semiconductor thin film transistor and manufacturing method thereof

technical field

The present invention relates to an oxide semiconductor thin film transistor and a manufacturing method thereof, in particular to an oxide semiconductor thin film transistor and a manufacturing method thereof that use a hydrogen diffusion control layer to control the state of hydrogen entering an oxide semiconductor layer.

Background technique

In recent years, the application of various displays has developed rapidly, and thin film transistor (thinfilmtransistor, TFT) is a semiconductor component widely used in display technology, such as in liquid crystal display (liquid crystal display, LCD), organic light emitting diode (organic light emitting diode, OLED) display and electronic paper (electronic paper, E-paper) and other displays. Thin film transistors are used to provide voltage or current switching, so that display pixels in various displays can display bright, dark and grayscale display effects.

The thin film transistors currently used in the display industry can be distinguished according to the semiconductor layer materials used, including amorphous silicon thin film transistors (a-SiTFT), polysilicon thin film transistors (polysilicon TFT) and oxide semiconductor thin film transistors (oxide semiconductor TFT). Among them, the oxide semiconductor thin film transistor is an oxide semiconductor material that has emerged in recent years. This type of material is generally an amorphous phase (amorphous) structure, so there is no problem of poor uniformity when applied to large-size panels, and it can be used Various methods of film formation, such as sputtering (sputter), spin-on (spin-on) and printing (inkjetprinting) and other methods. Since the electron mobility of oxide semiconductor thin film transistors is generally several times higher than that of amorphous silicon thin film transistors and has the above-mentioned process advantages, some commercial products using oxide semiconductor thin film transistors have gradually been launched on the market.

In the structure of a general oxide semiconductor thin film transistor, the contact resistance between the oxide semiconductor layer and the material of the source/drain will obviously affect the overall electrical performance of the oxide semiconductor thin film transistor. As shown in Figure 1, when the channel width (W) of the thin film transistor is fixed, the channel length (L) becomes smaller and smaller. It can be found that when L is reduced to less than 15 microns, the electrical performance of the oxide semiconductor thin film transistor An offset will occur. Therefore, in order to improve the performance of the oxide semiconductor thin film transistor, it is necessary to improve the contact resistance between the oxide semiconductor layer and the source/drain. The current general practice is to use plasma treatment (plasmatreatment) or directly contact the oxide semiconductor layer with a material with a high hydrogen content to cause hydrogen diffusion, so that part of the region of the oxide semiconductor layer that is expected to be in contact with the source/drain Resistivity decreases. However, the above-mentioned plasma treatment method is likely to cause unstable resistance of the treated oxide semiconductor layer, and the method of directly contacting a material with high hydrogen content to generate hydrogen diffusion is difficult to control its diffusion range, which is likely to cause the original The oxide semiconductor layer to be used as the conduction region is easily affected by diffusion and seriously affects the device characteristics of the thin film transistor, especially in the design of a short-channel thin film transistor.

Contents of the invention

One of the main purposes of the present invention is to provide an oxide semiconductor thin film transistor and its manufacturing method, which uses the hydrogen diffusion control layer to control the entry of hydrogen into the oxide semiconductor layer, so as to avoid the influence of hydrogen entering the conduction region of the oxide semiconductor layer. Regarding the device characteristics of thin film transistors, the conduction region defined here is the shortest distance that electrons move ideally in oxide semiconductor thin film transistors.

An embodiment of the present invention provides an oxide semiconductor thin film transistor, including a substrate, a patterned oxide semiconductor layer, a patterned gate dielectric layer, a gate, a hydrogen diffusion control layer, and a hydrogen source layer , a source and a drain. The patterned oxide semiconductor layer is disposed on the substrate. The patterned gate dielectric layer is disposed on the patterned oxide semiconductor layer. The gate is disposed on the patterned gate dielectric layer. The hydrogen diffusion control layer is disposed on the gate and the patterned oxide semiconductor layer, and the hydrogen diffusion control layer covers the gate and the patterned gate dielectric layer. The hydrogen source layer is disposed on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, and the hydrogen content of the hydrogen source layer is greater than that of the hydrogen diffusion control layer. The source and the drain are disposed on the hydrogen source layer, and the source and the drain are in contact with and electrically connected to the patterned oxide semiconductor layer.

According to an embodiment of the present invention, the hydrogen diffusion control layer directly contacts the patterned oxide semiconductor layer, and the hydrogen source layer directly contacts the hydrogen diffusion control layer.

According to another embodiment of the present invention, wherein the hydrogen source layer directly contacts the patterned oxide semiconductor layer.

According to another embodiment of the present invention, wherein the hydrogen diffusion control layer covers the patterned gate dielectric layer and the gate, the hydrogen diffusion control layer extends from a top surface of the gate along one side of the gate extending toward the patterned oxide semiconductor layer and not exceeding the projection range of the hydrogen diffusion control layer on the top surface vertically projected on the substrate.

According to another embodiment of the present invention, the hydrogen diffusion control layer further has an extension portion in a horizontal direction, and the extension portion covers both ends of the patterned oxide semiconductor layer in the horizontal direction.

According to another embodiment of the present invention, the oxide semiconductor thin film transistor further includes a plurality of contact openings penetrating through the hydrogen source layer, wherein the source and the drain pass through the contact openings and the patterned oxide The material semiconductor layers are in contact and electrically connected.

According to another embodiment of the present invention, the contact openings also penetrate through the hydrogen diffusion control layer.

According to another embodiment of the present invention, wherein the hydrogen diffusion control layer comprises metal oxide, silicon nitride, silicon oxide or silicon oxynitride.

According to another embodiment of the present invention, the hydrogen diffusion control layer has a thickness ranging from 100 angstrom to 500 angstrom.

According to another embodiment of the present invention, the hydrogen source layer comprises silicon nitride, silicon oxide or silicon oxynitride.

According to another embodiment of the present invention, the patterned oxide semiconductor layer includes InGaZnO, ZnO, IZnO or InGaO.

According to another embodiment of the present invention, wherein the hydrogen content of the hydrogen source layer is between 15 atoms/cm ³ and 27 atoms/cm ³ .

Another embodiment of the present invention provides a method for fabricating an oxide semiconductor thin film transistor, including the following steps. Forming a patterned oxide semiconductor layer on a substrate; forming a patterned gate dielectric layer on the patterned oxide semiconductor layer; forming a gate on the patterned gate dielectric layer; forming a hydrogen diffusion control layer on the oxide semiconductor layer, wherein the hydrogen diffusion control layer covers the gate and the patterned gate dielectric layer; forming a hydrogen source layer on the hydrogen diffusion control layer and the patterned oxide semiconductor layer, Wherein the hydrogen content of the hydrogen source layer is greater than the hydrogen content of the hydrogen diffusion control layer; and a source and a drain are formed on the hydrogen source layer, wherein the source and the drain are in contact with the patterned oxide semiconductor layer and are electrically connected connect.

According to an embodiment of the present invention, the hydrogen diffusion control layer covers the patterned gate dielectric layer and the gate, and the hydrogen diffusion control layer extends from a top surface of the gate to the gate along one side of the gate. The patterned oxide semiconductor layer extends, and does not extend beyond the projection range of the hydrogen diffusion control layer on the top surface vertically projected on the substrate.

According to another embodiment of the present invention, the hydrogen diffusion control layer, the patterned gate dielectric layer and the gate use the same mask to define patterns.

According to another embodiment of the present invention, wherein the hydrogen diffusion control layer comprises metal oxide, silicon nitride, silicon oxide or silicon oxynitride.

According to another embodiment of the present invention, wherein the hydrogen content of the hydrogen source layer is between 15 atoms/cm ³ and 27 atoms/cm ³ .

The oxide semiconductor thin film transistor of the present invention uses the hydrogen diffusion control layer covering the gate and the patterned gate dielectric layer to control the diffusion of hydrogen in the hydrogen source layer to the patterned oxide semiconductor layer, and can avoid the hydrogen source The hydrogen in the layer diffuses to the conduction region in the patterned gate dielectric layer through the patterned gate dielectric layer, whereby the electrical properties of the conduction region can be ensured while forming a doped region in the patterned oxide semiconductor layer. In this way, an oxide semiconductor thin film transistor with a short-channel design can be realized.

Description of drawings

FIG. 1 shows a drain current-gate voltage relationship diagram of an oxide semiconductor thin film transistor in the prior art.

2 to 6 illustrate schematic diagrams of the fabrication method of the oxide semiconductor thin film transistor according to the first embodiment of the present invention.

FIG. 7 is a graph showing the drain current-gate voltage relationship of the oxide semiconductor thin film transistor according to the first embodiment of the present invention.

FIG. 8 is a schematic diagram of an oxide semiconductor thin film transistor of a comparative example.

FIG. 9 is a graph showing the drain current-gate voltage relationship of the oxide semiconductor thin film transistor of the comparative example.

FIG. 10 is a schematic diagram of an oxide semiconductor thin film transistor according to a second embodiment of the present invention.

FIG. 11 is a schematic diagram of an oxide semiconductor thin film transistor according to a third embodiment of the present invention.

FIG. 12 and FIG. 13 are schematic diagrams illustrating a manufacturing method of an oxide semiconductor thin film transistor according to a fourth embodiment of the present invention.

FIG. 14 is a graph showing the drain current-gate voltage relationship of the oxide semiconductor thin film transistor according to the fourth embodiment of the present invention.

【Symbol Description】

10 substrates

20 Patterning the oxide semiconductor layer

20A conduction area

20B doped region

30 Patterned gate dielectric layer

30F Junction

30S side

40 grid

50 hydrogen diffusion control layer

50A extension

60 hydrogen source layer

70D drain

70S source

101-104 Oxide Semiconductor Thin Film Transistors

200 oxide semiconductor thin film transistors

Hhorizontal direction

Stop

V contact opening

W1 first width

W2 second width

W3 third width

Z vertical direction

Detailed ways

In order to enable those who are familiar with the technical field of the present invention to further understand the present invention, the preferred embodiments of the present invention are listed below, together with the accompanying drawings, to describe in detail the composition of the present invention and the desired effect .

Please refer to Figure 2 to Figure 6. 2 to 6 illustrate schematic diagrams of the fabrication method of the oxide semiconductor thin film transistor according to the first embodiment of the present invention. The manufacturing method of the oxide semiconductor thin film transistor of this embodiment includes the following steps. First, as shown in FIG. 2 , a patterned oxide semiconductor layer 20 is formed on the substrate 10 . The substrate 10 may include a rigid substrate such as a glass substrate and a ceramic substrate, a flexible substrate such as a plastic substrate, or a substrate formed of other suitable materials. The material of the patterned oxide semiconductor layer 20 may include indium gallium zinc oxide, zinc oxide, indium zinc oxide, indium gallium oxide or other suitable oxide semiconductor materials, and the patterned oxide semiconductor layer 20 may be obtained by, for example, lithography, etching, etc. The patterning effect can be achieved through other processes or directly formed by rolltoroll, but not limited thereto. Next, a patterned gate dielectric layer 30 and a gate 40 are formed on the patterned oxide semiconductor layer 20 . The patterned gate dielectric layer 30 and the gate 40 can be defined and formed by the same photoresist pattern (not shown), so that the pattern of the patterned gate dielectric layer 30 and the pattern of the gate 40 are aligned in the vertical direction Z The self-aligned (self-aligned) effect can be achieved, but not limited thereto. The patterned gate dielectric layer 30 can be a single-layer or multi-layer dielectric material layer, and its material can include inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, and Metal oxides such as alumina, organic materials such as acrylic resins, or other suitable dielectric materials. In addition, the gate 40 may include metal materials such as at least one of aluminum, copper, silver, chromium, titanium, and molybdenum, a composite layer of the above materials, or an alloy of the above materials, but it is not limited thereto and other materials with Materials with conductive properties.

Next, as shown in FIG. 3 , a hydrogen diffusion control layer 50 is formed on the patterned gate dielectric layer 30 . And as shown in FIG. 4, the hydrogen diffusion control layer 50 is patterned. In this step, the hydrogen diffusion control layer 50, the patterned gate dielectric layer 30 and the gate 40 use the same mask (mask) to define a pattern, The exposure amount is used to determine the size of the hydrogen diffusion control layer 50 covering the patterned gate dielectric layer 30 . In detail, the hydrogen diffusion control layer 50 is U-shaped, completely covering the patterned gate dielectric layer 30 and the side 30S of the gate 40 and the junction 30F between the side 30S and the patterned oxide semiconductor layer 20, allowing hydrogen to diffuse The control layer 50 extends from the top surface S of the gate 40 to the patterned oxide semiconductor layer 20 along the side 30S in the vertical direction Z, and does not extend beyond the projection of the hydrogen diffusion control layer 50 on the top surface S vertically projected on the substrate 10 scope. The horizontal direction H is preferably perpendicular to the vertical direction Z, and the vertical direction Z is preferably substantially perpendicular to the surface of the substrate 10 , but not limited thereto. In this embodiment, the hydrogen diffusion control layer 50 only covers the side 30S of the patterned gate dielectric layer 30 and the patterned oxide semiconductor The junction 30F of the layer 20 , so the hydrogen diffusion control layer 50 does not cover both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H, but the invention is not limited thereto. In other embodiments of the present invention, the patterned oxide semiconductor layer 20 may be fully covered or at least both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H may be covered as required. The hydrogen diffusion control layer 50 may include an insulating material with a lower hydrogen content than the hydrogen source layer 60, including silicon nitride, silicon oxide, silicon oxynitride, or metal oxide, and the metal oxide may be, for example, aluminum oxide. , calcium oxide, molybdenum oxide, zinc oxide, indium oxide, gallium oxide, indium gallium oxide, indium gallium zinc oxide, indium zinc oxide ( indium zinc oxide), indium tin oxide, titanium oxide, tin oxide, Group III metal oxide, Group IV metal oxide or Group V metal oxide, and other suitable metal oxides Material. The hydrogen content here refers to the hydrogen content of the hydrogen diffusion control layer 50 after the process treatment, and the hydrogen diffusion control layer 50 in this embodiment is preferably aluminum oxide with a relatively dense structure, so as to better prevent hydrogen diffusion. effect, but not limited to this. The hydrogen diffusion control layer 50 can be formed by chemical vapor deposition or physical vapor deposition, and the hydrogen content can be reduced by adjusting the process environment and parameters during the process. In addition, the thickness of the hydrogen diffusion control layer 50 is between 100 angstrom to 1000 angstrom, preferably between 100 angstrom to 500 angstrom, but not limited thereto. It is worth noting that the hydrogen diffusion control layer 50 of this embodiment is provided correspondingly to the gate 40 and the patterned gate dielectric layer 30, so the same mask used in the manufacturing process of the gate 40 can be used to control the hydrogen diffusion. The patterning effect of the control layer 50 can be achieved by using the same mask and adjusting the exposure (exposuredose) to form the corresponding photoresist pattern required for patterning the hydrogen diffusion control layer 50, thereby reducing the mask demand And the effect of reducing the production cost, but not limited thereto.

After that, as shown in FIG. 5 , a hydrogen source layer 60 is formed on the substrate 10 , the patterned oxide semiconductor layer 20 and the hydrogen diffusion control layer 50 . The hydrogen content of the hydrogen source layer 60 is greater than that of the hydrogen diffusion control layer 50 . The material of the hydrogen source layer 60 may include silicon nitride, silicon oxide, silicon oxynitride or other suitable insulating materials with high hydrogen content, and the hydrogen source layer 60 may include silicon nitride or silicon nitride with a higher hydrogen content after the process reaction. Silicon oxide with higher hydrogen content than the hydrogen diffusion control layer 50 after process reaction. The hydrogen source layer 60 can also be formed by chemical vapor deposition or physical vapor deposition, and the hydrogen content can be increased by adjusting the process environment and parameters during the process. For example, when chemical vapor deposition is used to form the hydrogen source layer 60 of silicon nitride, the process temperature may be 280° C., and the reaction gas may include silane (SiH ₄ ) and ammonia (NH ₃ ). , and the amount of methane (SiH ₄ ) and ammonia (NH ₃ ) can be respectively 200 sccm and 1200 sccm, thereby forming silicon nitride with a hydrogen content higher than that of the hydrogen diffusion control layer 50, but not limited thereto . The hydrogen content of the hydrogen source layer 60 in this embodiment is preferably between 15 atoms/cm ³ and 27 atoms/cm ³ , so as to have enough hydrogen to diffuse into the patterned oxide semiconductor layer 20 to form doping District 20B, but not limited thereto. Since the hydrogen diffusion control layer 50 of this embodiment does not cover both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H, both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H are exposed to the hydrogen diffusion control layer. 50 and is in direct contact with the hydrogen source layer 60, thereby enhancing the effect of the hydrogen component in the hydrogen source layer 60 diffusing to the corresponding patterned oxide semiconductor layer 20, thereby reducing the resistivity of the doped region 20B. In this embodiment, two doped regions 20B are formed where the patterned oxide semiconductor layer 20 is in direct contact with the hydrogen source layer 60 , and are connected to the hydrogen diffusion control layer 50 , the gate 40 and the patterned gate dielectric layer 30 The corresponding region still maintains the conductive region 20A with semiconductor characteristics. In other words, the patterned oxide semiconductor layer 20 of this embodiment may include a conduction region 20A and two doped regions 20B after the hydrogen source layer 60 is formed, the gate 40 overlaps the conduction region 20A in the vertical direction Z, The two doped regions 20B are respectively located on two sides of the conduction region 20A in the horizontal direction H, and the resistivity of the doped regions 20B is smaller than the resistivity of the conduction region 20A.

It is worth noting that, since the hydrogen diffusion control layer 50 of this embodiment covers the patterned gate dielectric layer 30, it is possible to prevent the hydrogen in the hydrogen source layer 60 from passing through the patterned gate dielectric layer 30 laterally. Affects the electrical condition of the conductive region 20A. The hydrogen diffusion control layer 50 covering the junction 30F between the side 30S of the patterned gate dielectric layer 30 and the patterned oxide semiconductor layer 20 can also be used to control the range of the doped region 20B to avoid making the doped region 20B If the range is too large, the entire patterned oxide semiconductor layer 20 is in an electrically conductive state. In this embodiment, the hydrogen diffusion control layer 50 disposed on the gate 40 and covering the gate 40 and the patterned gate dielectric layer 30 has a first width W1 in the horizontal direction H, and the gate 40 in the horizontal direction H has a second width W2, the conduction region 20A has a third width W3 in the horizontal direction H, and the first width W1 of the hydrogen diffusion control layer 50 is greater than or equal to the third width W3 of the conduction region 20A. The width of the conduction region 20A can be controlled by adjusting the hydrogen diffusion condition of the hydrogen source layer 60. For example, when the hydrogen diffusion condition of the hydrogen source layer 60 is strong, the third width W3 of the conduction region 20A may also be smaller than the gate 40. The second width W2. In addition, the manufacturing method of this embodiment may optionally further include a heat treatment process to assist the hydrogen diffusion effect of the hydrogen source layer 60 , but it is not limited thereto.

Then, as shown in FIG. 6 , a plurality of contact holes V are formed in the hydrogen source layer 60 , and the contact holes V penetrate the hydrogen source layer 60 to expose a part of the doped region 20B. Afterwards, a source 70S and a drain 70D are formed on the hydrogen source layer 60 , thereby completing the oxide semiconductor thin film transistor 101 shown in FIG. 5 . The source 70S and the drain 70D are in contact with and electrically connected to the two doped regions 20B through the contact opening V. The source 70S and the drain 70D may respectively include metal materials such as aluminum, copper, silver, chromium, titanium, and molybdenum. At least one of them is a composite layer of the above materials or an alloy of the above materials, but it is not limited thereto and other materials with conductive properties can be used.

As shown in FIG. 6, the oxide semiconductor thin film transistor 101 of this embodiment includes a patterned oxide semiconductor layer 20, a patterned gate dielectric layer 30, a gate 40, a hydrogen diffusion control layer 50, a hydrogen source layer 60, a source pole 70S and drain 70D. The patterned oxide semiconductor layer 20 is disposed on the substrate 10 . The patterned gate dielectric layer 30 is disposed on the patterned oxide semiconductor layer 20 . The gate 40 is disposed on the patterned gate dielectric layer 30 . The hydrogen diffusion control layer 50 is disposed on the gate 40 and the patterned oxide semiconductor layer 20 , and the hydrogen diffusion control layer 50 covers the gate 40 and the patterned gate dielectric layer 30 . The hydrogen source layer 60 is disposed on the hydrogen diffusion control layer 50 and the patterned oxide semiconductor layer 20 , and the hydrogen content of the hydrogen source layer 60 is greater than that of the hydrogen diffusion control layer 50 . The source 70S and the drain 70D are disposed on the hydrogen source layer 60 , and the source 70S and the drain 70D are in contact with and electrically connected to the two doped regions 20B through the contact opening V. The material characteristics of each element in the oxide semiconductor thin film transistor 101 have been described in the above-mentioned manufacturing method, so they will not be repeated here. It should be noted that the hydrogen diffusion control layer 50 of this embodiment is preferably in direct contact with the patterned oxide semiconductor layer 20, the hydrogen source layer 60 is preferably in direct contact with the hydrogen diffusion control layer 50, and the hydrogen source layer 60 is in direct contact with the doped oxide semiconductor layer 20. impurity region 20B, but not limited thereto. The hydrogen diffusion control layer 50 of this embodiment can control the diffusion of hydrogen in the hydrogen source layer 60 to the patterned oxide semiconductor layer 20, and at the same time prevent the hydrogen in the hydrogen source layer 60 from passing through the patterned gate dielectric layer 30 to diffuse into the conductive region 20A in the patterned oxide semiconductor layer 20 . Under this design, even if the gate 40 and the patterned gate dielectric layer 30 need to be reduced due to the short-channel design, the hydrogen diffusion control layer 50 can still be used to control the size of the doped region 20B and avoid the conductive region 20A. performance is affected, thereby improving the device characteristics of the oxide semiconductor thin film transistor 101 .

For example, please refer to FIG. 6 to FIG. 9 . FIG. 7 shows the relationship between the drain current and the gate voltage of the oxide semiconductor thin film transistor 101 according to the first embodiment when the channel width (W) and the channel length (L) are both 5 μm. FIG. 8 is a schematic diagram of an oxide semiconductor thin film transistor 200 of a comparative example. FIG. 9 shows the relationship between the drain current and the gate voltage of the oxide semiconductor thin film transistor 200 of the comparative example under the design condition that both the channel width and the channel length are 5 μm. The oxide semiconductor thin film transistor 200 of this comparative example is similar to the oxide semiconductor thin film transistor 101 except that it does not include the hydrogen diffusion control layer 50 of the first embodiment. As shown in FIG. 6 and FIG. 7 , the oxide semiconductor thin film transistor 101 of the first embodiment can still have a good thin film when the ratio of the channel width to the channel length is relatively high when the hydrogen diffusion control layer 50 is provided. Transistor characteristics, and its carrier mobility (mobility) can reach about 22cm ² /VS. Relatively speaking, as shown in FIG. 8 and FIG. 9 , since the hydrogen diffusion control layer is not provided, the oxide semiconductor thin film transistor of this comparative example will be biased to conduction under the condition that the ratio of the channel width to the channel length is relatively high. With thin film transistor characteristics.

Different embodiments of the present invention will be described below, and to simplify the description, the following description mainly focuses on the differences of the embodiments, and the similarities will not be repeated. In addition, the same elements in the various embodiments of the present invention are marked with the same symbols, so as to facilitate mutual comparison between the various embodiments.

Please refer to Figure 10. FIG. 10 shows a schematic diagram of an oxide semiconductor thin film transistor 102 according to a second embodiment of the present invention. The difference from the first embodiment above is that the third width W3 of the conduction region 20A in this embodiment is smaller than the first width W1 of the hydrogen diffusion control layer 50 , and the third width W3 of the conduction region 20A is substantially the same as the gate 40 The second width W2 is the same, but not limited thereto.

Please refer to Figure 11. FIG. 11 shows a schematic diagram of an oxide semiconductor thin film transistor 103 according to a third embodiment of the present invention. The difference from the above-mentioned first embodiment is that this embodiment can make the third width W3 of the conduction region 20A smaller than the second width W2 of the gate 40 by strengthening the diffusion effect of hydrogen in the hydrogen source layer 60, thereby achieving more The purpose of further shortening the channel width of the oxide semiconductor thin film transistor 103 . The above-mentioned method of strengthening the hydrogen diffusion effect in the hydrogen source layer 60 may include increasing the concentration of hydrogen in the strong hydrogen source layer 60 (for example, additionally injecting hydrogen gas when depositing the hydrogen source layer 60), applying an auxiliary treatment such as heat treatment or other suitable A method that can be used to enhance the hydrogen diffusion effect.

Please refer to Figure 12 and Figure 13. FIG. 12 and FIG. 13 are schematic diagrams illustrating a manufacturing method of an oxide semiconductor thin film transistor according to a fourth embodiment of the present invention. The difference from the first embodiment above is that, as shown in FIG. 12 , the hydrogen diffusion control layer 50 of this embodiment can completely cover the patterned oxide semiconductor layer 20 , the patterned gate dielectric layer 30 and the gate 40 , Therefore, the hydrogen diffusion control layer 50 covers both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H, while the hydrogen source layer 60 does not directly contact the patterned oxide semiconductor layer 20 and the subsequently formed doped region 20B. In this manner, it is possible to avoid the excessively strong hydrogen diffusion effect in the hydrogen source layer 60 from causing the correspondingly formed doped region 20B to be too large, thereby affecting the electrical properties of the conduction region 20A. As shown in FIG. 13, when forming the oxide semiconductor thin film transistor 104 of this embodiment, since the doped region 20B is covered by the hydrogen diffusion control layer 50 and the hydrogen source layer 60, the contact opening V needs to penetrate the hydrogen source layer 60. The hydrogen diffusion control layer 50 partially exposes the two doped regions 20B, so that the source 70S and the drain 70D can contact the doped regions 20B through the contact opening V to form an electrical connection. In addition, the hydrogen diffusion control layer 50 of this embodiment further has an extension portion 50A, and the extension portion 50A covers both ends of the patterned oxide semiconductor layer 20 in the horizontal direction H.

Please refer to Figure 14, and please refer to Figure 13 as well. FIG. 14 shows the relationship between the drain current and the gate voltage of the oxide semiconductor thin film transistor 104 of the present embodiment under the design condition that both the channel width and the channel length are 5 μm. As shown in FIG. 14 and FIG. 13 , the oxide semiconductor thin film transistor 104 of this embodiment can still have a good thin film transistor under the condition that the ratio of the channel width to the channel length is relatively high when the hydrogen diffusion control layer 50 is provided. characteristics, and its carrier mobility (mobility) can reach about 13cm ² /VS. Although the carrier mobility of the oxide semiconductor thin film transistor 104 of this embodiment is lower than that of the above-mentioned first embodiment, since the hydrogen diffusion control layer 50 of this embodiment covers the patterned oxide semiconductor layer 20, the hydrogen source layer 60 does not The patterned oxide semiconductor layer 20 is directly in contact with, so the control accuracy of the hydrogen concentration of the hydrogen source layer 60 can be relatively relaxed, which is beneficial to the progress of the manufacturing process. Relatively speaking, as shown in FIG. 8 and FIG. 9 , since no hydrogen diffusion control layer is provided, the oxide semiconductor thin film transistor of this comparative example will be biased to conduction under the condition that the ratio of the channel width to the channel length is relatively high. With thin film transistor characteristics.

In summary, the oxide semiconductor thin film transistor of the present invention uses the hydrogen diffusion control layer to control the diffusion of hydrogen in the hydrogen source layer to the patterned oxide semiconductor layer, and at the same time prevent the hydrogen in the hydrogen source layer from passing through the patterned gate. The electrode dielectric layer diffuses into the conduction region in the patterned gate dielectric layer to affect the electrical properties of the conduction region. Therefore, even if the gate and the patterned gate dielectric layer in the oxide semiconductor thin film transistor need to be reduced in order to comply with the short channel design, the hydrogen diffusion control layer can still be used to control the formation range of the doped region and avoid the conductive region. performance is affected, so the purpose of improving the device characteristics of the oxide semiconductor thin film transistor can be achieved. In addition, the manufacturing method of the oxide semiconductor thin film transistor of the present invention can use the same mask to define the hydrogen diffusion control layer, the patterned gate dielectric layer and the pattern of the gate, thereby achieving the purpose of reducing the manufacturing cost.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (17)

1. an oxide semiconductor thin-film transistor, comprising:

One substrate;

One patterned oxide semiconductor layer, is arranged on this substrate;

One patterning gate dielectric, is arranged on this patterned oxide semiconductor layer;

One grid, is arranged on this patterning gate dielectric;

One hydrogen trap key-course, is arranged on this grid and this patterned oxide semiconductor layer, wherein this hydrogen trap key-course this grid coated and this patterning gate dielectric;

One hydrogen source layer, be arranged on this hydrogen trap key-course and this patterned oxide semiconductor layer, wherein the hydrogen content of this hydrogen source layer is greater than the hydrogen content of this hydrogen trap key-course; And

One source pole and one drains, and is arranged in this hydrogen source layer, and wherein this source electrode and this drain electrode contact with this patterned oxide semiconductor layer and be electrically connected.

2. oxide semiconductor thin-film transistor as claimed in claim 1, wherein this hydrogen trap key-course directly contacts this patterned oxide semiconductor layer, and this hydrogen source layer directly contacts this hydrogen trap key-course.

3. oxide semiconductor thin-film transistor as claimed in claim 1, wherein this hydrogen source layer directly contacts this patterned oxide semiconductor layer.

4. oxide semiconductor thin-film transistor as claimed in claim 1, wherein this hydrogen trap key-course covers this patterning gate dielectric and this grid, this hydrogen trap key-course extends along a side of this grid to this patterned oxide semiconductor layer from an end face of this grid, and extends and do not exceed this hydrogen trap key-course and be positioned at this end face upright projection in the drop shadow spread of this substrate.

5. oxide semiconductor thin-film transistor as claimed in claim 4, wherein this hydrogen trap key-course also has an extension in a horizontal direction, and this extension covers this patterned oxide semiconductor layer in the two ends of this horizontal direction.

6. oxide semiconductor thin-film transistor as claimed in claim 1, also comprises multiple contact perforate, runs through this hydrogen source layer, and wherein this source electrode and this drain electrode contact perforate through these and to contact with this patterned oxide semiconductor layer and to be electrically connected.

7. oxide semiconductor thin-film transistor as claimed in claim 6, wherein these contact perforates also run through this hydrogen trap key-course.

8. oxide semiconductor thin-film transistor as claimed in claim 1, wherein this hydrogen trap key-course comprises metal oxide, silicon nitride, silica or silicon oxynitride.

9. oxide semiconductor thin-film transistor as claimed in claim 1, wherein the thickness of this hydrogen trap key-course is between 100 dust to 500 dusts.

10. oxide semiconductor thin-film transistor as claimed in claim 1, wherein this hydrogen source layer comprises silicon nitride, silica or silicon oxynitride.

11. oxide semiconductor thin-film transistors as claimed in claim 1, wherein this patterned oxide semiconductor layer comprises indium oxide gallium zinc, zinc oxide, indium zinc oxide or indium oxide gallium.

12. oxide semiconductor thin-film transistors as claimed in claim 1, wherein this hydrogen content of this hydrogen source layer is between 15atoms/cm ³to 27atoms/cm ³between.

The manufacture method of 13. 1 kinds of oxide semiconductor thin-film transistors, comprising:

A patterned oxide semiconductor layer is formed on a substrate;

A patterning gate dielectric is formed on this patterned oxide semiconductor layer;

A grid is formed on this patterning gate dielectric;

A hydrogen trap key-course is formed, wherein this hydrogen trap key-course this grid coated and this patterning gate dielectric on this grid and this patterned oxide semiconductor layer;

On this hydrogen trap key-course and this patterned oxide semiconductor layer, form a hydrogen source layer, wherein the hydrogen content of this hydrogen source layer is greater than the hydrogen content of this hydrogen trap key-course; And

In this hydrogen source layer, form one source pole and a drain electrode, wherein this source electrode and this drain electrode contact with this patterned oxide semiconductor layer and are electrically connected.

The manufacture method of 14. oxide semiconductor thin-film transistors as claimed in claim 13, this hydrogen trap key-course covers this patterning gate dielectric and this grid, this hydrogen trap key-course extends along a side of this grid to this patterned oxide semiconductor layer from an end face of this grid, and extends and do not exceed this hydrogen trap key-course and be positioned at this end face upright projection in the drop shadow spread of this substrate.

The manufacture method of 15. oxide semiconductor thin-film transistors as claimed in claim 14, wherein this hydrogen trap key-course, this patterning gate dielectric and this grid use same mask to define figure.

The manufacture method of 16. oxide semiconductor thin-film transistors as claimed in claim 13, wherein this hydrogen trap key-course comprises metal oxide, silicon nitride, silica or silicon oxynitride.

The manufacture method of 17. oxide semiconductor thin-film transistors as claimed in claim 13, wherein this hydrogen content of this hydrogen source layer is between 15atoms/cm ³to 27atoms/cm ³between.