CN106997903A - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

The invention discloses a thin film transistor and a manufacturing method thereof. The thin film transistor has a first patterned semiconductor layer with a lower resistance value and a second patterned semiconductor layer with a higher resistance value, and the first patterned semiconductor layer is separated from the gate electrode. Closer, and the second patterned semiconductor layer is closer to the drain, so the number of additional carriers generated by the back channel being affected by the drain can be reduced, thereby reducing the critical voltage of the thin film transistor as different drain voltages change. amplitude.

Description

Thin film transistor and its manufacturing method

technical field

The invention relates to a thin film transistor and a manufacturing method thereof, in particular to a thin film transistor having two patterned semiconductor layers with different resistance values and a manufacturing method thereof.

Background technique

In recent years, the application of various flat-panel displays has developed rapidly. Various daily necessities such as televisions, mobile phones, automobiles, and even refrigerators can be combined with flat-panel displays. In flat panel display technology, thin film transistor (thin film transistor, TFT) is a widely used semiconductor element, such as in liquid crystal display (liquid crystal display, LCD), organic light emitting diode (organic light emitting diode, OLED) display and electronic paper (electronic paper, E-paper) and other flat-panel displays. Thin film transistors are used to provide voltage or current switching, so that display pixels in various displays can display bright, dark and grayscale display effects.

The thin film transistors currently used in the display industry can be distinguished according to the semiconductor layer materials used, including amorphous silicon thin film transistors (a-Si TFT), polysilicon thin film transistors (poly silicon TFT) and oxide semiconductor thin film transistors (metal oxide semiconductor TFT). Compared with polysilicon thin film transistors, oxide semiconductor thin film transistors have the advantages of higher electron mobility and simpler manufacturing process, so they are considered to have the opportunity to replace the current mainstream amorphous silicon thin film transistors. However, in the bottom-gate thin film transistor, since the back channel in the semiconductor layer is closer to the drain, when a voltage is applied to the drain, additional carriers will be generated in the back channel region, which will cause The threshold voltage of the thin film transistor changes, thereby reducing the control capability of the front channel (front channel) in the semiconductor layer close to the gate, making it more difficult to control the thin film transistor.

Contents of the invention

One of the main objectives of the present invention is to provide a thin film transistor and its manufacturing method, which can avoid the problem of threshold voltage change by arranging two patterned semiconductor layers with different resistance values.

To achieve the above object, an embodiment of the present invention provides a thin film transistor, which includes a substrate, a gate, a drain, a source, a gate insulating layer, a first patterned semiconductor layer and a first Second, patterning the semiconductor layer. The gate is disposed on the substrate, and the gate insulating layer is disposed on the gate. The first patterned semiconductor layer and the second patterned semiconductor layer are disposed on the gate insulating layer, wherein the gate is disposed between the substrate and the first patterned semiconductor layer, and the first patterned semiconductor layer is disposed on the second patterned semiconductor layer layer and the gate insulating layer, and the area of the first patterned semiconductor layer is larger than the area of the second patterned semiconductor layer. The drain and the source are arranged on the first patterned semiconductor layer and electrically connected with the first patterned semiconductor layer.

To achieve the above purpose, an embodiment of the present invention provides a method for manufacturing a thin film transistor, which includes the following steps. First, a gate is formed on a substrate, and a gate insulating layer is formed on the gate, and then a first semiconductor layer and a second semiconductor layer are sequentially formed on the gate insulating layer, wherein the first semiconductor layer is set between the second semiconductor layer and the gate insulating layer. Then, a patterned insulating layer is formed on the second semiconductor layer, and then the patterned insulating layer is used as an etching mask, and a first etching process is performed on the second semiconductor layer to form a second patterned semiconductor layer. Then, the first semiconductor layer is patterned to form a first patterned semiconductor layer, wherein the area of the first patterned semiconductor layer is larger than the area of the second patterned semiconductor layer, and a drain electrode and a drain electrode are formed on the patterned insulating layer. The source electrode, wherein the drain electrode and the source electrode are electrically connected to the first patterned semiconductor layer.

To achieve the above purpose, another embodiment of the present invention provides a method for fabricating a thin film transistor, which includes the following steps. A gate is first formed on a substrate, then a gate insulating layer is formed on the gate, and then a first semiconductor layer and a second semiconductor layer are sequentially formed on the gate insulating layer, wherein the first semiconductor layer is set between the second semiconductor layer and the gate insulating layer. Then, patterning the first semiconductor layer and the second semiconductor layer to form a first patterned semiconductor layer and a second pre-patterned semiconductor layer, and then forming a patterned interlayer dielectric on the second pre-patterned semiconductor layer layer, wherein the patterned interlayer dielectric layer has a first contact hole and a second contact hole. Then, using the patterned interlayer dielectric layer as an etching mask, and performing an etching process on the second pre-patterned semiconductor layer to form a second patterned semiconductor layer, the second patterned semiconductor layer has a third The contact hole and a fourth contact hole, wherein the first contact hole communicates with the third contact hole, the second contact hole communicates with the fourth contact hole, and the area of the first patterned semiconductor layer is larger than that of the second patterned semiconductor layer area. Next, a drain and a source are formed on the patterned interlayer dielectric layer, and the drain and the source are filled in the first contact hole, the second contact hole, the third contact hole and the fourth contact hole to be electrically connected A first patterned semiconductor layer.

Description of drawings

1 is a schematic partial cross-sectional view of a first embodiment of a thin film transistor of the present invention;

2 to 4 are schematic diagrams of the manufacturing process of the first embodiment of the manufacturing method of the thin film transistor of the present invention;

5 is a schematic partial cross-sectional view of a second embodiment of the thin film transistor of the present invention;

6 to 8 are schematic diagrams of the manufacturing process of the second embodiment of the manufacturing method of the thin film transistor of the present invention.

Symbol Description

1, 2 thin film transistors

100 substrates

102 grid

104 drain

106 source

108 Gate insulating layer

110 first patterned semiconductor layer

112 second patterned semiconductor layer

114 patterned insulating layer

116 first semiconductor layer

118 Second semiconductor layer

120, 122 photoresist

124 patterned interlayer dielectric layer

126 second pre-patterned semiconductor layer

128 The first etching process

130 Second etching process

132 Etching process

V1 first contact hole

V2 second contact hole

V3 third contact hole

V4 fourth contact hole

Z vertical projection direction

detailed description

In order to enable those who are familiar with the technical field of the present invention to have a better understanding of the present invention, the preferred embodiments of the present invention are enumerated below, together with the accompanying drawings, to describe in detail the thin film transistor of the present invention, its manufacturing method and the resulting desired effect.

Please refer to FIG. 1 , which is a partial cross-sectional view of a first embodiment of a thin film transistor of the present invention. The thin film transistor in this embodiment is an example of a thin film transistor applicable to a display panel, but not limited thereto. As shown in FIG. 1 , the thin film transistor 1 of this embodiment includes a substrate 100, a gate 102, a drain 104, a source 106, a gate insulating layer 108, a first patterned semiconductor layer 110, and a second patterned semiconductor layer 112. and patterned insulating layer 114 . The gate 102 is disposed on the substrate 100 , and the gate insulating layer 108 is disposed on the gate 102 and completely covers the gate 102 . The substrate 100 may include a rigid substrate such as a glass substrate and a ceramic substrate, a flexible substrate such as a plastic substrate, or a substrate formed of other suitable materials. The substrate 100 in this embodiment is an example of a glass substrate. The gate 102 is disposed between the substrate 100 and the first patterned semiconductor layer 110 , so the TFT 1 is a bottom-gate TFT. The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 are disposed on the gate insulating layer 108 , wherein the first patterned semiconductor layer 110 is disposed between the second patterned semiconductor layer 112 and the gate insulating layer 108 . The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 overlap part of the gate 102 in a vertical projection direction Z, wherein the vertical projection direction Z refers to a direction perpendicular to the surface of the substrate 100 . The area of the first patterned semiconductor layer 110 is greater than that of the second patterned semiconductor layer 112 , so the second patterned semiconductor layer 112 exposes both ends of the first patterned semiconductor layer 110 . In this embodiment, the first patterned semiconductor layer 110 is indium tin zinc oxide (ITZO), and the second patterned semiconductor layer 112 is indium gallium zinc oxide (IGZO), wherein the etching rate of aluminum acid on indium gallium zinc oxide Faster, while indium tin zinc oxide can resist aluminum etchant (Al etchant), so the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 have high selective etching ratio for aluminum etchant, when using aluminum etchant When the second patterned semiconductor layer 112 is etched, the first patterned semiconductor layer 110 is not affected by the aluminum etchant, or is limited by the influence of the aluminum etchant, so that when the aluminum etchant is used for the etching process, it can be The first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 with different patterns are fabricated. In addition, the resistance value of ITO in the first patterned semiconductor layer 110 is lower than the resistance value of InGaZnO in the second patterned semiconductor layer 112 . In other words, in addition to the high selective etching ratio between the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 of this embodiment, the resistance value of the first patterned semiconductor layer 110 is lower than that of the second patterned semiconductor layer 112 resistance.

In addition, the materials of the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 in this embodiment are not limited to ITO and IGZO. For example, the materials of the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 may respectively include indium tin zinc oxide, indium gallium zinc oxide or other types of metal oxide semiconductors, and the first patterned semiconductor layer 110 and the second patterned semiconductor layer The material selection of the second patterned semiconductor layer 112 can meet the above-mentioned conditions that the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 have a high selective etching ratio, and the resistance value of the first patterned semiconductor layer 110 is lower than that of the second patterned semiconductor layer. Two conditions for the resistance value of the patterned semiconductor layer 112 are sufficient. In other variant embodiments, when the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 contain the same type of metal oxide semiconductor material, the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 can be Each has a different crystal structure, such as a crystalline metal oxide semiconductor layer and an amorphous metal oxide semiconductor layer. For example, the first patterned semiconductor layer 110 can be crystalline ITO and the second patterned semiconductor layer 112 can be amorphous ITO, but not limited thereto.

In this embodiment, the patterned insulating layer 114 is disposed on the second patterned semiconductor layer 112, wherein the patterned insulating layer 114 and the second patterned semiconductor layer 112 have substantially the same area and pattern, and the patterned insulating layer The area of 114 and the second patterned semiconductor layer 112 is smaller than the area of the first patterned semiconductor layer 110 . In other words, the patterned insulating layer 114 and the second patterned semiconductor layer 112 only cover part of the first patterned semiconductor layer 110 and expose both ends of the first patterned semiconductor layer 100 . In addition, the drain 104 and the source 106 are disposed on the first patterned semiconductor layer 110 and electrically connected to the first patterned semiconductor layer 110 , and the drain 104 and the source 106 are electrically isolated from each other. In detail, the drain 104 and the source 106 cover and directly contact the top surface and sidewalls of both ends of the first patterned semiconductor layer 110 respectively, and the drain 104 and the source 106 are further extended and disposed on the patterned insulating layer 114 Since the second patterned semiconductor layer 112 is covered by the patterned insulating layer 114 , the drain 104 and the source 106 are not in contact with the top surface of the second patterned semiconductor layer 112 . Through the design that the areas of the patterned insulating layer 114 and the second patterned semiconductor layer 112 are smaller than the area of the first patterned semiconductor layer 110, the drain 104 and the source 106 can be directly connected to the first patterned semiconductor with a lower resistance value. The layer 110 is in direct contact, so the drain 104 and the source 106 of this embodiment can have a lower contact resistance. Since the first patterned semiconductor layer 110 is closer to the gate 102 , the first patterned semiconductor layer 110 can be regarded as the front channel of the TFT 1 , while the second patterned semiconductor layer 112 can be regarded as the back channel. In addition, because the second patterned semiconductor layer 112 has a higher resistance value, the amount of extra carriers generated by the back channel affected by the drain 104 can be reduced, so as to reduce the change range of the threshold voltage of the thin film transistor 1 . On the other hand, since the first patterned semiconductor layer 110 is closer to the gate 102 and has a lower resistance value than the second patterned semiconductor layer 112, most carriers flow in the first patterned semiconductor layer 110, thereby increasing the thickness of the thin film. Control capability of the front channel of transistor 1.

Please refer to FIG. 2 to FIG. 4 , which are schematic diagrams of the manufacturing process of the first embodiment of the manufacturing method of the thin film transistor of the present invention. As shown in FIG. 2 , according to the first embodiment of the present invention, firstly, a substrate 100 is provided, and then a gate 102 is formed on the substrate 100 , and a gate insulating layer 108 is formed on the gate 102 . The way of forming the gate 102 is, for example, first forming a metal layer (not shown) on the entire surface of the substrate 100, and then performing a patterning process on the metal layer, such as performing a photolithography and etching process, so as to form a gate on the substrate 100. Pole 102. The material of the metal layer may include one or more of aluminum, copper, silver, chromium, titanium, molybdenum, a composite layer of the above materials or Alloys of the above materials, but not limited thereto. The material of the gate insulating layer 108 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, graphene oxide, graphene nitride, graphene oxynitride, etc., or organic insulating materials or organic/inorganic hybrid insulating materials. material, and can be a single-layer structure or a composite layer structure, but not limited thereto. Next, the entire surface of the first semiconductor layer 116 and the second semiconductor layer 118 are sequentially formed on the gate insulating layer 108 , wherein the first semiconductor layer 116 is disposed between the second semiconductor layer 118 and the gate insulating layer 108 . In this embodiment, the first semiconductor layer 116 is indium tin zinc oxide (ITZO), and the second semiconductor layer 118 is indium gallium zinc oxide (IGZO), but not limited thereto. The materials of the first semiconductor layer 116 and the second semiconductor layer 118 can respectively include indium tin zinc oxide, indium gallium zinc oxide or other types of metal oxide semiconductors, and the materials of the first semiconductor layer 116 and the second semiconductor layer 118 can be selected as long as It is enough that the first semiconductor layer 116 and the second semiconductor layer 118 have a high selective etching ratio, and the resistance of the first semiconductor layer 116 is lower than the resistance of the second semiconductor layer 118 . In other variant embodiments, the first semiconductor layer 116 and the second semiconductor layer 118 may contain the same metal oxide semiconductor material, but each has a different crystal structure, for example, the first semiconductor layer 116 is crystalline indium tin zinc oxide and The second semiconductor layer 118 is amorphous indium tin zinc oxide, but not limited thereto.

Then, a patterned insulating layer 114 is formed on the second semiconductor layer 118 . The method for forming the patterned insulating layer 114 is, for example, first forming an insulating layer (not shown) on the entire surface of the second semiconductor layer 118, and then using the photoresist 120 to define the position where the patterned insulating layer 114 is to be formed, Then an etching process (such as a dry etching process) is performed to form the patterned insulating layer 114 . The photoresist 120 may be removed using a photoresist stripper (stripper) after the patterned insulating layer 114 is formed, but not limited thereto. The material of the patterned insulating layer 114 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, graphene oxide, graphene nitride, graphene oxynitride, etc., but not limited thereto. The material of the patterned insulating layer 114 may also include an organic insulating material or an organic/inorganic hybrid insulating material, and may be a single-layer structure or a composite layer structure. In addition, the thickness of the patterned insulating layer 114 is, for example, about 500 angstroms, but not limited thereto.

As shown in FIG. 3 , the patterned insulating layer 114 is then used as an etching mask, and a first etching process 128 is performed on the second semiconductor layer 118 to form the second patterned semiconductor layer 112 . In this embodiment, the first etchant is used to perform the first etching process 128 , and the first etchant is an aluminum etchant, so the first etching process 128 is a wet etching process, but not limited thereto. Because the etching rate of aluminum etchant to indium gallium zinc oxide is relatively fast, and indium tin zinc oxide is resistant to aluminum etchant, so in the first etching process 128, the second semiconductor layer 118 can be etched to form the second pattern The semiconductor layer 112 and the first semiconductor layer 116 are generally not affected by the first etchant. In addition, since the patterned insulating layer 114 is directly used as an etching mask in the first etching process 128 , the formed second patterned semiconductor layer 112 has substantially the same pattern and area as the patterned insulating layer 114 . In other words, in this embodiment, the pattern of the second patterned semiconductor layer 112 is defined by patterning the insulating layer 114 .

As shown in FIG. 4 , a patterning process is then performed on the first semiconductor layer 116 to form the first patterned semiconductor layer 110 . The patterning manufacturing process can be, for example, a photolithography and etching manufacturing process. First, a layer of photoresist layer can be coated on the entire surface, and then a photomask can be used to expose the photoresist layer to define the desired pattern. The position of a patterned semiconductor layer 110 is then developed to form a patterned photoresist 122, which has the pattern of the first patterned semiconductor layer 110 to be made, and then carries out a second etching with a second etching solution The manufacturing process 130 is to form the first patterned semiconductor layer 110, and the second etching solution in this embodiment is oxalic acid, but not limited thereto. In this embodiment, the photoresist 122 is formed at the position of the second patterned semiconductor layer 112, and the photoresist 112 has a larger area than the second patterned semiconductor layer 112, and can cover the second The semiconductor layer 112 and the insulating layer 114 are patterned, but not limited thereto. Thus, the area of the first patterned semiconductor layer 110 formed through the second etching process 130 is greater than the area of the second patterned semiconductor layer 112 . In addition, the photoresist 122 may be removed using a photoresist stripper after the first patterned semiconductor layer 110 is formed, but not limited thereto.

Referring to FIG. 1 again, the photoresist 122 is then removed to expose the two ends of the first patterned semiconductor layer 110 not covered by the patterned insulating layer 114 and the second patterned semiconductor layer 112 . Then, the drain 104 and the source 106 are formed on the patterned insulating layer 114, wherein the drain 104 and the source 106 are also formed on the first patterned semiconductor layer 110 and respectively cover and directly contact the first patterned semiconductor layer The top surfaces and sidewalls at both ends of the first patterned semiconductor layer 110 are electrically connected to the drain 104 and the source 106 . In addition, since the second patterned semiconductor layer 112 is covered by the patterned insulating layer 114 , the drain 104 and the source 106 are not in contact with the top surface of the second patterned semiconductor layer 112 . The method of forming the drain 104 and the source 106 may be the same as the method of forming the gate 102 , but not limited thereto. The material of the drain electrode 104 and the source electrode 106 may include one or more of aluminum, copper, silver, chromium, titanium, molybdenum, the above materials The composite layer or the alloy of the above materials, but not limited thereto. According to this embodiment, since the second patterned semiconductor layer 112 is fabricated by directly using the patterned insulating layer 114 as an etching mask in the first etching fabrication process 128, compared with the fabrication of the conventional bottom-gate TFT In this embodiment, the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 with different patterns and areas can be produced without additional photomasks.

The thin film transistor and its manufacturing method of the present invention are not limited to the above-mentioned embodiments. The following will continue to disclose other embodiments of the present invention, but in order to simplify the description and highlight the differences between the embodiments, the same reference numerals are used to mark the same components, and the repeated parts will not be repeated.

Please refer to FIG. 5 , which is a partial cross-sectional view of a second embodiment of the thin film transistor of the present invention. As shown in FIG. 5 , the thin film transistor 2 of this embodiment differs from the first embodiment in that the thin film transistor 2 includes a patterned interlayer dielectric layer 124 disposed on the second patterned semiconductor layer 112 , and the drain 104 The source electrode 106 is disposed on the patterned interlayer dielectric layer 124 . The thickness of the patterned interlayer dielectric layer 124 in this embodiment is, for example, approximately 3000 angstroms, but not limited thereto. The material of the patterned interlayer dielectric layer 124 can be an organic dielectric material or an inorganic dielectric material, and the patterned interlayer dielectric layer 124 can be a single-layer structure or a composite layer structure, and related materials can be selected from the aforementioned patterned The material of the insulating layer 114 will not be repeated here. In addition, the patterned interlayer dielectric layer 124 has a first contact hole V1 and a second contact hole V2, and the second patterned semiconductor layer 112 has a third contact hole V3 and a fourth contact hole V4, wherein the first contact hole V1 and The third contact hole V3 is connected, the second contact hole V2 is connected to the fourth contact hole V4, and the third contact hole V3 and the fourth contact hole V4 do not cover two parts of the top surface of the first patterned semiconductor layer 110 respectively. . In addition, the source electrode 106 is not only disposed on the patterned interlayer dielectric layer 124, but also fills the first contact hole V1 and the third contact hole V3, and is directly connected to a part of the top surface of the first patterned semiconductor layer 110. contact, and the drain electrode 104 is not only disposed on the patterned interlayer dielectric layer 124, but also fills the second contact hole V2 and the fourth contact hole V4 at the same time, and is connected to the top of another part of the first patterned semiconductor layer 110. direct face contact. Since the second patterned semiconductor layer 112 of this embodiment has a contact hole, the area of the second patterned semiconductor layer 112 is smaller than that of the first patterned semiconductor layer 110, and through the design of this embodiment, the drain 104 and the source 106 It can be in direct contact with the first patterned semiconductor layer 110 having a lower resistance value, so the drain electrode 104 and the source electrode 106 in this embodiment can have a lower contact resistance. On the other hand, since the thin film transistor 2 has the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 with different resistance values, the amount of extra carriers generated by the back channel affected by the drain 104 can be reduced, so as to The change range of the threshold voltage of the thin film transistor 2 is reduced, thereby increasing the control capability of the front channel of the thin film transistor 2 . The rest of the features of the thin film transistor 2 of this embodiment are substantially the same as those of the first embodiment, and reference may be made to the description of related component arrangement and materials in FIG. 1 , which will not be repeated here.

Please refer to FIG. 6 to FIG. 8 , which are schematic diagrams of the manufacturing process of the second embodiment of the manufacturing method of the thin film transistor of the present invention. As shown in FIG. 6 , the difference between the second embodiment of the present invention and the first embodiment is that, after forming the first semiconductor layer and the second semiconductor layer (for example, the first semiconductor layer 116 and the second semiconductor layer shown in FIG. 2 118 ), the first semiconductor layer and the second semiconductor layer are patterned first to form the first patterned semiconductor layer 110 and the second pre-patterned semiconductor layer 126 . The first patterned semiconductor layer 110 and the second pre-patterned semiconductor layer 126 can be formed by photolithography and etching process, for example. For example, the first semiconductor layer in this embodiment is indium tin zinc oxide, the second semiconductor layer is indium gallium zinc oxide, and the etching solution used includes oxalic acid, which can simultaneously treat the first semiconductor layer and the second semiconductor layer Etching is performed, but not limited thereto. As shown in FIG. 7 , a patterned interlayer dielectric layer 124 is then formed on the second pre-patterned semiconductor layer 126 , wherein the patterned interlayer dielectric layer 124 has a first contact hole V1 and a second contact hole V2 . The method of forming the patterned interlayer dielectric layer 124 is, for example, first forming a dielectric layer (not shown) on the entire surface, and then performing a patterning process (such as photolithography and etching process) on the dielectric layer, so that the interlayer The first contact hole V1 and the second contact hole V2 are formed in the electrical layer, but not limited thereto.

As shown in FIG. 8, the patterned interlayer dielectric layer 124 is then used as an etching mask, and an etching process 132 is performed on the second pre-patterned semiconductor layer 126 to form a second patterned semiconductor layer 112, wherein the etching process In process 132 , aluminum etchant is used to pattern the second pre-patterned semiconductor layer 126 . After the etching process 132, the second patterned semiconductor layer 112 has a third contact hole V3 and a fourth contact hole V4, wherein the first contact hole V1 communicates with the third contact hole V3, and the second contact hole V2 communicates with the fourth contact hole V3. The four contact holes V4 are connected, so the third contact hole V3 and the fourth contact hole V4 respectively expose two parts of the top surface of the first patterned semiconductor layer 110 . Since the second patterned semiconductor layer 112 of this embodiment has the third contact hole V3 and the fourth contact hole V4 , the area of the first patterned semiconductor layer 110 is larger than the area of the second patterned semiconductor layer 112 . Please continue to refer to FIG. 5, and then form the drain 104 and the source 106 on the patterned interlayer dielectric layer 124. The drain 104 fills the second contact hole V2 and the fourth contact hole V4 and is electrically connected to the first patterned The semiconductor layer 110 , and the source 106 is filled in the first contact hole V1 and the third contact hole V3 and is electrically connected to the first patterned semiconductor layer 110 . In addition, since the top surface of the first patterned semiconductor layer 110 has two parts exposed by the third contact hole V3 and the fourth contact hole V4, the drain 104 can be connected through the second contact hole V2 and the fourth contact hole V4. It is in direct contact with the top surface of a part of the first patterned semiconductor layer 110, and the source 106 can directly contact the top surface of another part of the first patterned semiconductor layer 110 via the first contact hole V1 and the third contact hole V3. . According to this embodiment, since the patterned interlayer dielectric layer 124 is directly used as an etching mask in the etching process 132, no additional light is required compared to the existing method for fabricating bottom-gate thin film transistors. The mask can form the first patterned semiconductor layer 110 and the second patterned semiconductor layer 112 with different areas and patterns. Other manufacturing processes and conditions of the manufacturing method of the thin film transistor 2 of this embodiment and the materials of each component may be substantially the same as those of the first embodiment, and will not be repeated here.

In summary, the second patterned semiconductor layer of the thin film transistor disclosed in the present invention has a higher resistance value, so the number of extra carriers generated by the back channel affected by the drain can be reduced, so as to reduce the threshold of the thin film transistor. The magnitude of the change in voltage. On the other hand, since the first patterned semiconductor layer is closer to the gate and has a lower resistance than the second patterned semiconductor layer, most carriers flow in the first patterned semiconductor layer, thereby increasing the front channel of the thin film transistor. control ability. In addition, in the manufacturing method of the thin film transistor disclosed in the present invention, in the process of forming the second patterned semiconductor layer, the patterned insulating layer or the patterned interlayer dielectric layer is directly used as an etching mask, thus forming the first patterned semiconductor layer with different areas. The first patterned semiconductor layer and the second patterned semiconductor layer do not require additional photomasks compared with the existing method for manufacturing bottom-gate thin film transistors.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (25)

1. A thin film transistor, comprising: Substrate; a gate disposed on the substrate; a gate insulating layer disposed on the gate; The first patterned semiconductor layer and the second patterned semiconductor layer are arranged on the gate insulating layer, wherein the gate is arranged between the substrate and the first patterned semiconductor layer, and the first patterned semiconductor layer is arranged between the second patterned semiconductor layer and the gate insulating layer, and the area of the first patterned semiconductor layer is larger than the area of the second patterned semiconductor layer; and The drain and the source are arranged on the first patterned semiconductor layer and electrically connected with the first patterned semiconductor layer. 2. The thin film transistor according to claim 1, further comprising a patterned insulating layer disposed on the second patterned semiconductor layer, wherein the patterned insulating layer and the second patterned semiconductor layer have substantially the same area . 3. The thin film transistor as claimed in claim 2, wherein the patterned insulating layer and the second patterned semiconductor layer expose two ends of the first patterned semiconductor layer. 4. The thin film transistor as claimed in claim 3, wherein the drain and the source are separately disposed on the patterned insulating layer, and the drain and the source directly contact the two ends of the first patterned semiconductor layer respectively. the top surface, and the drain and the source are not in contact with the top surface of the second patterned semiconductor layer. 5. The thin film transistor according to claim 1, further comprising a patterned interlayer dielectric layer disposed on the second patterned semiconductor layer, wherein the patterned interlayer dielectric layer has a first contact hole and a second contact hole. a contact hole, the second patterned semiconductor layer has a third contact hole and a fourth contact hole, the first contact hole communicates with the third contact hole, the second contact hole communicates with the fourth contact hole, and The third contact hole and the fourth contact hole do not cover the first patterned semiconductor layer. 6. The thin film transistor according to claim 5, wherein the drain and the source are disposed on the patterned interlayer dielectric layer and filled in the first contact hole, the second contact hole, the third contact The hole is in the fourth contact hole and is in contact with the first patterned semiconductor layer. 7. The thin film transistor according to claim 1, wherein the materials of the first patterned semiconductor layer and the second patterned semiconductor layer respectively comprise indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO) or other types metal oxide semiconductors. 8. The thin film transistor as claimed in claim 7, wherein the resistance of the first patterned semiconductor layer is lower than the resistance of the second patterned semiconductor layer. 9. The thin film transistor according to claim 7, wherein the first patterned semiconductor layer and the second patterned semiconductor layer comprise the same material, but the first patterned semiconductor layer is a crystalline metal oxide semiconductor layer and the The second patterned semiconductor layer is an amorphous metal oxide semiconductor layer. 10. A method for manufacturing a thin film transistor, comprising the following steps: forming a gate on a substrate; forming a gate insulating layer on the gate; sequentially forming a first semiconductor layer and a second semiconductor layer on the gate insulating layer, wherein the first semiconductor layer is disposed between the second semiconductor layer and the gate insulating layer; forming a patterned insulating layer on the second semiconductor layer; using the patterned insulating layer as an etching mask, and performing a first etching process on the second semiconductor layer to form a second patterned semiconductor layer; patterning the first semiconductor layer to form a first patterned semiconductor layer, wherein the area of the first patterned semiconductor layer is larger than the area of the second patterned semiconductor layer; and A drain and a source are formed on the patterned insulating layer, wherein the drain and the source are electrically connected to the first patterned semiconductor layer. 11. The method for fabricating a thin film transistor as claimed in claim 10, wherein the patterned insulating layer and the second patterned semiconductor layer have substantially the same area. 12. The manufacturing method of the thin film transistor as claimed in claim 11, wherein the patterned insulating layer and the second patterned semiconductor layer expose two ends of the first patterned semiconductor layer. 13. The manufacturing method of a thin film transistor according to claim 12, wherein the drain and the source directly contact the top surfaces of both ends of the first patterned semiconductor layer respectively, and the drain and the source do not contact the The top surface of the second patterned semiconductor layer. 14. The manufacturing method of the thin film transistor as claimed in claim 10, wherein the first etching process comprises using a first etching solution, and the first etching solution includes aluminum etching solution (Al etchant). 15. The manufacturing method of a thin film transistor according to claim 10, wherein the step of patterning the first semiconductor layer comprises a second etching process using a second etching solution, and the second etching solution including oxalic acid. 16. The method for fabricating a thin film transistor as claimed in claim 10, wherein the materials of the first patterned semiconductor layer and the second patterned semiconductor layer respectively include indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO) or other kinds of metal oxide semiconductors. 17. The thin film transistor as claimed in claim 16, wherein the resistance of the first patterned semiconductor layer is lower than the resistance of the second patterned semiconductor layer. 18. The thin film transistor according to claim 16, wherein the first patterned semiconductor layer and the second patterned semiconductor layer comprise the same material, but the first patterned semiconductor layer is a crystalline metal oxide semiconductor layer and the The second patterned semiconductor layer is an amorphous metal oxide semiconductor layer. 19. A method for manufacturing a thin film transistor, comprising the following steps: forming a gate on a substrate; forming a gate insulating layer on the gate; sequentially forming a first semiconductor layer and a second semiconductor layer on the gate insulating layer, wherein the first semiconductor layer is disposed between the second semiconductor layer and the gate insulating layer; patterning the first semiconductor layer and the second semiconductor layer to form a first patterned semiconductor layer and a second pre-patterned semiconductor layer; forming a patterned interlayer dielectric layer on the second pre-patterned semiconductor layer, wherein the patterned interlayer dielectric layer has a first contact hole and a second contact hole; Using the patterned interlayer dielectric layer as an etching mask, and performing an etching process on the second pre-patterned semiconductor layer to form a second patterned semiconductor layer, the second patterned semiconductor layer has a first Three contact holes and a fourth contact hole, wherein the first contact hole communicates with the third contact hole, the second contact hole communicates with the fourth contact hole, and the area of the first patterned semiconductor layer is larger than the area of the second patterned semiconductor layer; and A drain and a source are formed on the patterned interlayer dielectric layer, the drain and the source fill the first contact hole, the second contact hole, the third contact hole and the fourth contact The hole is electrically connected to the first patterned semiconductor layer. 20. The manufacturing method of the thin film transistor as claimed in claim 19, wherein the third contact hole and the fourth contact hole do not cover the first patterned semiconductor layer, and the drain and the source respectively pass through the first The contact hole, the second contact hole, the third contact hole and the fourth contact hole are in direct contact with the first patterned semiconductor layer. 21. The manufacturing method of the thin film transistor as claimed in claim 19, wherein the etching process comprises using Al etchant to pattern the second pre-patterned semiconductor layer. 22. The manufacturing method of the thin film transistor as claimed in claim 19, wherein the step of patterning the first semiconductor layer and the second semiconductor layer comprises using oxalic acid as an etching solution. 23. The manufacturing method of a thin film transistor as claimed in claim 19, wherein the materials of the first patterned semiconductor layer and the second patterned semiconductor layer respectively include indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO) or other kinds of metal oxide semiconductors. 24. The thin film transistor as claimed in claim 23, wherein the resistance of the first patterned semiconductor layer is lower than the resistance of the second patterned semiconductor layer. 25. The thin film transistor according to claim 23, wherein the first patterned semiconductor layer and the second patterned semiconductor layer comprise the same material, but the first patterned semiconductor layer is a crystalline metal oxide semiconductor layer and the The second patterned semiconductor layer is an amorphous metal oxide semiconductor layer.