CN105205017A - Storage controller based on PCIE SSD - Google Patents

Abstract

The invention discloses a PCIE-based The storage controller of SSD is characterized by utilizing PCIE? The SSD acts as a secondary cache and completes the communication between the SSD and the controller CPU and memory through the PCIE bus.

Description

A storage controller based on PCIE SSD

technical field

The present invention relates to the field of storage hardware, in particular to a PCIESSD-based storage controller.

Background technique

In traditional hardware storage, it generally includes two parts: the controller and the disk. The controller usually communicates with and identifies the disk through SASexpander. Since the disk is a mechanical hard disk, the head needs to be in the disk when data is written or read. Seek to find the address space where the data is stored, resulting in IO delay.

With the development of SSD disk technology, SSDs are used as the secondary cache in the disk cabinets of storage hardware devices to store hot data and improve the read and write performance of the storage controller. However, SSDs also communicate with the controller through the back-end SASexpander backplane, and the performance improvement is also very limited. Currently, the maximum rate of SAS3.0 is 12Gb/S. Figure 1 shows the storage architecture of commonly used SSDs as L2 cache.

Contents of the invention

In order to solve the above technical problems, the present invention provides a PCIESSD-based storage controller. Compared with existing storage devices, the device has the advantages of improving system read and write performance, reducing delay, improving the utilization rate of disk cabinets, and not affecting drive cabinets. Excellent I/O performance and other advantages.

The invention provides a PCIESSD-based storage controller, which is characterized in that the communication between the SSD, the controller CPU and the memory is completed through the PCIE bus.

Further, the storage controller includes two controller modules.

Further, the controller modules are interconnected through a PCIE bus.

Further, the controller modules are respectively equipped with two channel adapters.

Further, the controller modules respectively have two driver interfaces.

Further, the storage controller uses PCI ESSD as a secondary cache.

Further, the PCIESSD is installed in the controller module and does not occupy a disk cabinet slot.

Further, the PCIESSD is connected to the controller CPU through a PCIE bus.

Further, the PCIESSD supports hot plugging.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings .

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solution of the present invention, and constitute a part of the description, and are used together with the embodiments of the application to explain the technical solution of the present invention, and do not constitute a limitation to the technical solution of the present invention.

FIG. 1 is a storage architecture in which SSD is used as a secondary cache in the prior art;

FIG. 2 is an architecture diagram of a PCI ESSD storage controller according to an embodiment of the present invention.

Detailed ways

The present invention is a PCIESSD-based storage controller device, which completes the communication between the SSD, the controller CPU and the memory through the PCIE bus.

In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings . It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

As shown in FIG. 2 , the storage controller architecture involved in the present invention includes two controller modules, which are interconnected through a PCIE bus, and each module is respectively equipped with two channel adapters and two drive interfaces. The storage controller uses the PCIESSD as the secondary cache, and the PCIESSD is connected to the CPU of the controller through the PCIE bus, and supports hot swapping. PCIESSD is installed in the controller, not in the disk enclosure.

Three components, including operation unit, shard management and metadata management, and shard data storage.

Operation unit: Unified scheduling of write tasks and read tasks, and unified processing of write operations and read operations;

Fragmentation management and metadata management: manage all fragmentation information and metadata information, store fragmentation information and metadata information in NVDIMM, and ensure access performance and reliability through NVDIMM's fast access speed and power-off features. ;

Fragmented data storage: all the actual fragmented data is stored, these fragmented data are stored on the actual hard disk, and the data is written in an incremental manner;

As shown in Figure 2 , when there is a write request, the written content is segmented and the segmented data is written into the segmented data storage, and the segmented information is written into the segment management and metadata management components; Completely convert actual write requests into increased write operations to improve hard disk write performance;

As shown in Figure 2 , when there is a read task, the operation unit will obtain the fragmentation status of the data from the metadata management component of the fragmentation management machine according to the read content, and actually read from the fragmentation data storage component according to the fragmentation situation. Get the data;

In summary, it is a high-speed writing method based on discrete storage.

Although the embodiments disclosed in the present invention are as above, the described content is only an embodiment adopted for understanding the present invention, and is not intended to limit the present invention. Anyone skilled in the field of the present invention can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present invention, but the patent protection scope of the present invention must still be The scope defined by the appended claims shall prevail.

Claims (9)

1. a memory controller of Based PC IESSD, is characterized in that, comprising:

The communication between PCIESSD and controller CPU, internal memory is completed by PCIE bus.

2. device according to claim 1, is characterized in that, described memory controller comprises two controller modules.

3. device according to claim 2, is characterized in that, described controller module is by PCIE bus interconnection.

4. device according to claim 2, is characterized in that, described controller module is furnished with two channel adapters respectively.

5. device according to claim 2, is characterized in that, described controller module has two driver interfaces respectively.

6. device according to claim 1, is characterized in that, described memory controller utilizes PCIESSD as L2 cache.

7. device according to claim 6, is characterized in that, described PCIESSD is arranged in controller module, does not take disk chassis slot.

8. device according to claim 6, is characterized in that, described PCIESSD is connected with controller CPU by PCIE bus.

9. device according to claim 6, is characterized in that, affiliated PCIESSD supports hot plug.