CN103838676A - Data storage system, data storage method and PCM bridge - Google Patents

Abstract

Embodiments of the present invention provide a data storage system, a data storage method, and a PCM bridge. The system includes: a processor, a memory controller, a phase-change memory PCM bridge, and a phase-change memory PCM. The processor is connected to the PCM bridge through the memory controller. , the PCM bridge is connected to the PCM, and non-volatile small data is stored in the PCM, and the PCM bridge is used to receive the first operation signal for reading or writing small data from the CPU through the memory controller, and convert the first operation signal A second operation signal capable of reading or writing to the PCM is formed to read small data in the PCM or write small data in the PCM through the second operation signal. The data storage system, the data storage method and the PCM bridge provided by the embodiments of the present invention can be read or written bit by bit by using the PCM, which improves the operation efficiency, increases the life of the system, and accelerates the ability of data access.

Description

Data storage system, data storage method and PCM bridge

technical field

The embodiments of the present invention relate to data storage technologies, and in particular to a data storage system, a data storage method and a PCM bridge.

Background technique

In the storage architecture composed of traditional NAND flash memory NAND Flash, when data is written into NAND Flash in the storage system, NAND Flash needs to be read into Dynamic Random Access Memory (Dynamic Random Access Memory, hereinafter referred to as: DRAM), and modified in DRAM. , and then write back to the process in NAND Flash; in the writing process, the metadata Metadata and the user data Userdata are written into the NAND Flash together, and the metadata Metadata is usually stored in the NANDMetadata block, because the size of the metadata Metadata is generally smaller than that based on NAND The minimum block size of the file system stored in Flash and the frequent updates cause additional management overhead for NAND Flash on the one hand, and increase the life loss of NAND Flash on the other hand; in addition, the operation of NAND Flash itself needs to be erased first before it can be used. programming.

In the process of realizing the embodiment of the present invention, the inventor found that in the prior art, the NAND Flash writing process is complicated, does not support direct writing, and needs to be read into DRAM for modification; frequent modification of metadata Matadata will accelerate the loss of NAND Flash Lifespan, and most of the metadata Matadata is small data, which is smaller than the minimum block device management size of the NAND Flash-based file system, resulting in a waste of file system load.

Contents of the invention

This embodiment provides a data storage system, a data storage method and a PCM bridge, which are used to solve the problem in the prior art that reading and writing NAND Flash causes a waste of file system load.

In a first aspect, an embodiment of the present invention provides a data storage system, including:

Processor, memory controller, phase change memory PCM bridge and phase change memory PCM;

The processor is connected to the PCM bridge through the memory controller, and the PCM bridge is connected to the PCM;

Non-volatile small data is stored in the PCM;

The PCM bridge is used to receive a first operation signal from the CPU for reading or writing small data through the memory controller, and convert the first operation signal into a signal capable of reading or writing the PCM. The second operation signal is used to read small data in the PCM or write small data in the PCM through the second operation signal.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the PCM is specifically used to store non-volatile small data that is often read or written.

With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the first operation signal includes a read signal, and the first operation signal Converting into a second operation signal capable of reading the PCM so as to read the small data in the PCM through the second operation signal includes:

converting the read signal into a read signal capable of reading the PCM so as to read small data in the PCM through the read signal.

With reference to the first aspect or the first possible implementation manner of the first aspect or the second possible implementation manner of the first aspect, in the third possible implementation manner of the first aspect, the PCM bridge is also used for :

The memory controller receives an adjustment signal from the CPU for adjusting the storage location of the small data stored in the PCM, the adjusting the storage location of the small data stored in the PCM Including: moving the small data stored in the PCM with a low frequency of use from the PCM memory, or moving the small data with a high frequency of use to the PCM memory;

converting the adjustment signal into an adjustment signal capable of reading or writing the PCM so as to adjust the storage location of the small data in the PCM through the adjustment signal.

In combination with the first aspect or the first possible implementation manner of the first aspect or the second possible implementation manner of the first aspect or the third possible implementation manner of the first aspect, it further includes:

The memory, connected to the processor through the memory controller, is used to store data required by the CPU for executing programs.

Peripheral memory, used to connect with the CPU through a peripheral interface;

The peripheral memory stores non-volatile large data, and the CPU is also used to read or write the peripheral memory through the peripheral interface, wherein the large data is larger than the small data The data.

In combination with the first aspect or the first possible implementation manner of the first aspect or the second possible implementation manner of the first aspect or the third possible implementation manner of the first aspect, the small data is small user data , or metadata, or any one or more of system log data.

Combining the first aspect and all implementation manners of the first aspect, in another embodiment, the small data is block operation data whose size is smaller than that of general flash operations.

Combining the first aspect and all implementation manners of the first aspect, in another embodiment, the size of the small data byte is less than or equal to 512 bytes.

In a second aspect, an embodiment of the present invention provides a data storage method, including:

The memory controller connected to the PCM bridge is used to read or store the non-volatile small data stored in the phase change memory PCM connected to the PCM bridge from the CPU connected to the memory controller. write first operation signal;

converting the first operation signal into a second operation signal capable of reading or writing the PCM so as to read small data in the PCM or write small data in the PCM through the second operation signal data.

In the first implementation manner of the second aspect, the small data is small data that is frequently read or written.

With reference to the second aspect or the first implementation manner of the second aspect, in the second implementation manner of the second aspect, the first operation signal includes a read signal, and the conversion of the first operation signal into a The second operation signal that the PCM reads to read the small data in the PCM through the second operation signal includes:

converting the read signal into a read signal capable of reading the PCM so as to read small data in the PCM through the read signal.

In combination with the second aspect or the first implementation manner of the second aspect or the second implementation manner of the second aspect, in the third implementation manner of the second aspect, it further includes:

The memory controller receives an adjustment signal from the CPU for adjusting the storage location of the small data stored in the PCM, the adjusting the storage location of the small data stored in the PCM Including: moving the small data stored in the PCM with a low frequency of use from the PCM memory, or moving the small data with a high frequency of use to the PCM memory;

converting the adjustment signal into an adjustment signal capable of reading or writing the PCM so as to adjust the storage location of the small data in the PCM through the adjustment signal.

In combination with the second aspect or the first implementation manner of the second aspect or the second implementation manner of the second aspect or the third implementation manner of the second aspect, the fourth implementation manner of the second aspect further includes:

The memory connected to the processor through the memory controller stores the data required for the CPU to run, so that the CPU can read or write the data required to execute the program;

The peripheral memory is connected to the CPU through a peripheral interface;

The peripheral memory stores non-volatile big data, and the CPU is also used to read or write the peripheral memory through the peripheral interface.

In combination with the second aspect or the first implementation manner of the second aspect or the second implementation manner of the second aspect or the third implementation manner of the second aspect or the fourth implementation manner of the second aspect, the small data is Any one or more of small user data, or metadata, or system log data; or,

The small data is less than the block operation data during the general flash operation; or,

The small data size is less than or equal to 512 bytes.

In a third aspect, an embodiment of the present invention provides a PCM bridge, including:

The receiving unit is used to receive the non-volatile data stored in the phase change memory PCM connected to the PCM bridge from the CPU connected to the memory controller through the memory controller connected to the PCM bridge. The first operation signal for reading or writing small data;

a conversion unit, configured to convert the first operation signal received by the receiving unit into a second operation signal capable of reading or writing the PCM;

A read or write unit, configured to read small data in the PCM or write small data in the PCM according to the second operation signal converted by the conversion unit.

In the first implementation manner of the third aspect, the small data is small data that is frequently read or written.

With reference to the third aspect or the first implementation manner of the third aspect, in the second implementation manner of the third aspect, the first operation signal includes a read signal, and the conversion of the first operation signal into a The second operation signal that the PCM reads to read the small data in the PCM through the second operation signal includes:

converting the read signal into a read signal capable of reading the PCM so as to read small data in the PCM through the read signal.

In combination with the third aspect or the first implementation manner of the third aspect or the second implementation manner of the third aspect, the small data is any one of small user data, or metadata, or system log data, or Various; or,

The small data is less than the block operation data during general flash operation; or

The small data byte size is less than or equal to 512 bytes.

In the data storage system, data storage method, and PCM bridge provided by the embodiments of the present invention, the processor is connected to the PCM bridge through a memory controller, and the PCM bridge is connected to the PCM. Non-volatile small data is stored in the PCM, and the PCM bridge is used for The first operation signal used to read or write the small data stored in the PCM is received by the memory controller from the CPU, and the first operation signal is converted into a second operation signal capable of physically reading or writing the PCM to pass through the second The operation signal reads or writes small data in the PCM. The feature of using PCM to read or write can be read or written bit by bit, which improves the operation efficiency, increases the system life, and accelerates the ability of data access.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of Embodiment 1 of a data storage system provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of Embodiment 2 of the data storage system provided by the embodiment of the present invention;

FIG. 3 is a schematic structural diagram of Embodiment 3 of the data storage system provided by the embodiment of the present invention;

FIG. 4 is a schematic diagram of the software structure of Embodiment 4 of the data storage system provided by the embodiment of the present invention;

FIG. 5 is a schematic flowchart of Embodiment 1 of the data storage method provided by the embodiment of the present invention;

FIG. 6 is a schematic diagram of a data writing process of a data storage method provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of Embodiment 1 of a PCM bridge provided by an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

In a traditional DRAM&Flash/HDD-based storage system, the memory is volatile at high speed, and the storage is relatively low-speed non-volatile. There is an insurmountable gap between the two. PCM has read or write latency close to DRAM and excellent graded Scale capability, indicating its potential for capacity expansion, and also has Byte variability and non-volatility, blurring the boundaries between memory and storage. As the Flash technology faces physical limits, PCM is the most likely technology to replace Flash, and designing a PCM-based storage solution can maximize device performance.

The data storage system, data storage method, and PCM bridge provided by the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of Embodiment 1 of a data storage system provided by an embodiment of the present invention. As shown in FIG. 1 , the data storage system includes a processor 11, a memory controller 12, a phase-change memory PCM bridge 13, and a phase-change memory PCM14. in,

The processor 11 is connected to the PCM bridge 13 through the memory controller 12, and the PCM bridge 13 is connected to the PCM14, and the non-volatile small data is stored in the PCM14 (non-volatile means that the data will not disappear after power off, and will still be stored in the memory), the PCM bridge 13 is used to receive the first operation signal from the CPU for reading or writing small data through the memory controller 12, and convert the first operation signal into a second operation signal capable of reading or writing the PCM14 The small data in the PCM14 can be read or written into the PCM14 through the second operation signal. The first operation signal includes a read or write signal, and converting the first operation signal into a second operation signal capable of reading or writing the PCM to read or write the small data in the PCM through the second operation signal includes: converting the read or write signal to the PCM The write signal is converted into a read or write signal capable of reading or writing to the PCM so as to read or write small data in the PCM through the read or write signal. For example, the CPU sends the first operation signal for logical writing, and the PCM bridge receives the first operation signal through the memory controller, and then converts the first operation signal into a second operation signal capable of physically reading or writing the PCM to pass the second operation signal. The second operation signal writes the small data in the PCM. The read operation is similar to this and will not be repeated here.

Wherein, the small data is small data that is often read or written, and may be determined according to different situations, which is not limited in this embodiment.

Wherein, the PCM bridge is also used to receive an adjustment signal from the CPU for adjusting the storage location of the small data stored in the PCM through the memory controller, and adjusting the storage location of the small data stored in the PCM includes: The small data with lower frequency is moved from the PCM memory, or the small data with higher frequency is moved to the PCM memory; the adjustment signal is converted into an adjustment signal that can read or write the PCM to adjust the small data in the PCM through the adjustment signal to adjust the storage location.

In the data storage system provided by this embodiment, the processor is connected to the PCM bridge through the memory controller, and the PCM bridge is connected to the PCM. Non-volatile small data is stored in the PCM, and the PCM bridge is used to receive data from the CPU through the memory controller. The first operation signal used to read or write the small data stored in the PCM, and convert the first operation signal into a second operation signal that can physically read or write the PCM so that the small data in the PCM can be processed by the second operation signal to read or write. Using PCM to read or write can be read or written bit by bit. When reading or writing is required, only a few bits are needed, which improves the operating efficiency. At the same time, because there is no need to read or write a block each time, the lifespan can be increased, so the operation efficiency is improved, the lifespan of the system is increased, and the ability to speed up data access is realized.

FIG. 2 is a schematic structural diagram of the second embodiment of the data storage system provided by the embodiment of the present invention. As shown in FIG. 2, on the basis of the embodiment shown in FIG. 12 is connected to the processor 11, and the memory 15 is used for the CPU to read or write data required for executing programs.

As an implementable manner, the data storage system may also include a peripheral memory, which is used to connect to the CPU through a peripheral interface, and the peripheral memory stores non-volatile big data (data larger than small data) , such as data whose size exceeds a certain threshold, the size of the "threshold" here is not limited, and those skilled in the art can adjust it according to the actual situation, for example, it can be 512 bytes, or a larger number of bytes), the CPU can also Used to read or write to the peripheral memory through the peripheral interface. Compared with the above embodiments, non-volatile large data can be stored in the peripheral memory for read or write operations.

In the foregoing embodiments, small data is small user data, or metadata, or any one or more of system log data, and small data is block operation data smaller than general flash operations, and the size of small data is less than or equal to 512 words Festival.

A specific embodiment is used below to describe the technical solution of the above-mentioned system embodiment in detail.

Figure 3 is a schematic structural diagram of the third embodiment of the data storage system provided by the embodiment of the present invention. The host adapters of the storage are connected through communication such as Fiber Channel Protocol (Fibre Channel Protocol, FC for short), Ethernet, and the like. The host system includes the first central processing unit CPU. There is a server frame in the host system, and there is a bottom board inside. The multi-core CPU, memory, PCM bridge and other chips are installed on the bottom board, which are used to control other expansion cards and realize the host computer. function; and the host storage module connected on the first central processing unit CPU, the host storage module includes several first phase-change memories PCM and DRAM in the embodiment of the present invention, communicates with the first central processing unit CPU in the memory bus A memory controller is connected, because the PCM is connected with the first memory controller in the CPU so its response and processing speed are fast, but its memory is not particularly large, so for memory needs, the host memory module in the embodiment of the present invention can also include Several phase-change memory dual-in-line memory modules PCM DIMM are connected with the first central processing unit CPU through the input-output transponder IOH, and the phase-change memory dual-in-line memory module PCM DIMM is compared to the response and processing of PCM Slow, but it has a larger memory. Therefore, the host memory module here can be configured to include PCM or/and phase change memory dual in-line memory module PCM DIMM according to different requirements.

The peripheral memory at least includes a peripheral hard disk.

The above-mentioned several phase-change memory dual-in-line memory modules PCM DIMM are connected to the input and output transponder IOH in the form of a standard fast channel PCIE expansion card for interconnecting peripheral components, and connected to the IO in the form of a PCIE expansion card. The PCM DIMM on the Hub can replace NAND flash, providing faster read or write performance and longer service life. PCM memory particles include PCM controller, which is also a chip, such as FPGA, ASIC, etc., by programming this chip to complete the read or write request of the receiving host, and perform various access and control on the PCM chip; PCM control The chip corresponding to the device can be set on a PCB board with each PCM, connected by PCB wiring, and finally presents a dual in-line memory module DIMM strip form, which can be directly accessed through the memory bus Memory bus. In this embodiment, the phase change memory dual in-line memory module PCM DIMM bar and the PCM controller can also be made into a PCIE SSD card, which is connected to the base plate through the PCIE interface, used as the data storage of the host, and accessed through the PCIE.

The peripheral memory also includes a second central processing unit CPU, as shown in Figure 3, a server frame is arranged in the peripheral memory, and a base plate is arranged inside, and chips such as multi-core CPU, memory, PCM bridge are installed on the base plate, are used for pairing other expansion cards for control. The second central processing unit CPU is connected with the peripheral hard disk through the input-output transponder IOH.

The peripheral memory also includes a plurality of second phase change memories PCM and DRAM, PCM and DRAM are connected with the second memory controller in the second central processing unit CPU through the memory bus, and the PCM particles and the controller are connected on the memory bus Memory bus , because PCM power-off data is not lost, it can be stored as small data, accessed in the form of memory, and stored as server code and metadata. The host adapter in the peripheral memory is transferred to the PCIE/SAS/SATA interface NAND SSD and SAS/SATA interface HDD through PCIE through the IO Hub. The peripheral memory host reads or writes small data in PCM/DRAM through the Memory controller, and reads data in PCM through the PCIE card.

In this embodiment, the peripheral hard disk includes NAND Flash and/or hard disk drive HDD.

The embodiment of the present invention improves the data storage process, that is, distinguishes the architecture and channel of large data and small data storage, and based on the feature that PCM memory read or write can be read or written bit by bit, small data storage and read or write are carried out. Optimization, to achieve improved operating efficiency, increased system life, and accelerated data access capabilities.

After introducing PCM as a storage medium, it is necessary to design a storage software system based on byte access, which is different from the file system accessed by block devices, in view of the variable characteristics of PCM bytes. FIG. 4 is a schematic diagram of the software structure of the fourth embodiment of the data storage system provided by the embodiment of the present invention. As shown in FIG. Larger) address space or 64bit (or larger) address space for reading or writing and reallocation, which can perform functions of hot and cold data layers. Under the virtual storage layer, there are virtual PCM storage layer, virtual Flash storage layer, and virtual HDD storage layer. The virtual PCM storage layer realizes address space remapping, atomic-level write operations, and atomic-level write operations are based on CPU's cache memory (Cache Memory) , hereinafter referred to as: Cache) size, very fine granularity division, can read and write in Byte units, log function and wear leveling algorithm, there are multiple PCM particles on the PCM card, controlled by the PCM controller control.

The embodiment of the present invention adopts a three-level accelerated data access acceleration scheme, which solves the current difficulty in the industry regarding performance degradation of small data access.

The first level: the central processing unit CPU is connected to the PCM through the memory bus Memory bus. PCM stores small data and hot data (Small&Hot data), such as metadata Meta data, log log, small user data (small user data) (using the form of PCM byte-by-byte access);

The second level: NAND Flash stores hot data and big data (Hot&large data), and big data hotspot migration accelerates system access;

The third level: in the external storage, PCM replaces Nor Flash, stores code Code, and data base (Data Base (config data))

Fig. 5 is a schematic flow chart of the first embodiment of the data storage method provided by the embodiment of the present invention. The method is applied to the phase change memory PCM bridge. As shown in Fig. 5, the method may include:

S501, receiving the first request from the CPU connected to the memory controller through the memory controller connected to the PCM bridge for reading or writing the non-volatile small data stored in the phase change memory PCM connected to the PCM bridge Action signal.

S502. Convert the first operation signal into a second operation signal capable of physically reading or writing the PCM, so as to read small data in the PCM or write small data in the PCM through the second operation signal.

Wherein, the small data is small data that is often read or written, and may be determined according to different situations, which is not limited in this embodiment. The first operation signal includes a read or write signal, and converting the first operation signal into a second operation signal capable of reading or writing the PCM to read or write the small data in the PCM through the second operation signal includes: converting the read or write signal to the PCM The write signal is converted into a read or write signal capable of reading or writing to the PCM so as to read or write small data in the PCM through the read or write signal. For example, during a write operation, the CPU sends the first operation signal for logical writing, and the PCM bridge receives the first operation signal through the memory controller, and then converts the first operation signal into a second operation that can physically read or write the PCM signal to perform a write operation on the small data in the PCM through the second operation signal. The read operation is similar to this and will not be repeated here.

On the basis of the above embodiments, the data storage method may further include: receiving an adjustment signal from the CPU through the memory controller for adjusting the storage location of the small data stored in the PCM, and adjusting the storage location of the small data stored in the PCM The adjustment specifically includes: moving small data stored in the PCM with low usage frequency from the PCM memory, or moving small data with high usage frequency to the PCM memory. The adjustment signal is converted into an adjustment signal capable of reading or writing the PCM so as to adjust the storage position of the small data in the PCM through the adjustment signal.

The data storage method may also include: storing the data required by the CPU through the memory connected to the processor through the memory controller, for the CPU to read or write the data required for executing the program, the peripheral memory is connected to the CPU through the peripheral interface, and the peripheral It is assumed that the memory stores non-volatile large data, and the CPU is also used to read or write the peripheral memory through the peripheral interface.

In the foregoing embodiments, small data is small user data, or metadata, or any one or more of system log data, and small data is block operation data smaller than general flash operations, and the size of small data is less than or equal to 512 words Festival.

In the data storage method provided by this embodiment, the memory controller connected to the PCM bridge receives the non-volatile small data stored in the phase change memory PCM connected to the PCM bridge from the CPU connected to the memory controller. The first operation signal for reading or writing. The first operation signal is converted into a second operation signal capable of physically reading or writing the PCM so as to read or write small data in the PCM through the second operation signal. Using PCM to read or write can be read or written bit by bit. When reading or writing is required, only a few bits are needed, which improves the operating efficiency. At the same time, because there is no need to read or write a block each time, the lifespan can be increased, so the operation efficiency is improved, the lifespan of the system is increased, and the ability to speed up data access is realized.

A specific embodiment is used below to describe the technical solution of the above-mentioned method embodiment in detail.

The specific data storage method in the embodiment of the present invention can be divided into two situations. One is that if it is judged that the data type of the data to be stored is a system file type, it is directly written into the host memory module PCM; here the system file type includes User data metadata type and/or log log type, namely file system metadata and log log in the embodiment of the present invention, all are written in the PCM as small data;

Second, if it is determined that the data type of the data to be stored is a user file type, and the data size of the data to be stored does not exceed the preset data granularity, and the preset data granularity is less than or equal to 512 bytes, the implementation of the present invention In the example, if the data granularity does not exceed the preset data granularity, it will be written into the host storage module. In the embodiment of the present invention, the user data user data needs to be judged according to the data size. If it is small data (the data size is determined according to the CPU cache size), then write to PCM;

If it is judged that the data type of the data to be stored is a user file type, and the data size of the data to be stored exceeds the data granularity, write to the external hard disk. In the embodiment of the present invention, the user data userdata needs to be judged for the data size, if it is large data (the data size is determined according to the CPUcache size), then write in the peripheral hard disk NAND Flash/HDD.

If it is judged that the data type of the data to be stored is a user file type, and the data size of the data to be stored does not exceed the preset data granularity, it is written into the host storage module. Judging by the size, if it is small data (the size of the data is determined according to the size of the CPU cache), it will be written into the PCM. In this case, it includes:

If it is determined that the data type of the data to be stored is a user file type, and the data size of the data to be stored does not exceed the preset data granularity, the original data of the data to be stored is searched, and if the original data is found in the host storage module, Then update the original data directly at the storage location of the original data. In the embodiment of the present invention, if the user data user data is small data, it is necessary to search for the original data of the small data. If the original data is found in the host storage module PCM, Then update the original data directly at the storage location of the original data; if the original data is not found in the host storage module, then search in the peripheral hard disk.

If the original data is found in the peripheral hard disk, the original data is read into the host storage module, and the original data is updated in the host storage module. After the update, it also includes: marking the original data stored in the host storage module It is dirty data, and it is erased when it is idle. In the embodiment of the present invention, if the original data is found in the NAND Flash, it is considered as an old data update. It is necessary to read the old data into the PCM, and then mark the data in the NAND Flash Dirty data is erased when the NAND Flash is idle. At the same time, the migration of hot data is realized during the moving process. If the data is updated next time, it can be directly hit in the PCM. If the original data cannot be found, it is directly written into the host storage module. In the embodiment of the present invention, if the original data cannot be found in the NAND Flash, it is directly written into the PCM.

The following describes the data writing process in detail in conjunction with FIG. 6. FIG. 6 is a schematic diagram of the data writing process of the data storage method provided by the embodiment of the present invention. As shown in FIG. 6, for example, the data is set to 64 bytes in advance, and the data writing process Include the following steps:

Step 101, the host CPU issues a write data instruction;

Step 102, the host CPU judges the data type based on the byte-variable file system, that is, judges whether the data to be written is metadata, log of the file system, or user data user data, thereby determining the process of writing data later ;

Step 103, if it is metadata and log, it will be directly written into the first PCM;

Step 104, if it is user data User data, it is necessary to further determine the size of the data;

Step 105, judging whether the data is greater than 64Byte, the judging size is set by the file system according to the situation, assuming that the granularity of the file system is set to 64Byte;

Step 106, if it is greater than 64Byte, it is considered as big data, and the host CPU sends the write data request to the peripheral memory CPU, and the peripheral memory CPU writes the data into the NAND Flash/HDD;

Step 107, if it is less than 64Byte, it is considered as small data, but before writing, in order to ensure data consistency, the original data must be searched;

Step 108, judging whether the original data can be found in the first PCM;

Step 109, if the original data can be found in the first PCM, then directly update the original data at the storage location of the original data;

Step 110, if not found, you need to look for it in the NAND Flash of the peripheral memory;

Step 111, judging whether the original data can be found in the NAND Flash of the peripheral memory;

Step 112, if the original data cannot be found in the NAND Flash of the peripheral memory, then think that this data is new data, write new small data in the first PCM;

Step 113, if the original data can be found in the NAND Flash of the peripheral memory, then it is considered that the old data is updated, and the old data needs to be read into the first PCM, and then the data in the NAND Flash of the peripheral memory is marked as dirty data, and the external It is assumed that the NAND Flash of the memory is erased when it is idle, and at the same time, the migration of hot data is realized during the moving process. If the data is updated next time, it can be directly hit in the first PCM.

In the data storage method provided by the embodiment of the present invention, since the read performance of PCM itself is more than 100 times that of NANDFlash, when writing to PCM, it is not necessary to read and then modify in DRAMBuffer like NAND Flash, so the embodiment of the present invention realizes Small data optimization, small data read or write acceleration; currently the latest 20nm MLC NAND Flash write life is only a few thousand times, the write life of PCM is more than 100-1000 times that of NAND, and the frequently updated small data will be stored in PCM Medium operation can write and absorb small data to NAND Flash, which greatly prolongs the writing life of NAND Flash in the storage system; PCM bytes are variable, and NAND Flash operates according to the page page. When small data is written, the data size is much larger. Smaller than the page (2-4K) size of NAND Flash, using PCM can reduce the load payload of the file system and speed up the operation of the file system, thus reducing the load of the file system and improving the operating efficiency of the system.

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above method embodiments can be completed by program instructions and related hardware. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above-mentioned method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other various media that can store program codes.

FIG. 7 is a schematic structural diagram of Embodiment 1 of the PCM bridge provided by the embodiment of the present invention. As shown in FIG. 7, the PCM bridge includes: a receiving unit 20, a converting unit 21 and a reading or writing unit 22, wherein,

The receiving unit 20 is used to receive the non-volatile small data stored in the phase change memory PCM connected to the PCM bridge from the CPU connected to the memory controller through the memory controller connected to the PCM bridge. The first operation signal of .

The conversion unit 21 is used for converting the first operation signal received by the receiving unit into a second operation signal capable of reading or writing the PCM.

The read or write unit 22 is used for reading small data in the PCM or writing small data in the PCM according to the second operation signal converted by the conversion unit.

Among them, small data is small data that is often read or written. Small data can be small user data, or metadata, or any one or more of system log data. Small data can also be smaller than general flash operations. When the block operation data, the size of the small data is less than or equal to 512 bytes, which can be determined according to different situations, and this embodiment does not limit it. The first operation signal includes a read or write signal, and converting the first operation signal into a second operation signal capable of reading or writing the PCM to read or write the small data in the PCM through the second operation signal includes: converting the read or write signal to the PCM The write signal is converted into a read or write signal capable of reading or writing to the PCM so as to read or write small data in the PCM through the read or write signal.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (18)

1. A data storage system, comprising:

the phase change memory comprises a processor, a memory controller, a phase change memory PCM bridge and a phase change memory PCM;

the processor is connected with the PCM bridge through the memory controller, and the PCM bridge is connected with the PCM;

the PCM is used for storing nonvolatile small data;

the PCM bridge is used for receiving a first operation signal for reading or writing small data from the CPU through the memory controller, converting the first operation signal into a second operation signal capable of reading or writing the PCM so as to read or write small data in the PCM through the second operation signal.

2. The data storage system of claim 1, wherein:

the PCM is particularly used to store nonvolatile small data that is read or written frequently.

3. The data storage system of claim 1 or 2, wherein:

the first operation signal comprises a read or write signal, and the converting the first operation signal into a second operation signal capable of reading or writing the PCM to read or write small data in the PCM through the second operation signal comprises:

converting the read or write signal into a read or write signal capable of reading or writing the PCM to read or write small data in the PCM by the read or write signal.

4. The data storage system of any of claims 1-3, wherein the PCM bridge is further configured to:

receiving, by the memory controller, an adjustment signal from the CPU for adjusting a storage location of the small data stored by the PCM, the adjusting the storage location of the small data stored by the PCM comprising: shifting out the small data stored by the PCM, which are used less frequently, from the PCM memory or shifting the small data, which are used more frequently, to the PCM memory;

converting the adjustment signal into an adjustment signal capable of reading or writing the PCM to adjust a storage location of the small data in the PCM by the adjustment signal.

5. The data storage system of any of claims 1-4, further comprising:

and the memory is connected with the processor through the memory controller and is used for storing data required by the CPU when executing programs.

6. The data storage system of any of claims 1-5, further comprising:

the peripheral memory is used for being connected with the CPU through a peripheral interface;

the peripheral memory stores nonvolatile big data, and the CPU is also used for reading or writing the peripheral memory through the peripheral interface, wherein the big data is data larger than the small data.

7. The data storage system of any of claims 1-6, wherein:

the small data is any one or more of small user data, metadata or system log data.

8. The data storage system of any of claims 1-7, wherein:

the small data is block operation data with the size smaller than that of the general flash operation.

9. The data storage system of any of claims 1-8, wherein:

the small data byte size is less than or equal to 512 bytes.

10. A data storage method is applied to a phase change memory PCM bridge and comprises the following steps:

receiving, by a memory controller connected to the PCM bridge, a first operation signal for reading or writing non-volatile small data stored in a phase change memory PCM connected to the PCM bridge from a CPU connected to the memory controller;

converting the first operation signal into a second operation signal capable of reading or writing the PCM to read or write small data in the PCM by the second operation signal.

11. The data storage method of claim 10, wherein:

the small data is small data that is read or written frequently.

12. The data storage method according to claim 10 or 11, wherein:

the first operation signal comprises a read or write signal, and the converting the first operation signal into a second operation signal capable of reading or writing the PCM to read or write small data in the PCM through the second operation signal comprises:

converting the read or write signal into a read or write signal capable of reading or writing the PCM to read or write small data in the PCM by the read or write signal.

13. The data storage method of any of claims 10-12, further comprising:

receiving, by the memory controller, an adjustment signal from the CPU for adjusting a storage location of the small data stored by the PCM, the adjusting the storage location of the small data stored by the PCM comprising: shifting out the small data stored by the PCM, which are used less frequently, from the PCM memory or shifting the small data, which are used more frequently, to the PCM memory;

converting the adjustment signal into an adjustment signal capable of reading or writing the PCM to adjust a storage location of the small data in the PCM by the adjustment signal.

14. A data storage method according to any one of claims 10 to 13, wherein:

the small data is any one or more of user data with small size, or metadata, or system log data; or,

the small data is block operation data with the size smaller than that of the general flash operation; or,

the small data byte size is less than or equal to 512 bytes.

15. A PCM bridge, comprising:

a receiving unit, configured to receive, by a memory controller connected to the PCM bridge, a first operation signal from a CPU connected to the memory controller, the first operation signal being used to read or write small nonvolatile data stored in a phase change memory PCM connected to the PCM bridge;

a conversion unit configured to convert the first operation signal received by the reception unit into a second operation signal capable of reading or writing the PCM;

and the reading or writing unit is used for reading small data in the PCM or writing small data into the PCM according to the second operation signal converted by the conversion unit.

16. A PCM bridge according to claim 15, wherein:

the small data is small data that is read or written frequently.

17. A PCM bridge according to claim 15 or 16, wherein:

the first operation signal comprises a read or write signal, and the conversion unit is specifically used for converting the read or write signal into a read or write signal capable of reading or writing the PCM so as to read or write small data in the PCM through the read or write signal.

18. A PCM bridge according to any of claims 15-17, wherein:

the small data is any one or more of small user data, metadata or system log data; or,

the small data is block operation data with the size smaller than that of the general flash operation; or

The small data byte size is less than or equal to 512 bytes.

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