CN105187342A - Three-tap decision feedback equalizer having low power dissipation and used for receiving end of high-speed serial interface - Google Patents

Abstract

The invention belongs to the technical field of data transmission, and in particular relates to a low-power consumption 3-tap decision feedback equalizer for a high-speed serial interface receiving end, which includes two data paths with the same structure, namely an odd data path and an even data path; each A data path includes a gain stage, an offset cancellation unit, a dynamic combining summer, a dynamic latching summer, a buffer, a dynamic feedback stage, and a splitter; The gain stages and offset elimination units in the odd and even data paths form the equalized front end; the dynamic latch summers, dynamic feedback stages, and buffers in the odd and even data paths form the first tap loop; the odd and even data paths The second and third tap loops are composed of a dynamic combiner, summer, and splitter; the summing unit of the entire 3-tap module is clock-controlled. The invention has the characteristics of low power consumption, high working speed and strong balancing ability.

Description

Low Power 3-Tap Decision Feedback Equalizer for High-Speed Serial Interface Receiver

technical field

The invention belongs to the technical field of data transmission, and in particular relates to a low-power consumption 3-tap decision feedback equalizer used for a high-speed serial interface receiving end.

Background technique

In recent years, the data rate transmitted by high-speed serial port transceivers has been rising continuously. At present, the data rate of a single channel has reached more than 40Gbps. Under such a high data rate, the channel will seriously attenuate the signal. At this time, the design of the receiver is faced with Serious ISI problem. Commonly used equalizers mainly include a continuous time linear equalizer (ContinuousTimeLinearEqualizer, CTLE) and a decision feedback equalizer (DecisionFeedbackEqualizer, DFE). The decision feedback equalizer is widely used in the design of the receiving end of the high-speed serial interface. The decision feedback equalizer is placed at the front end of the receiver, and the serial data from the channel is compensated in the time domain to eliminate its Inter-Symbol Interference (ISI). Make sure the receiver is working correctly. The decision feedback equalizer is a nonlinear equalizer, which can provide a smaller bit error rate (BitErrorRates, BER) than the general linear equalizer. The linear equalizer also amplifies the noise while reducing the ISI, and the decision feedback An equalizer can eliminate ISI without introducing noise gain.

The design of the multi-tap direct decision feedback equalizer is mainly limited by the timing of the critical path of the first tap. The principle of 1-tap decision feedback equalizer to eliminate ISI is to complete the previous 1 bit within the unit data cycle (UnitInterval, UI). (bit) data judgment and send it back to the summation unit, eliminating the ISI of the current bit data. Figure 1 is a schematic diagram of a typical 1-tap direct decision feedback equalizer. The input analog signals of odd channels are judged by triggers as digital signals and fed back to the transconductance summation unit of even channels, thereby eliminating the first postcursor (1 ^st postcursor, post1) ISI. The timing constraints for the entire critical path are limited by Equation (1):

T _ckq +T _settle +T _setup <1UI(1)

Among them, T _ckq and T _setup represent the propagation delay and setup time of the flip-flop respectively, and T _settle represents the stabilization time of the analog summing node. If timing optimization is not performed on critical paths, T _ckq +T _settle +T _setup can easily exceed 1UI at a data rate of 40Gbps.

In order to solve the tight timing problem of the critical path of the first tap, a method is shown in Figure 2, using the speculative structure to design the first tap, at this time the timing of the new loop is:

T _ckq +T _s,MX +T _setup <1UI(2)

Among them, T _ckq and T _setup respectively represent the propagation delay and setup time of the flip-flop, and T _s,MX represent the digital signal propagation delay of the data selector, usually T _s,MX is smaller than T _settle . Although this speculative structural design can relax the timing requirements for the first tap critical path, it is not conducive to the design of the second and subsequent tap loops. The reason is that the data selector will introduce a large amount of load and add additional time delays. , on the other hand, the number of data selectors will increase exponentially with the number of taps.

As the data rate increases, the power consumption-data rate trade-off at the receiving end of the high-speed serial interface becomes very tense.

Contents of the invention

In order to overcome the above-mentioned shortcoming of the prior art, the object of the present invention is to provide a kind of low power consumption 3 tap decision feedback equalizers for the high-speed serial interface receiving end, it is characterized in that: comprise the odd data path of two identical structures and even datapaths; each datapath includes a gain stage, an offset cancellation unit, a dynamic combining summer, a dynamic latching summer, a buffer, a dynamic feedback stage, and 1 splitter;

The gain stage and the offset elimination unit in the odd data path and the even data path form the equalization front end, and the offset elimination unit is placed between the gain stage output terminal and the ground, and the gain stage output terminals of the odd data path and the even data path are respectively connected to the odd data path The input ends of the dynamic combination summer of the road and the even data path, the output ends of the dynamic combination summer of the odd data path and the even data path are respectively connected to the dynamic latches of the odd data path and the even data path in the first tap loop summer input;

The first tap loop is realized by merging the first tap of the odd data path and the first tap of the even data path, and the first tap of the odd data path is connected to the dynamic latch solution of the odd data path by the output end of the dynamic feedback stage of the even data path The output end of the summator and the output end of the dynamic latch summator of the odd data path are connected to the buffer input end of the odd data path, and the first tap of the even data path is connected to the output end of the dynamic feedback stage of the odd data path to the even The output end of the dynamic latch summer of the data path and the output end of the dynamic latch summer of the even data path are connected to the buffer input end of the even data path, and the buffer output ends of the odd data path and the even data path are respectively connected to Splitter inputs to odd and even data paths;

The splitter of the even data path reduces the speed of the even path data to two paths of 1/4 rate data, and transmits it to the dynamic combiner and summer of the even data path and the odd data path from the output end of the even data path splitter The input end constitutes the 2nd tap of the even data path and the 3rd tap of the odd data path respectively. The output end transmits it to the input end of the dynamic combination summer of the odd data path and the even data path, respectively forming the second tap of the odd data path and the third tap of the even data path; the second tap loop is composed of the even data path The 2nd tap is combined with the 2nd tap of the odd data path, and the 3rd tap loop is realized by merging the 3rd tap of the even data path and the 3rd tap of the odd data path; the summing unit of the entire 3-tap module is realized by clock control Way.

In the first tap loop, the dynamic latch summers of the odd data path and the even data path are respectively controlled by a pair of 1/2 rate complementary clocks to switch between summation and latch states; in 2. In the 3-tap loop, the splitters of the odd data path and the even data path are controlled by two clocks respectively, and these four clocks are shared by the dynamic combiner and summer.

Both the gain stage and the offset elimination unit use a current mode logic circuit.

The dynamic latch summator is implemented by combining the summator and the dynamic latch, and includes a first NMOS transistor M0 that acts as a tail current source controlled by the positive edge clock CLKP, and a pair of second NMOS transistors driven by input data. NMOS transistor M1, third NMOS transistor M2, a pair of first PMOS transistor M3 and second PMOS transistor M4 controlled by negative edge clock CLKN, and a pull-up third PMOS transistor M6 controlled by positive edge clock CLKP; The source of a PMOS transistor M3 is connected to the power supply VDD, the drain thereof is connected to the drain of the second NMOS transistor M1, the drain of the third NMOS transistor M2 is connected to the drain of the second PMOS transistor M4, and the drain of the second PMOS transistor M4 The source of the first NMOS transistor M0 is connected to the power supply VDD, the source of the third PMOS transistor M6 is connected to the power supply VDD, the source of the first NMOS transistor M0 is grounded; the source of the second NMOS transistor M1, the source of the third NMOS transistor M2, the third NMOS transistor M2 The drains of the three PMOS transistor M6 and the drain of the first NMOS transistor M0 are connected to the third node VP; the first node VA is at the junction of the drain of the third NMOS transistor M2 and the drain of the second PMOS transistor M4, and One node VA is connected to the differential data positive output terminal OUTP; the second node VB is at the connection between the drain of the first PMOS transistor M3 and the drain of the second NMOS transistor M1, and the second node VB is connected to the differential data negative output terminal OUTN ; The gates of the first PMOS transistor M3 and the second PMOS transistor M4 are connected to the negative edge clock CLKN, the gate of the second NMOS transistor M1 is connected to the differential data positive input terminal INP, and the gate of the third NMOS transistor M2 is connected to the differential The data negative input terminal INN, the gates of the first NMOS transistor M0 and the third PMOS transistor M6 are connected to the positive edge clock CLKP.

The buffers employ current mode logic circuits.

The even data path splitter is controlled by a pair of 1/4 rate differential clocks: the first differential clock CKE10 and the second differential clock CKEX10, and the odd data path splitter is controlled by a pair of 1/4 rate differential clocks: the second The three differential clocks CKO10 and the fourth differential clock CKOX10 are controlled; the first differential clock CKE10 , the third differential clock CKO10 , the second differential clock CKEX10 , and the fourth differential clock CKOX10 have a phase difference of 90 degrees in sequence.

The dynamic combiner and summator is implemented by embedding a combiner into a summation unit, including 2 pairs of differential clock input terminals, 4 pairs of differential data input terminals and 1 pair of differential data output terminals.

Beneficial effect

Compared with the prior art, the decision feedback equalizer proposed by the present invention can ensure that the timing of the first tap loop is sufficient, the feedback of the second and third taps is realized at a quarter rate, and all tap summation units are clock control mode, the equalizer is implemented in a dynamic way, and the structure of 3 taps has the characteristics of low power consumption, high working speed and strong equalization ability.

Description of drawings

FIG. 1 is a schematic diagram of a typical 1-tap direct decision feedback equalizer.

Fig. 2 is a schematic structural diagram of a typical 1-tap speculative decision feedback equalizer.

Figures 3a-3b are schematic diagrams of a typical 1-tap direct decision feedback equalizer in which the summing unit is merged with the master latch, and the slave latch is merged with the feedback stage.

Fig. 4 is a schematic structural diagram of a 1-tap direct decision feedback receiver in the present invention.

Fig. 5 is a schematic diagram of the implementation of the second and third tap circuits in the present invention.

FIG. 6 is a schematic structural diagram of a low-power consumption 3-tap decision feedback equalizer for a high-speed serial interface receiving end of the present invention.

Fig. 7 is a dynamic latch summer circuit in the present invention.

Fig. 8 is a circuit diagram of a splitter in the present invention.

Fig. 9 is a circuit diagram of a dynamic combination summer in the present invention.

Figure 10 is an eye diagram of the input data.

Fig. 11 is an eye diagram of the output data of the even data path.

Detailed ways

The preferred embodiments will be described in detail below in conjunction with the accompanying drawings and embodiments.

In order to solve the tight timing problem of the first tap loop, a circuit structure of "dynamic latch summer" and "dynamic feedback stage" is proposed, which can significantly reduce power consumption while meeting the timing requirements of the critical path. As shown in Figure 3a~3b, the summation unit of the typical 1-tap direct decision feedback equalizer in Figure 1 is combined with the master latch, and the slave latch is combined with the feedback stage to make the "summation stable" process Simultaneously with the "signal amplification" process. The unit after combining the summation unit and the master latch is called a "dynamic latch summer", and the unit after the combination of the slave latch and the feedback stage is called a "dynamic feedback stage". Summer", "Dynamic Feedback Stage", the timing requirements of the critical path can be reduced to:

T _dq <1UI(3)

Here, T _dq represents the propagation delay of the "dynamic latch summer", and its size is almost as large as the setup time T _setup of the flip-flop. After this step of optimization, the timing of the critical path is largely relaxed, and the optimized first tap loop is shown in Figure 3b. Since the "Dynamic Latch Summer" needs to drive the "Dynamic Feedback Stage", the shunt and the parasitic capacitance between the lines, its load is equivalent to the minimum size inverter with a fan-out of 4, so in the "Dynamic Latch Summation A first-level buffer is added behind the "device" to enhance its driving effect. The structure diagram of the entire 1-tap direct decision feedback equalizer is shown in Figure 4.

The 2nd and 3rd tap loops are proposed to be realized by adopting the "splitting-combining" structural form of the splitter and the "dynamic combining and summing device", which significantly reduces power consumption. Its implementation is as follows: As shown in Figure 5, the 1/2 data rate odd and even two channels of data D_O, D_E generate 4 channels of 1/4 data rate after passing through the splitter under the control of clocks CKE10, CKEX10, CKO10, and CKOX10 The data D00, D01, D0, and D03 of the 4-way 1/4 rate data are combined and summed through the "dynamic combiner and summator" under the control of the clock CKE10, CKEX10, CKO10, and CKOX10 .

Figure 6 shows the circuit structure of the decision feedback equalizer proposed by the present invention, including two data paths with the same structure, followed by an odd data path and an even data path; each data path includes a gain-enhancing stage and an offset elimination unit, a dynamic combining summer, a dynamic latching summer, a dynamic feedback stage, a buffer, and a splitter.

The gain stages and offset elimination units in the odd and even data paths form the equalized front end; the dynamic latch summers, dynamic feedback stages, and buffers in the odd and even data paths form the first tap loop; the odd and even data paths A dynamic combiner, summer, and splitter form the second and third tap loops;

The gain stage of the equalization front end includes a differential input terminal and a differential output terminal; the differential input terminal is used to receive the channel-attenuated data signal Din, and the differential output terminal transmits the amplified data signal to the output terminal of the offset cancellation unit and thereafter The input terminal of the dynamic combination summer;

In the first tap loop, the output end of the dynamic latch summer of the even data path is connected to the buffer input end of the even data path, the output end of the dynamic feedback stage of the odd data path, and shares the clock CK20 with the dynamic feedback stage of the odd data path, The first tap that constitutes the even data path; and the output end of the even data path buffer is connected to the dynamic latch summator output end of the odd data path to connect the odd data path buffer input end, the even data path dynamic feedback stage output end, and The clock CKX20 is shared with the dynamic feedback stage of the even data path to form the first tap of the even data path; the first taps of the odd and even data paths are controlled by a pair of 1/2 rate complementary clocks CKX20 and CK20 respectively, so that the odd and even The dynamic latching summer switches between latching and summing states respectively;

Fig. 7 is a schematic diagram of a dynamic latch adder circuit in odd and even data paths. The dynamic latch summator adopted in the present invention is realized by the dynamic latch of band pull-up PMOS transistor, comprises an NMOS transistor M0 that plays the role of tail current source controlled by positive edge clock CLKP, a pair of NMOS transistor M0 driven by input data NMOS transistors M1 and M2, a pair of PMOS load transistors M3 and M4 controlled by the negative edge clock CLKN, and a pull-up PMOS transistor M6 controlled by CLKP; when CLKP is high, the dynamic latch summer executes the summation And function, when CLKN is high level, the dynamic latch summator performs the latch function;

In the 2nd and 3rd tap loops, the input end of the splitter receives the data from the output end of the buffer, and the even data path splitter reduces the speed of the even data D_E to two 1/4 rate data of D00 and D02, and the output send it to the input end of the dynamic combiner and summer of the even data path and the odd data path to form the 2nd tap of the even data path and the 3rd tap of the odd data path respectively; The data D_O is decelerated into two channels of 1/4 rate data of D01 and D03, and is transmitted from the output terminal to the input terminal of the dynamic combination summer of the odd data channel and the even data channel, respectively forming the second channel of the odd data channel. Tap and the third tap of the even data path; the splitter of the even data path is controlled by a pair of 1/4 rate differential clocks CKE10 and CKEX10, and the splitter of the odd data path is controlled by a pair of 1/4 rate differential clocks CKO10 and CKOX10 Control, CKE10, CKO10, CKEX10, CKOX10 have a phase difference of 90 degrees in turn;

Fig. 8 is a circuit diagram of a splitter in the odd and even data paths, the circuit is composed of two parts, the front-stage sampling switch and the rear-stage positive feedback pair. The sampling switch is controlled by a pair of complementary clocks CK10 and CKX10 at a rate of 1/4, and alternately samples the data of the odd data path or even data path at a rate of 1/2 to realize the branching function. The positive feedback pair is controlled by the same pair of 1/4 rate complementary clocks CK10 and CKX10. In each channel, the clock of the sampling switch is complementary to the clock of the positive feedback pair to ensure that the positive feedback pair The data signal can be amplified, and the degree of data signal amplification is controlled by the positive feedback to the bias voltage BIAS of the tail current source.

Fig. 9 is a circuit diagram of a dynamic combination summer in odd and even data paths, and the dynamic combination and summer circuit is realized by four dynamic summing units with the same structure. Take the combined summation of the second tap as an example, two identical dynamic summation units are controlled by a pair of 1/4 rate complementary clocks CKE10 and CKEX10, when CKE10 and CKEX10 are alternately high, the summation unit will be in the future The 1/4 rate data from the splitter is combined, and the combined sum of the third tap is exactly the same as that of the second tap. The summing weights of the second tap and the third tap are respectively controlled by the bias voltages Tap2_B and TAP3_B of the tail current source transistors of the summing unit.

Figure 10 and Figure 11 are eye diagram comparisons of input and output data, respectively. When PRBS31 data with a data rate of 40Gbps passes through a channel that attenuates the signal by 22dB at the Nyquist frequency (20GHz), it is input into the system shown in Figure 1, and the eye diagram of the input data is shown in Figure 10. It can be seen that the eyes are almost completely closed; the eye diagram in Figure 11 is the even data path output data eye diagram of the DFE shown in Figure 6, and the equalization effect of the DFE can be clearly seen from the comparison of the left and right diagrams.

Compared with the existing technology, the present invention adopts the CML structure realization of the gain stage and the offset elimination unit, and the other parts are realized by clock control. This dynamic processing method can significantly reduce the power consumption of the decision feedback equalizer.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (7)

1. for a low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal, it is characterized in that: comprise the identical data path odd data road of two-strip structure and even data road; Every bar data path comprises 1 gain stage, unit, 1 dynamic conjunction road summer, 1 dynamic latch summer, 1 buffer, 1 dynamical feedback level and 1 splitter are eliminated in 1 imbalance;

Gain stage in odd data road and even data road and imbalance are eliminated unit and are formed balanced front end, imbalance is eliminated unit and is placed between gain stage output and ground, the gain stage output on odd data road and even data road is connected respectively to the dynamic conjunction road summer input on odd data road and even data road, and the dynamic conjunction road summer output on odd data road and even data road is connected respectively to the dynamic latch summer input on odd data road and even data road in the 1st tap loop;

1st tap loop is merged by the 1st tap on odd data road and the 1st tap on even data road and realizes, form after the dynamic latch summer output of dynamic latch summer output and odd data road that the 1st tap on odd data road is connected to odd data road by the dynamical feedback level output on even data road is connected to the buffer input on odd data road, the buffer input that the dynamic latch summer output of dynamic latch summer output and even data road that the 1st tap on even data road is connected to even data road by the dynamical feedback level output on odd data road is connected to even data road is formed, the buffer output end on odd data road and even data road is connected respectively to the splitter input on odd data road and even data road,

Even circuit-switched data reduction of speed is two-way 1/4 speed data by the splitter on even data road, and the dynamic conjunction road summer input on even data road and odd data road is sent to by even data road splitter output, form the 2nd tap on even data road and the 3rd tap on odd data road respectively, strange circuit-switched data reduction of speed is two-way 1/4 speed data by odd data road splitter, and be sent to by odd data road splitter output the input that road summer is dynamically closed on odd data road and even data road, form the 2nd tap on odd data road and the 3rd tap on even data road respectively; 2nd tap loop is merged by the 2nd tap on even data road and the 2nd tap on odd data road and realizes, and the 3rd tap loop is merged by the 3rd tap on even data road and the 3rd tap on odd data road and realizes; The sum unit of whole 3 tap modules is clock implementation.

2. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, it is characterized in that, the dynamic latch summer on described odd data road and even data road is all controlled respectively by the complementary clock of a pair 1/2 speed, makes it switch between summation and latch mode; The splitter on described odd data road and even data road respectively has two clock controls, and these four clocks are dynamically closed road summer shares.

3. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, is characterized in that, described gain stage and imbalance are eliminated unit and all adopted current mode logic circuit.

4. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, it is characterized in that, described dynamic latch summer is merged by summer and dynamic latch and realizes, comprise one by the first NMOS tube (M0) just having controlled tail current source effect along clock (CLKP), a pair by the second NMOS tube (M1) and the 3rd NMOS tube (M2) that input data-driven, the first PMOS (M3) controlled by negative edge clock (CLKN) for a pair and the second PMOS (M4), also has one by the pull-up the 3rd PMOS (M6) just controlled along clock (CLKP), the source electrode of the first PMOS (M3) is connected with power supply (VDD), its drain electrode is connected to the drain electrode of the second NMOS tube (M1), the drain electrode of the 3rd NMOS tube (M2) is connected to the drain electrode of the second PMOS (M4), the source electrode of the second PMOS (M4) is connected to power vd D, the source electrode of the 3rd PMOS (M6) is connected to power vd D, the source ground of the first NMOS tube (M0), the source electrode of the second NMOS tube (M1), the source electrode of the 3rd NMOS tube (M2), the drain electrode of the 3rd PMOS (M6) and the drain electrode of the first NMOS tube (M0) are connected to the 3rd node (VP), first node (VA) is on the connecting line of the drain electrode of the 3rd NMOS tube (M2) and the drain electrode of the second PMOS (M4), and first node (VA) is connected to differential data positive output end (OUTP), Section Point (VB) is on the connecting line of the drain electrode of the first PMOS (M3) and the drain electrode of the second NMOS tube (M1), and Section Point (VB) is connected to differential data negative output terminal (OUTN), the grid of the first PMOS (M3) and the second PMOS (M4) is connected to negative edge clock (CLKN), the grid of the second NMOS tube (M1) is connected to differential data positive input terminal (INP), the grid of the 3rd NMOS tube (M2) is connected to differential data negative input end (INN), and the grid of the first NMOS tube (M0) and the 3rd PMOS (M6) is connected to just along clock (CLKP).

5. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, is characterized in that, described buffer adopts current mode logic circuit.

6. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, it is characterized in that, described even data road splitter is by a pair 1/4 speed difference quadrature clocks: the first differential clocks (CKE10) and the second differential clocks (CKEX10) control, and described odd data road splitter is by a pair 1/4 speed difference quadrature clocks: the 3rd differential clocks (CKO10) and the 4th differential clocks (CKOX10) control; First differential clocks (CKE10), the 3rd differential clocks (CKO10), the second differential clocks (CKEX10), the 4th differential clocks (CKOX10) differ 90 degree of phase places successively.

7. the low-power consumption 3 tap DFF for HSSI High-Speed Serial Interface receiving terminal according to claim 1, it is characterized in that, described dynamic conjunction road summer embeds sum unit by mixer and realizes, comprise 2 pairs of differential clocks inputs, 4 pairs of differential data input terminal and 1 pair of differential data output.