CN105185713A - HKMG device preparation method - Google Patents

Abstract

The invention discloses an HKMG device preparation method. The method comprises the steps of 1, providing a semiconductor substrate; 2, successively depositing thick gate oxide, amorphous carbon and a silicon dioxide film on the semiconductor substrate, and depositing polycrystalline silicon on the silicon dioxide film; 3, performing the patterning treatment on the polycrystalline silicon to form an isolating layer on the polycrystalline silicon out of a region for grid formation, and forming an etching stop layer among the isolating layer, the semiconductor substrate and the grid region; 4, etching to remove the polycrystalline silicon in the grid region; 5, stripping to remove the silicon dioxide film and the amorphous carbon that remain in the grid region; 6, filling a high-k dielectric layer and the metal grid material in the grid region. According to the technical scheme of the invention, the thick gate oxide, the amorphous carbon and the silicon dioxide film can be directly applied in existing equipment, so that no extra equipment investment is required. Meanwhile, the problems of pollution and thermal instability are avoided.

Description

A kind of preparation method of HKMG device

technical field

The invention relates to the field of integrated circuit manufacturing, in particular to a preparation method of an HKMG (high-k gate insulating layer+metal gate) device.

Background technique

With the rapid development of VLSI technology, the size of MOSFET devices is continuously reduced, which usually includes: the reduction of the channel length of MOSFET devices, the thinning of gate oxide layer thickness, etc. to obtain faster device speed. However, when it develops to the ultra-deep submicron level, especially when the technology node is 45nm and below, it can no longer bear the high leakage caused by the continuous reduction of the gate oxide thickness. The industry has introduced the design of high-k gate insulating layer and metal gate in the process of 45nm and below. After 28nm, due to the thermal stability of high-k (high dielectric value) materials, HKMG (high-k Gate-last process of gate insulating layer + metal gate).

The existing technology utilizes redundant polysilicon forming technology well-known in the industry to prepare HKMG devices. The specific process is shown in Figures 1-4, and the steps include:

First, grow a thick layer of gate oxide 2 on the semiconductor substrate 1;

Next, the polysilicon layer 3 is grown in a normal process, and the polysilicon layer 3 is patterned to form an isolation layer 4 on the polysilicon layer 3 except for the gate area to be formed, as shown in FIG. 2 .

Next, as shown in FIG. 3 , the redundant polysilicon layer 3 in the gate region is etched by dry method, and the thick gate oxide 2 is used as the cut-off layer. Since the HKMG device has high requirements on the thickness of the thick gate oxide 2, this requires that the etching selection ratio of polysilicon and silicon dioxide must reach 1:100 or even higher. Therefore, the etching adjustment and control of the polysilicon layer 3 in this step very difficult. In addition, there is also a combination of dry etching and wet etching, but dry etching has extremely high requirements on the stability of the machine. At the same time, wet etching also needs to maintain a lot of over-etching to ensure that there is no residue, and the loss of the bottom thick gate oxide 2 is relatively large.

Finally, as shown in FIG. 4 , the thick gate oxide 2 is patterned and stripped according to the normal flow, an initial oxide layer is grown and a high-k material 5 is deposited and a metal gate material 6 is filled.

It can be seen that the above-mentioned process has extremely high requirements on the precision control of the etching process. A slight over-etching will affect the thickness of the initial oxide film and the surface flatness of the silicon substrate in the channel region. extremely small.

Contents of the invention

The invention provides a method for preparing HKMG devices to solve the above-mentioned technical problems in the prior art.

In order to solve the above-mentioned technical problems, the invention provides a kind of preparation method of HKMG device, comprising:

Step 1: providing a semiconductor substrate;

Step 2: sequentially depositing thick gate oxide, amorphous carbon and silicon dioxide films on the semiconductor substrate, and depositing polysilicon on the silicon dioxide film;

Step 3: Patterning the polysilicon to form an isolation layer outside the area where the gate is to be formed on the polysilicon, and an etching stop layer is formed between the isolation layer and the semiconductor substrate and the gate area ;

Step 4: Etching and removing the polysilicon in the gate region;

Step 5: stripping and removing the remaining silicon dioxide film and amorphous carbon in the gate area;

Step 6: filling the gate region with a high-k dielectric layer and metal gate material.

Preferably, in the step 2, the amorphous carbon is formed on the thick gate oxide by chemical vapor deposition, and a silicon dioxide film is deposited on the amorphous carbon by atomic position deposition.

Preferably, the thickness of the amorphous carbon is 50-200 angstroms, and the thickness of the silicon dioxide film is 20-100 angstroms.

As preferably, said step 3 includes:

Step 31: Coating photoresist on the polysilicon area where the gate is to be formed;

Step 32: using the photoresist as a mask and the semiconductor substrate as a cut-off layer, etching the polysilicon, silicon dioxide film, amorphous carbon and thick gate oxide outside the gate region to form a groove;

Step 33: forming an etching stop layer on the semiconductor substrate in the groove and on the edge of the groove, and filling the groove with an insulating material to form an isolation layer.

Preferably, in step 5, a dry etching process is used to remove the remaining silicon dioxide film and amorphous carbon.

Preferably, when forming the core low-voltage device, the step 6 includes: stripping and removing the thick gate oxide, and sequentially depositing an initial oxide layer on the semiconductor substrate, and sequentially filling a high-k dielectric layer on the initial oxide layer , work function metal layer and metal gate material.

Preferably, when forming the IO device, the step 6 includes: sequentially filling a high-k dielectric layer, a work function metal layer and a metal gate material on the thick gate oxide.

Preferably, aluminum is used as the metal gate material, and silicon dioxide is used as the thick gate oxide.

Preferably, in step 4, the polysilicon layer in the gate region is removed by a dry etching process.

Compared with the prior art, the present invention has the following advantages:

1. The present invention forms an oxygen (thick gate oxygen)-amorphous carbon-oxygen (silicon dioxide film) composite film on a semiconductor substrate, and the deposition of each layer can be directly carried out in existing equipment without additional equipment input, and oxygen-amorphous carbon-oxygen belongs to the previous standard material, so there is no need to worry about pollution or thermal stability issues;

2. In the step of etching polysilicon, the etching stops on the uppermost silicon dioxide film. Since the uppermost silicon dioxide film is a sacrificial layer, the etching selectivity ratio of polysilicon and silicon dioxide is allowed to be as low as 1:10, compared to In the prior art, the etching of the present invention is easy to adjust and control, and is easier for large-scale production;

3. When peeling off the remaining small amount of the uppermost silicon dioxide film and amorphous carbon, the influence on the thickness of the bottom layer of the thick gate oxide is small and the difference is fixed. Generally, the film thickness loss of the thick gate oxide is within 2A, which can effectively improve the stability of the device sex;

4. In the oxygen-amorphous carbon-oxygen combination film of the present invention, the uppermost layer of silicon dioxide film is used as a sacrificial layer for dry etching, and the middle layer of amorphous carbon film is used to protect the lowest layer of thick gate oxide;

5. The preparation method of the HKMG device of the present invention first dry-etches the polysilicon, and stops on the uppermost silicon dioxide film. Then dry stripping a small amount of the uppermost silicon dioxide film and the middle amorphous carbon film can protect the process of polysilicon stripping.

Description of drawings

Fig. 1 is the device schematic diagram after depositing polysilicon in the preparation method of existing HKMG device;

Fig. 2 is the schematic diagram of the device after forming the isolation layer in the preparation method of the existing HKMG device;

Fig. 3 is the device schematic diagram after etching polysilicon in the preparation method of existing HKMG device;

Fig. 4 is the device schematic diagram after forming HKMG device in the preparation method of existing HKMG device;

Fig. 5 is the device schematic diagram after depositing polysilicon in the preparation method of HKMG device of the present invention;

6 is a schematic diagram of the device after forming an isolation layer in the preparation method of the HKMG device of the present invention;

7 is a schematic diagram of the device after etching and removing polysilicon and part of the silicon dioxide film in the preparation method of the HKMG device of the present invention;

8 is a schematic diagram of the device after removing the remaining silicon dioxide film and amorphous carbon in the preparation method of the HKMG device of the present invention;

FIG. 9 is a schematic diagram of the HKMG device formed in the method for preparing the HKMG device of the present invention.

detailed description

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that all the drawings of the present invention are in simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

As shown in Fig. 5 to Fig. 9, a kind of preparation method of HKMG device of the present invention specifically comprises the following steps:

Step 1: Provide a semiconductor substrate 10, which is usually a silicon substrate.

Step 2: Deposit thick gate oxide 20 , amorphous carbon 30 and silicon dioxide film 40 sequentially on the semiconductor substrate 10 , and deposit polysilicon 50 on the silicon dioxide film 40 . The formed device is shown in FIG. 5 , specifically, the thick gate oxide 20 is made of silicon dioxide, and after the thick gate oxide 20 is deposited, an amorphous layer is deposited on the thick gate oxide 20 by CVD (Chemical Vapor Deposition). The carbon 30 has a thickness ranging from 50 to 200 Å. Further, the deposited amorphous carbon 30 can withstand heat treatment at a temperature of 950° C. for 30 minutes, which can meet the thermal budget requirements of a normal logic process. Next, a silicon dioxide film 40 is deposited in an atomic position in an ALD (atomic position deposition) device without plasma, and the thickness of the silicon dioxide film 40 is 20˜100 angstroms.

Step 3: Patterning the polysilicon 50 to form an isolation layer 70 outside the area where the gate is to be formed on the polysilicon 50, and forming an isolation layer 70 between the semiconductor substrate 10 and the gate area There is an etching stop layer 60, and the device structure after formation is shown in FIG. 6 .

Preferably, said step 3 mainly includes:

Step 31: Coating photoresist on the polysilicon 50 where the gate is to be formed;

Step 32: using the photoresist as a mask and the semiconductor substrate 10 as a cut-off layer, etching the polysilicon 50, silicon dioxide film 40, amorphous carbon 30 and thick gate oxide 20 outside the gate region, to form grooves;

Step 33 : forming an etching stop layer 60 on the semiconductor substrate 10 in the groove and on the edge of the groove, and filling the groove with an insulating material to form an isolation layer 70 .

Further, the etching stop layer 60 is made of silicon nitride, and the etching stop layer 60 can prevent the etching from affecting the isolation layer 70 during the subsequent etching process of the polysilicon 50 .

Step 4: As shown in FIG. 7, etch and remove the polysilicon 50 in the gate region; specifically, a dry etching process can be used to remove the polysilicon 50 in the gate region, and the etching stops on the uppermost silicon dioxide film 40, because The uppermost silicon dioxide film 40 is a sacrificial layer, which allows the etching selectivity ratio of polysilicon 50 and silicon dioxide to be as low as 1:10. Compared with the prior art, the etching of the present invention is easy to adjust and control, and is easier for large-scale production .

Step 5: As shown in FIG. 8 , remove the remaining silicon dioxide film 40 and amorphous carbon 30 in the gate region, specifically, dry etching process can be used to remove the remaining silicon dioxide film 40 and the amorphous carbon 30.

Step 6: filling the gate region with a high-k dielectric layer and metal gate material. Due to the different devices formed, the structures of the gates are also different. In the present invention, there are differences in the gate formation methods of core low-voltage devices and IO devices.

As shown in FIG. 9, when forming the core low-voltage device, step 6 includes: stripping and removing the thick gate oxide 20, and sequentially depositing an initial oxide layer 80 on the semiconductor substrate 10, on the initial oxide layer 80 The high-k dielectric layer 90 , the work function metal layer 100 and the metal gate material 110 are sequentially filled.

When forming an IO device, there is no need to remove the thick gate oxide 20, so step 6 includes: sequentially filling the high-k dielectric layer 90, the work function metal layer 100 and the metal gate material 110 on the thick gate oxide 20, further, the The metal gate material 110 is aluminum.

In summary, the present invention provides a method for preparing an HKMG device, comprising: step 1: providing a semiconductor substrate 10; step 2: depositing thick gate oxide 20, amorphous carbon 30 and Silicon dioxide film 40, and depositing polysilicon 50 on the silicon dioxide film 40; Step 3: Carrying out patterning treatment on the polysilicon 50, so as to form isolation outside the area where the gate is to be formed on the polysilicon 50 Layer 70, an etch stop layer 60 is formed between the isolation layer 70 and the semiconductor substrate 10 and the gate region; step 4: etching and removing the polysilicon 50 in the gate region; step 5: stripping and removing the remaining polysilicon in the gate region Silicon dioxide film 40 and amorphous carbon 30; step 6: filling high-k dielectric layer 90 and metal gate material 110 in the gate region. In the present invention, by forming an oxygen-amorphous carbon-silicon dioxide composite film on the semiconductor substrate 10, it can be directly carried out in existing equipment without additional equipment investment, and oxygen-amorphous carbon-oxygen belongs to the previous standard material, There is no need to worry about pollution or thermal stability issues; in step 4, the etching stops on the uppermost silicon dioxide film 40, since the uppermost silicon dioxide film 40 belongs to the sacrificial layer, allowing polysilicon 50 and silicon dioxide etching selectivity ratio As low as 1:10, compared with the prior art, the etching of the present invention is easy to adjust and control, and is easier to produce on a large scale; The thickness of the thick gate oxide 20 has little effect and the difference is fixed. Generally, the film thickness loss of the thick gate oxide 20 is within 2A, which can effectively improve the stability of the device.

Obviously, those skilled in the art can make various changes and modifications to the invention without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (9)

1. A preparation method of an HKMG device, comprising: Step 1: providing a semiconductor substrate; Step 2: sequentially depositing thick gate oxide, amorphous carbon and silicon dioxide films on the semiconductor substrate, and depositing polysilicon on the silicon dioxide film; Step 3: Patterning the polysilicon to form an isolation layer outside the area where the gate is to be formed on the polysilicon, and an etching stop layer is formed between the isolation layer and the semiconductor substrate and the gate area ; Step 4: Etching and removing the polysilicon in the gate region; Step 5: stripping and removing the remaining silicon dioxide film and amorphous carbon in the gate area; Step 6: filling the gate region with a high-k dielectric layer and metal gate material. 2. the preparation method of HKMG device as claimed in claim 1 is characterized in that, in described step 2, adopt chemical vapor deposition method to form described amorphous carbon on described thick gate oxide, adopt atomic position deposition method in A silicon dioxide film is deposited on the amorphous carbon. 3. The preparation method of HKMG device according to claim 1 or 2, characterized in that, the thickness of the amorphous carbon is 50-200 angstroms, and the thickness of the silicon dioxide film is 20-100 angstroms. 4. the preparation method of HKMG device as claimed in claim 1 is characterized in that, described step 3 comprises: Step 31: Coating photoresist on the polysilicon area where the gate is to be formed; Step 32: using the photoresist as a mask and the semiconductor substrate as a cut-off layer, etching the polysilicon, silicon dioxide film, amorphous carbon and thick gate oxide outside the gate region to form a groove; Step 33: forming an etching stop layer on the semiconductor substrate in the groove and on the edge of the groove, and filling the groove with an insulating material to form an isolation layer. 5. The preparation method of HKMG device according to claim 1, characterized in that, in the step 5, a dry etching process is used to remove the remaining silicon dioxide film and amorphous carbon. 6. The preparation method of HKMG device according to claim 1, characterized in that, when forming the core low-voltage device, the step 6 comprises: stripping and removing the thick gate oxide, and sequentially depositing initial The oxide layer is filled with a high-k dielectric layer, a work function metal layer and a metal gate material in sequence on the initial oxide layer. 7. The method for preparing an HKMG device according to claim 1, wherein when forming an IO device, said step 6 comprises: sequentially filling a high-k dielectric layer, a work function metal layer and Metal grid material. 8. The method for fabricating an HKMG device according to claim 6 or 7, wherein aluminum is used as the metal gate material, and silicon dioxide is used as the thick gate oxide. 9 . The method for fabricating an HKMG device according to claim 1 , wherein in step 4, a dry etching process is used to remove the polysilicon layer in the gate region.