CN104241109A - Method for manufacturing semiconductor device - Google Patents

Abstract

The invention discloses a method for manufacturing a semiconductor device, which includes the following steps: providing a semiconductor substrate, forming a gate oxide layer and a dummy gate in sequence on the semiconductor; forming a gate spacer; forming a contact hole etch stop layer on the dummy gate, the gate spacer and the semiconductor substrate; forming an interlayer dielectric on the contact hole etch stop layer layer; performing a planarization process to expose the dummy gate, the gate spacer and the contact hole etch stop layer; the exposed gate spacer, the contact hole etch stop layer and The interlayer dielectric layer is implanted with carbon. The method according to the present invention solves the problem of loss of contact hole etch stop layer and gate spacer structure in the process of etching and removing dummy gate and gate oxide layer by using full-scale carbon implantation to process semiconductor device, so as to avoid generation of metal residue It can improve the overall performance of semiconductor devices and improve the yield rate of semiconductors.

Description

A method of manufacturing a semiconductor device

technical field

The invention relates to a semiconductor manufacturing process, in particular to a method for removing a dummy gate.

Background technique

With the increasing maturity of semiconductor integrated circuit (IC) industrial technology and the rapid development of ultra-large-scale integrated circuits, the size of components is getting smaller and smaller, and the integration level of chips is getting higher and higher. Due to the high density of devices, the requirement of small size has an increasingly prominent impact on semiconductor technology. The continuous increase of IC integration requires the continuous scaling down of device size, but the operating voltage of electrical appliances sometimes remains unchanged, resulting in higher power consumption of actual metal oxide semiconductor (MOS) devices. Polysilicon and silicon dioxide are commonly used to form gates and interlayer dielectrics of MOS transistors.

As the gate size shrinks to tens of nanometers, the thickness of the gate oxide layer drops below 3nm, causing problems such as excessive gate resistance, increased gate leakage, and depletion of polysilicon gates. Therefore, people have turned their attention to metal gate technology again, using metal gate materials instead of traditional polysilicon materials, high-k dielectrics instead of oxide layer materials, that is, using high-k dielectric/metal gate (HK/MG) structures instead of gate oxides. layer/dummy polysilicon gate structure to avoid polysilicon depletion effect caused by polysilicon dummy gate, diffusion of doped boron atoms and higher gate leakage current. At the same time, N-MOS and P-MOS have different functions, so gates with different structures are required.

The metal gate technology includes a gate-first process and a gate-last process. The characteristic of the Gate-last process is that the metal gate is formed after the drain/source region ion implantation operation and the subsequent high-temperature annealing step are completed on the silicon wafer, and the removal of the polysilicon dummy gate (DPGR) and gate oxide layer is one of the key steps. one. Dry etching is usually used to remove polysilicon dummy gates, because dry etching is more efficient than wet etching, and the change of etching rate is not affected by doping. Diluted hydrofluoric acid (DHF) is used to remove gate oxide. layer to form the interface layer (interfacial layer), however, the contact hole etch stop layer (CESL) and the gate spacer (spacer) are easily recessed during the process of removing the gate oxide layer with dilute hydrofluoric acid , which will lead to the formation of metal residues.

In the prior art, a method for removing the gate oxide layer using the SiCoNi pre-cleaning process is disclosed, that is, the SiCoNi pre-cleaning process is used to replace the diluted hydrofluoric acid to clean and remove the gate oxide layer. As shown in FIG. 1A, a semiconductor substrate ( not shown). A gate oxide layer 100 and a polysilicon dummy gate 101 are sequentially formed on the semiconductor substrate, and gate spacers 102A and 102B are formed on both sides of the gate oxide layer 100 and the polysilicon dummy gate 101. The material can be selected as silicon nitride, and the formation method It may be a chemical vapor deposition (CVD) method. A contact hole etch stop layer 103 is formed on the semiconductor substrate, the polysilicon dummy gate 101 and the gate spacers 102A, 102B. Next, an interlayer dielectric layer (ILD) 104 is formed on the contact hole etch stop layer 103 . Then, the redundant interlayer dielectric layer and the contact hole etch stop layer are removed by chemical mechanical polishing (CMP) to expose the polysilicon dummy gate 101, the gate spacers 102A, 102B and the contact hole etch stop layer 103, And the tops of the polysilicon dummy gate 101 , the gate spacers 102A, 102B, the contact hole etch stop layer 103 and the interlayer dielectric layer 104 are flush.

As shown in FIG. 1B , the polysilicon dummy gate 101 is etched away to form a trench 105 to expose the gate oxide layer 100 . Etching may be performed by dry etching or wet etching. Dry etching is preferred.

As shown in FIG. 1C , the gate oxide layer 100 is removed by a SiCoNi pre-cleaning process to form trenches 106 . Among them, the SiCoNi pre-cleaning process includes two steps: NF ₃ /NH ₃ remote plasma etching and in-situ annealing, and these two steps are completed in the same chamber, and the semiconductor substrate is placed in the reaction chamber to remove the gate. Polar oxide layer 100. Alternatively, dilute hydrofluoric acid is used to remove the gate oxide layer 100 to form trenches 106 .

In the process of manufacturing a complementary metal oxide semiconductor device with a metal gate structure, the process of removing the polysilicon dummy gate and the gate oxide layer is a key step in the subsequent formation of the metal gate structure. However, when the gate oxide layer is removed by dilute hydrofluoric acid or SiCoNi pre-cleaning process according to the prior art, the semiconductor structure will be damaged. Specifically, when using diluted hydrofluoric acid to remove the gate oxide layer, most of the contact hole etch stop layer and gate spacer will be lost, and when the SiCoNi pre-cleaning process is used to remove the gate oxide layer, part of the contact holes will be lost etch stop layer. According to the prior art, during the process of removing the gate oxide layer, the removal process used will consume the contact hole etch stop layer and the gate spacer structure in the semiconductor structure, which will lead to the formation of metal residues.

Therefore, a new method is needed to avoid the loss of the gate spacer structure and the contact hole etching stop layer when the gate oxide layer is etched away, so as to improve the overall performance of the device and the yield rate of the semiconductor device.

Contents of the invention

A series of concepts in simplified form are introduced in the Summary of the Invention, which will be further detailed in the Detailed Description. The summary of the invention in the present invention does not mean to limit the key features and essential technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.

In order to solve the problems existing in the prior art, the present invention proposes a method for manufacturing a semiconductor device, comprising the following steps, providing a semiconductor substrate, forming a gate oxide layer and a dummy gate in sequence on the semiconductor; forming a gate spacer on both sides of the oxide layer and the dummy gate; forming a contact hole etch stop layer on the dummy gate, the gate spacer and the semiconductor substrate; forming an interlayer dielectric layer on the etch stop layer; performing a planarization process to expose the dummy gate, the gate spacer and the contact hole etch stop layer; for the exposed gate spacer , performing carbon implantation on the contact hole etch stop layer and the interlayer dielectric layer.

Preferably, the carbon implantation step is performed using a comprehensive carbon implantation process.

Preferably, the ion beam energy of carbon implantation is 10KV-50KV.

Preferably, the ion dose of carbon implantation is 1e ¹⁴ to 1e ²⁰ atoms/cm ² .

Preferably, it also includes the step of removing the dummy gate after the carbon implantation.

Preferably, the method further includes a step of removing the gate oxide layer to form a first trench after removing the dummy gate.

Preferably, the gate oxide layer is removed using diluted hydrofluoric acid.

Preferably, the method further includes the step of forming an interface layer at the bottom of the first trench to form a second trench after removing the gate oxide layer.

Preferably, the method further includes the step of filling the second trench with a high-k dielectric layer and a metal gate after the formation of the interface layer.

In summary, the method of the present invention solves the problem of loss of contact hole etch stop layer and gate spacer structure in the process of etching and removing dummy gate and gate oxide layer by using comprehensive carbon implantation to process semiconductor devices, so as to Avoid the generation of metal residues, improve the overall performance of semiconductor devices, and improve the yield of semiconductors.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention. In the attached picture,

1A-1C are schematic cross-sectional structure diagrams of a device obtained by etching and removing a dummy gate and a gate oxide layer according to related steps in the prior art;

2A-2G are schematic cross-sectional structure diagrams of devices obtained by etching and removing the dummy gate and gate oxide related steps according to an embodiment of the present invention;

FIG. 3 is a process flow diagram of etching and removing a dummy gate and a gate oxide layer according to an embodiment of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

In order to thoroughly understand the present invention, detailed steps will be proposed in the following description, so as to illustrate how the present invention uses carbon implantation process to solve the problem of the contact hole etching stop when etching and removing the dummy gate and gate oxide layer in the semiconductor device. Layer and gate spacer structure loss issues. Apparently, the preferred embodiments of the present invention are described in detail as follows, however, the present invention may also have other implementations apart from these detailed descriptions.

In order to overcome the loss of the contact hole etch stop layer and the gate spacer structure during traditional removal of the dummy gate and gate oxide layer, the present invention proposes to process the semiconductor substrate with a carbon implantation process. Referring to FIG. 2A to FIG. 2G , there are shown cross-sectional views of related steps of fabricating a PMOS according to an embodiment of an aspect of the present invention.

As shown in FIG. 2A, a semiconductor substrate is provided, and the semiconductor substrate may include any semiconductor material, which may include but not limited to: Si, SiC, SiGe, SiGeC, Ge alloys, GeAs, InAs, InP, and others III-V or II-VI compound semiconductors. Semiconductor substrates include various isolation structures such as shallow trench isolation (STI). The semiconductor substrate may also include an organic semiconductor or a layered semiconductor such as Si/SiGe, silicon-on-insulator (SOI), or SiGe-on-insulator (SGOI). A PMOS region is formed on a semiconductor substrate, the PMOS region has a dummy gate structure 200 formed on a uniformly doped channel region, and the dummy gate structure 200 includes a gate oxide layer 201 and a dummy gate 202 . The gate oxide layer 201 can be formed by thermal oxidation, chemical vapor deposition (CVD) or oxynitride process. Gate oxide layer 201 may comprise any conventional dielectric such as _SiO2 , SiON, SiON2, and other similar oxides including perovskite-type oxides. Wherein, the gate oxide layer 201 is preferably made of silicon oxynitride, and is formed by chemical vapor deposition. The material of the dummy gate 202 may be polysilicon, silicon nitride or amorphous carbon, wherein the material of the dummy gate 202 is preferably undoped polysilicon. The method for forming the polysilicon dummy gate 202 may be a low pressure chemical vapor deposition (LPCVD) process. The process conditions for forming the polysilicon include: the reaction gas is silane (SiH ₄ ), the flow range of the silane may be 100-200 cubic centimeters per minute (sccm), such as 150 sccm; the temperature range in the reaction chamber may be 700-750 Celsius; the pressure in the reaction chamber can be 250 to 350 millimeters of mercury (mTorr), such as 300mTorr; a buffer gas can also be included in the reaction gas, and the buffer gas can be helium or nitrogen, and the helium and nitrogen The flow rate range can be 5-20 liters per minute (slm), such as 8slm, 10slm or 15slm. Gate spacers 203A, 203B are formed on both sides of the gate oxide layer 201 and the dummy gate 202 . The material of the gate spacer can be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. As an optimized implementation of this embodiment, the spacer is composed of silicon oxide and silicon nitride. Next, a contact hole etch stop layer 204 is formed on the semiconductor substrate, the dummy gate 202 and the gate spacers 203A, 203B. The material of the contact hole etching stop layer 204 may be silicon nitride, silicon carbide, silicon oxynitride or silicon carbide nitride. Then, an interlayer dielectric layer 205 is formed on the contact hole etch stop layer 204. The interlayer dielectric layer 205 can be made of, for example, silicon oxide, fluorocarbon (CF), carbon-doped silicon oxide (SiOC), or carbon nitride Silicon (SiCN), etc. Alternatively, a thin film of SiCN formed on a fluorocarbon (CF) or the like may be used. Thermal chemical vapor deposition methods, plasma processes can be used. Use chemical mechanical polishing (CMP) to remove the redundant interlayer dielectric layer and the contact hole etch stop layer, so that the dummy gate 202, the gate spacers 203A, 203B, the contact hole etch stop layer 204 and the interlayer dielectric The top of layer 205 is flush.

As shown in FIG. 2B , Blanket Carbon Implantation is performed on the semiconductor structure to form a carbon doped layer 206 on the gate spacers 203A, 203B, the contact hole etch stop layer 204 and the interlayer dielectric layer 205 . Specifically, the dummy gate 202, the gate spacers 203A, 203B, the contact hole etch stop layer 204 and the interlayer dielectric layer 205 are fully carbon-implanted, and the gate spacers 203A, 203B, the contact hole etch stop Carbon doped layer 206 is formed in layer 204 and interlayer dielectric layer 205 . The process of comprehensive carbon implantation is: implantation ion beam energy is 10KV-50KV, ion dose is 1e ^{14-1e 20} atoms/cm ² . Carbon plasma is implanted into the materials of the gate spacers 203A, 203B, the contact hole etch stop layer 204 and the interlayer dielectric layer 205, and the gate spacers 203A, 203B, the contact hole etch stop layer 204 and the layer A carbon-doped layer is formed in the inter-dielectric layer 205 .

As shown in FIG. 2C , the dummy gate 202 in the PMOS region is removed by etching, and a trench structure 207 is formed at the original position of the dummy gate 202 . The dummy gate 202 can be removed by dry etching, and the dry etching process includes but not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser cutting. For example, by using plasma etching, the etching gas may be an oxygen-based (O ₂ -based) gas, which can reduce the loss of the interlayer dielectric layer 201 . Specifically, the dry etching of polysilicon is realized by adopting relatively low radio frequency energy and generating low-pressure and high-density plasma gas. As an example, using a plasma etching process, the etching gas used is an oxygen (O ₂ -based) gas, and the flow rate of the etching gas can range from 50 cubic centimeters per minute (sccm) to 150 cubic centimeters per minute (sccm), the pressure in the reaction chamber may be 5 mTorr (mTorr)-20 mTorr (mTorr). Wherein, the etching gas for dry etching may also be hydrogen bromide gas, carbon tetrafluoride gas or nitrogen trifluoride gas.

As shown in FIG. 2D , the gate oxide layer 201 may be removed by a SiCoNi pre-cleaning process to form trenches 208 . The SiCoNi pre-cleaning process includes two steps: NF ₃ /NH ₃ remote plasma etching and in-situ annealing, and these two steps are completed in the same chamber, and the semiconductor substrate is placed in the reaction chamber to remove the gate oxide Layer 201. Alternatively, dilute hydrofluoric acid is used to remove the gate oxide layer 201 to form trenches 208 .

As shown in FIG. 2E , an interfacial layer (IL layer) 209 of the metal gate is formed at the bottom of the trench 208 to form the trench 210 . The interfacial layer may comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant of from about 4 to about 20. Alternatively, the interfacial layer may comprise a generally higher dielectric constant dielectric material having a dielectric constant of from about 20 to at least about 100.

As shown in FIG. 2F , a high-k dielectric layer (HK) 211 is deposited on the sidewall and bottom surface of the trench 210 on the interface layer 209 to form the trench 212 . The thickness of the high-k dielectric layer is small, and the high-k dielectric distributed along the surface of the trench structure 210 forms a U-shaped structure. The high-k dielectric material layer can be selected from but not limited to HfO _x , HfSiO _x , HfSiNO _x , HfZrO _x , and the height is about 5-25 angstroms.

As shown in FIG. 2G , a metal gate 213 forming a PMOS is deposited in the trench 212 in the PMOS region. Deposit the PMOS work function metal layer and metal electrode layer on the surface of the carbon-doped layer 206, the surface of the high-k dielectric layer 211, the sidewall and the bottom surface of the trench structure 212, and the material of the metal gate includes copper, aluminum, TiN or TaN, etc. , the forming method may be a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method, wherein a copper metal layer is preferably deposited. Next, chemical mechanical polishing (CMP) is performed to remove excess work function metal layer and metal electrode layer, so that the carbon-doped layer 206 is exposed, then the chemical-mechanical polishing is stopped, and the top of the carbon-doped layer 206 is flush with the top of the metal gate 213 .

According to another aspect of the present invention, the above method for preparing the metal gate of the PMOS region of the semiconductor device structure can also be used in the preparation process of the NMOS region. Specifically, a gate oxide layer and a polysilicon dummy gate are sequentially formed on the semiconductor substrate, and gate spacers are formed on both sides of the gate oxide layer and the polysilicon dummy gate. Next, a contact hole etch stop layer is formed on the semiconductor substrate, the dummy gate and the gate spacer. Then, an interlayer dielectric layer is formed on the etch stop layer of the contact hole, and the redundant interlayer dielectric layer and the etch stop layer of the contact hole are removed by chemical mechanical polishing (CMP), so that the dummy gate, the gate spacer , the contact hole etch stop layer is flush with the top of the interlayer dielectric layer. Next, carbon implantation is performed on the dummy gate, the gate spacer, the contact hole etch stop layer and the interlayer dielectric layer, and doped carbon is formed in the gate spacer, the contact hole etch stop layer and the interlayer dielectric layer. carbon layer. Then, the dummy gate and the gate oxide layer in the NMOS region are removed to form a trench structure. Finally, a metal gate structure of NMOS is formed in the trench structure. Specifically, an interface layer, a high-k dielectric layer, an NMOS work function metal layer and a metal electrode layer are formed in the trench.

Preferably, the PMOS region and the NMOS region in the semiconductor device structure can be performed simultaneously. Specifically, when preparing a certain operation in the PMOS region, such as "etching and removing the dummy gate", "etching and removing the gate oxide layer", "forming the trench structure" or "filling the metal gate", etc., a mask can be used Or the photoresist masks the NMOS region of the semiconductor device structure. Correspondingly, when operating on the NMOS region, the PMOS region may be shielded with a mask or a photoresist. Of course, whether the NMOS region and the PMOS region of the semiconductor device structure are prepared at the same time or for a single region is mainly based on the selection of actual process equipment.

Referring to FIG. 3 , there is shown a process flow chart for removing dummy gates and gate oxide layers according to an embodiment of the present invention, which is used to briefly illustrate the flow of the entire manufacturing process.

In step 301, a semiconductor substrate with shallow trench isolation is provided, and a gate oxide layer and a polysilicon dummy gate are sequentially formed on the semiconductor substrate, and spacers are formed on both sides of the gate oxide layer and the polysilicon dummy gate. A contact hole etch stop layer is formed on the semiconductor substrate, the polysilicon dummy gate and the gate spacer, and the redundant contact hole etch stop layer is removed to expose the polysilicon dummy gate and the gate spacer. Next, an interlayer dielectric layer is formed on the polysilicon dummy gate, the gate spacer and the etch stop layer of the contact hole. Then, the redundant interlayer dielectric layer is removed by chemical mechanical polishing process to expose the polysilicon dummy gate, gate spacer and contact hole etch stop layer, and the polysilicon dummy gate, gate spacer and contact hole are etched The stop layer is flush with the top of the interlayer dielectric layer.

In step 302, carbon implantation is performed on the dummy gate, the gate spacer, the contact hole etch stop layer and the interlayer dielectric layer, so that the gate spacer, the contact hole etch stop layer and the interlayer dielectric A carbon-doped layer is formed in the layer.

In step 303, the dummy gate is removed by etching, and a first trench structure is formed at the original position of the dummy gate.

In step 304, the gate oxide layer 201 is removed by dilute hydrofluoric acid or a SiCoNi pre-cleaning process to form a second trench.

In step 305 , an interface layer of the metal gate is formed at the bottom of the second trench to form a third trench.

In step 306, a high-k dielectric layer, a work function metal layer and a metal electrode layer are filled in the third trench to form a metal gate.

In summary, the method of the present invention solves the problem of loss of contact hole etch stop layer and gate spacer in the process of etching and removing dummy gate and gate oxide layer by using comprehensive carbon implantation to process semiconductor devices, so as to avoid Metal residues are generated, which ultimately improves the overall performance of the semiconductor device and the yield rate of the semiconductor device.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the present invention, and these variations and modifications all fall within the scope of the present invention. .

Claims (9)

1. A method of making a semiconductor device, comprising: providing a semiconductor substrate on which a gate oxide layer and a dummy gate are sequentially formed; forming gate spacers on both sides of the gate oxide layer and the dummy gate; forming a contact hole etch stop layer on the dummy gate, the gate spacer and the semiconductor substrate; forming an interlayer dielectric layer on the etch stop layer of the contact hole; performing a planarization process to expose the dummy gate, the gate spacer and the contact hole etch stop layer; Carbon implantation is performed on the exposed gate spacer, the contact hole etch stop layer and the interlayer dielectric layer. 2. The method of claim 1, wherein the carbon implantation step is performed using a full-scale carbon implantation process. 3. The method according to claim 1, characterized in that the ion beam energy for carbon implantation is 10KV-50KV. 4 . The method according to claim 1 , wherein the ion dose of carbon implantation is 1e ¹⁴ -1e ²⁰ atoms/cm ² . 5. The method of claim 1, further comprising the step of removing said dummy gate after carbon implantation. 6. The method according to claim 5, further comprising the step of removing the gate oxide layer to form a first trench after removing the dummy gate. 7. The method of claim 6, wherein the gate oxide layer is removed using diluted hydrofluoric acid. 8. The method according to claim 6, further comprising the step of forming an interface layer at the bottom of the first trench to form a second trench after removing the gate oxide layer. 9. The method according to claim 8, further comprising the step of filling the second trench with a high-k dielectric layer and a metal gate after said forming the interface layer.