CN105100654B - A kind of pixel unit circuit and pixel read chip - Google Patents

Abstract

The embodiment of the present invention discloses a pixel unit circuit and a pixel readout chip. The pixel unit circuit includes: a charge-sensitive preamplifier for low-noise amplification of the pixel detector signal; a discriminator for low-noise The amplified detection signal is compared with the threshold value, and the useful signal is screened and judged; a counter chain includes an N-bit counter, and the useful signal is counted and counted according to the screening judgment result, wherein N is an integer greater than 1; a shift register chains, including N-bit registers, are respectively connected to the counter chains, and when a frame refresh signal arrives, the shift register chain shifts and reads out the counting statistics results in the counter chains. The technical solution of the embodiment of the present invention can reduce the readout dead time and improve the frame refresh rate index of the chip.

Description

A pixel unit circuit and a pixel readout chip

technical field

The invention relates to the technical field of semiconductors, in particular to a pixel unit circuit and a pixel readout chip.

Background technique

The pixel readout chip or pixel detection system in the traditional sense mainly completes the signal detection based on charge integration. For example, CCD (Charge-coupled Device, charge-coupled device), CMOS (a typical solid-state imaging sensor) camera, etc., integrate the charge through the capacitor connected to the photodiode, and read out the integrated amplitude, as shown in the figure 1 and Figure 2, so as to detect the semaphore within a period of time. This method cannot effectively distinguish signal and noise, and the signal-to-noise ratio is not high.

In order to effectively distinguish single photons or incident particles, a type of pixel readout chip based on single photon signal processing has been developed. As shown in Figure 3, this type of chip uses a charge-sensitive preamplifier to first amplify a single incident signal with low noise, and then set a threshold to reject noise signals whose amplitude is lower than the threshold, so as to obtain a true noise-free signal. detector signal. For threshold-crossing discrimination signals, the simplest processing method is to count the number of threshold-crossing events within a period of time, so as to indirectly obtain the statistics of signal brightness during this period. This method is called single-photon counting mode. Afterwards, the chip needs to read out and clear the counting results of each pixel according to a certain refresh frequency, so as to start a new round of counting. If the count of each pixel is used as the image brightness, the two-dimensional position of the pixel corresponds to the position of the image point, and the read data forms a frame of image, that is, the chip usually works in the frame refresh mode.

Single photon counting pixel chips have been developed, mainly for synchrotron radiation or medical imaging applications. The structural block diagrams of the pixel unit circuits of two representative mainstream products are shown in Fig. 4 and Fig. 5 respectively. It can be seen from the figure that the analog front-end circuits of the two products are similar, and the charge-sensitive preamplifier described above is used to amplify the input signal of the detector with low noise, and then pass through the discriminator (referred to as discriminator in Figure 5). Discriminator) compares the signal amplitude with the set threshold, and uses the counter to count the over-threshold signals.

There are some differences between the two products in the way they are read out. In Fig. 4, the counting result of the counter is read out through the way of row and column strobe, and through the way of column bus. That is, during the readout process, the counting result of the counter is locked, and the pixels are sequentially enabled through the row and column selection signals, so that the counting result is connected to the data bus, thereby realizing readout. In Fig. 5, the read-out is accomplished by means of a linear feedback shift register, that is, in the counting phase, this part of the logic works as a pseudo-random number counter to make statistics on the discrimination threshold signal; and in the read-out phase, This part of the logic will be connected to the front and rear adjacent pixels, and work as a section of the long chain of shift registers. Through the global clock, the counting results of each pixel will be sequentially shifted to the chip pins and output.

It can be seen that the readout methods of the two mainstream products have a common disadvantage: the counter cannot simultaneously count when reading out. In Figure 4, the counter needs to wait to be loaded to the data bus, so the result needs to be in a latched state until the result of a frame is read out before it can be cleared and continue to work next time; while in Figure 5, the counter circuit is reading It is used as a shift register when it is output, and it can only switch back to the counting mode after a frame is read out. Therefore, the readout time of these two structures will become the detection dead time. At the same time, this working method also limits the improvement of the frame refresh rate: that is, if the frame refresh rate is to be increased, the only way to reduce the readout time is to use high-speed clocks and high-speed clocks. On the one hand, the difficulty of designing high-speed digital circuits is greatly improved, and at the same time, the introduction of high-speed digital signals will also cause more crosstalk to sensitive analog circuits.

The two readout methods discussed in Figure 4 and Figure 5 are the main representative readout structures of various products of single photon counting pixel chips. Due to the limitations of the structure and working principle, the frame refresh rate indicators of the latest versions of these two mainstream series products are only at the level of tens of frames per second to one hundred frames per second, and a high-speed display with a clock frequency of about 100MHz is required. The clock, though, still has a high dead time of around 3ms per frame. The frame refresh rate and dead time indicators can no longer meet the requirements of the latest generation of synchrotron radiation applications, and there are currently no products that meet the requirements on the market. This type of application requires a refresh rate better than 1,000 frames per second under the premise of ensuring performance, so as to observe the dynamic response of some short-lived samples. Therefore, the development of a single-photon counting pixel readout chip design method with a high frame refresh rate has become the key to promote the application of this technology in higher-end applications.

In addition, since it works under radiation conditions, the design of the readout chip must consider the anti-radiation design. In the pixel unit configuration registers of mainstream products, the classic triple-mode redundant circuit is generally used, and a certain degree of anti-radiation reinforcement is carried out for Single Event Upset (SEU). As shown in FIG. 6 and FIG. 7 , configuration registers usually adopt a certain redundancy design. For a pixel readout chip that typically requires 5, 6 register bits or even more per pixel unit, this will take up a lot of space. Under the premise of ensuring performance, the readout method proposed by the present invention can also reduce the design complexity of this part and save pixel space.

Contents of the invention

In view of this, an embodiment of the present invention provides a pixel unit circuit and a pixel readout chip, so as to reduce the readout dead time and increase the frame refresh rate index of the chip.

Other features and advantages of the present disclosure will become apparent from the following detailed description, or in part, be learned by practice of the present disclosure.

In a first aspect, an embodiment of the present invention provides a pixel unit circuit, including:

A charge-sensitive preamplifier for low-noise amplification of the pixel detector signal;

A discriminator, used to compare the low-noise amplified detection signal with a threshold value, and discriminate and judge the useful signal;

A counter chain, including N-bit counters, for counting and counting useful signals according to the screening and judgment results, wherein N is an integer greater than 1;

A shift register chain, including N-bit registers, is respectively connected to the counter chain, and when a frame refresh signal arrives, the shift register chain shifts and reads out the counting results in the counter chain.

Further, the pixel unit circuit further includes a configuration register module connected to the shift register chain;

When the frame refresh signal arrives, the configuration register module inputs the configuration information of the next frame to the input end of the shift register chain, and at the same time, the shift register chain outputs the counting statistics result of the previous frame from the output end , the configuration information and the counting statistics result pass through the shift register chain without overlapping.

Further, when the frame refresh signal arrives, it specifically includes:

When the frame refresh signal arrives at the rising edge of the clock, the signal path between the discriminator and the counter chain is shielded, so that the counting statistics result of the last frame in the counter chain is blocked;

In the first clock cycle from the subsequent falling edge of the clock: the configuration register module becomes a transparent latch state, and the configuration information on the shift register chain is refreshed to each of the configuration register modules The corresponding configuration register is defined as the working state of the next frame of the pixel unit corresponding to the pixel unit circuit;

In the second clock cycle starting from the falling edge of the clock: the counting statistics result of the last frame in the blocked counter chain is loaded into the shift register chain;

In the third clock cycle from the falling edge of the clock: the counting statistics result of the counter chain is cleared, and at the same time, the lock of the counter chain is released.

Further, after the lock of the counter chain is released, it also includes:

The N-bit counter in the counter chain begins to count the useful signals that cross the threshold in a new frame, and the configuration information of the new frame is input from the input end of the shift register chain, and the configuration information of the previous frame is input at the same time. The count data is output from the output end of the shift chain, and the configuration data stream and the count data stream flow through the shift chain without overlapping.

Further, between the charge-sensitive preamplifier and the discriminator, a shaping/amplification module is further included for further amplifying and filtering the low-noise amplified detection signal;

The discriminator is configured to compare the amplified and filtered detection signal with a threshold, and to discriminate and judge useful signals.

Further, the N is an integer greater than or equal to 4 and less than or equal to 20.

In a second aspect, an embodiment of the present invention further provides a pixel readout chip, including a plurality of pixel unit circuits as described in the first aspect.

Further, the pixel readout chip includes:

104 row X72 column pixel array;

9 pixel unit circuits according to any one of claims 1-5;

Each pixel unit circuit includes 104 rows×72 columns of pixels, and the pixel depth is 20 bits.

Further, the frame refresh frequency of the pixel readout chip is greater than or equal to 1.2 kilohertz, and the clock frequency of the pixel readout chip is greater than or equal to 20 megahertz.

The beneficial technical effect of the technical scheme that the embodiment of the present invention proposes is:

The pixel unit circuit described in the embodiment of the present invention includes a counter chain of N-bit counters, counting and counting the useful signals passed through the screening and judgment in the pixel unit; including a shift register of N-bit registers respectively connected to the counter chain chain, when the frame refresh signal arrives, the shift register chain shifts and reads out the counting statistics results in the counter chain. Can significantly improve the frame refresh rate.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments of the present invention. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention , for those skilled in the art, other drawings can also be obtained according to the content of the embodiment of the present invention and these drawings without any creative effort.

Fig. 1 is a kind of integrated voltage readout mode circuit schematic diagram described in the background technology of the present invention;

Fig. 2 is a working timing diagram corresponding to the integrated voltage readout mode circuit principle diagram described in the background technology of the present invention;

Fig. 3 is a schematic block diagram of a single-photon counting pixel readout method described in the background technology of the present invention;

4 is a block diagram of a pixel unit circuit structure of one of the mainstream single-photon counting pixel readout chip products described in the background of the present invention;

Fig. 5 is a block diagram of the pixel unit circuit structure of the second mainstream single-photon counting pixel readout chip product in the background technology of the present invention;

Fig. 6 is a three-mode redundancy and arbitration logic block diagram described in the background technology of the present invention;

Fig. 7 is a transistor-level circuit diagram of a DICE Latch described in the background technology of the present invention;

FIG. 8 is a structural block diagram of a pixel unit circuit according to Embodiment 1 of the present invention;

9 is a block diagram of the gate-level structure of the readout part of the pixel unit circuit according to the first embodiment of the present invention;

FIG. 10 is a working sequence diagram when the pixel unit circuit according to the first embodiment of the present invention reads out a partial frame refresh;

Fig. 11 is a block diagram of the overall structure of a single-photon counting pixel readout chip according to the second embodiment of the present invention.

detailed description

In order to make the technical problems solved by the present invention, the technical solutions adopted and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only the technical solutions of the present invention. Some, but not all, embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.

The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and through specific implementation methods.

Embodiment one

Fig. 8 is the pixel unit circuit described in this embodiment, as shown in Fig. 8, the pixel unit circuit described in this embodiment includes:

A charge-sensitive preamplifier 1, which performs low-noise amplification on the detector signal of the pixel;

A discriminator 2, used to compare the low-noise amplified detection signal with the threshold, and to discriminate and judge the useful signal;

A counter chain 3, including N-bit counters, for counting and counting useful signals according to the screening and judgment results;

A shift register chain 4, including N-bit registers, connected to the counter chain 3 respectively, when the frame refresh signal arrives, the shift register chain 4 shifts the counting statistics results in the counter chain 3 read out.

It should be noted that the pixel unit circuit described in this embodiment utilizes the charge-sensitive preamplifier 1 to perform low-noise amplification on the detector signal in the analog front-end part, which can ensure the low-noise performance of the pixel readout chip. The discriminator 2 compares the output of the preamplifier with the threshold value, so as to complete the screening and judgment of the useful signal; the screening result is sent to the counter for counting statistics.

In order to further amplify and filter the signal for easy identification, in this embodiment, a shaping/amplifying module 5 can be used between the charge-sensitive preamplifier 1 and the discriminator 2 to amplify the detection signal after low-noise amplification Further amplification and filtering. At this time, the discriminator 2 is configured to compare the amplified and filtered detection signal with a threshold value to discriminate and judge useful signals.

The pixel unit circuit described in the embodiment of the present invention includes a counter chain 3 of an N-bit counter, which counts and counts the useful signals passed through the screening and judgment in the pixel unit; The bit register chain 4, when the frame refresh signal arrives, the shift register chain 4 shifts and reads the counting statistics result in the counter chain 3. It can reduce the read dead time and improve the frame refresh rate index of the chip.

Wherein, N is an integer greater than 1, preferably an integer with N greater than or equal to 4 and less than or equal to 20. For example, N is 20, and the counter chain 3 includes a 20-bit counter in each pixel unit, that is, refreshes at a refresh rate of 1 frame per second according to a count rate of 1 MHz per pixel, and just fills up the counter 20 places. If refreshed at a faster refresh rate, the number of counter bits required for the same count rate will be reduced accordingly. Correspondingly, the shift register chain 4 also includes 20 bits of shift information in each pixel unit, and each counter bit is respectively connected to the corresponding shift register bit.

Furthermore, in the readout part, the embodiment of the present invention is quite different from other products of the same kind. In order to avoid occupation of the counter in the data readout stage, a counter chain 3 and a shift register chain 4 that work independently of each other and have the same number of bits need to be designed in the pixel unit circuit described in this embodiment. Data exchange between the two occurs only when the frame refresh signal arrives, and the occupied time is one clock cycle.

In addition, the pixel unit circuit further includes a configuration register module connected to the shift register chain 4 . When the frame refresh signal arrives, the configuration register module inputs the configuration information of the next frame to the input end of the shift register chain 4, and the shift register chain 4 outputs the count statistics result of the previous frame from the output terminal output, and the configuration information and the counting statistics result pass through the shift register chain 4 without overlapping.

The configuration information of the pixel unit circuit described in this embodiment will be input by using the same shift chain, and when the frame refresh signal arrives, the configuration information on the shift chain will be refreshed into the configuration register corresponding to each pixel unit. For example, when the frame refresh signal arrives, the specific working details of the readout part are as follows:

When the frame refresh signal arrives at the rising edge of the clock, the signal path between the discriminator 2 and the counter chain 3 is shielded, so that the counting statistics result of the last frame in the counter chain 3 is blocked;

In the first clock cycle starting from the subsequent falling edge of the clock: the configuration register module becomes a transparent latch state, and the configuration information on the shift register chain 4 is refreshed to the configuration register module Each corresponding configuration register is defined as the working state of the next frame of the pixel unit corresponding to the pixel unit circuit;

In the second clock cycle starting from the falling edge of the clock: the counting statistics result of the last frame in the blocked counter chain 3 is loaded into the shift register chain 4;

In the third clock cycle from the falling edge of the clock: the counting statistics result of the counter chain 3 is cleared, and the blockade of the counter chain 3 is released;

After that, the counter, shift register and configuration register work independently.

The above operations are repeated until all frames of the pixel unit corresponding to the pixel unit circuit are read out.

Figure 9 shows a more specific block diagram of the gate-level circuit structure of the readout section. Each part of the circuit is only shown by its most basic components to show the design idea, but it is not limited to the specific circuit form shown in the figure. All derivative circuit structures based on this structure are within the scope of the present invention. Figure 10 shows the key working timing of the pixel unit circuit before and after the arrival of the frame refresh signal.

As shown in Figure 9 and Figure 10, in the normal working state, the counter continuously counts the discrimination pulses, and the shift register, as a section of the overall shift, participates in the shift readout of the count data, and at the same time shifts and inputs the configuration information ;When the frame refresh signal (frame signal in the figure) arrives at the rising edge of the clock, four steps of action occur in sequence: the counter is the same as the data source, that is, the output of the discriminator is disconnected, and the data is blocked, corresponding to the pixel_down signal in the figure; Within one clock cycle starting from the falling edge of the clock, the configuration register in the pixel unit circuit becomes a transparent latch state, and the configuration information on the shift chain is refreshed to the corresponding configuration register of each pixel unit, corresponding to the refresh signal in the figure, As the definition of the working state of the next frame of the pixel unit; in the next clock cycle (still starting from the falling edge of the clock), the blocked counter count data is latched and loaded into the shift chain, corresponding to the load_shiftb signal in the figure; In the third clock cycle (starting from the falling edge of the clock), the counter result is cleared, and the data block is released at the same time, corresponding to the counter_clear signal in the figure. After this point, the counter and the shift chain can work completely independently again: the counter starts counting the discrimination threshold signal in a new frame; the configuration information of the next frame is input from the input terminal of the shift chain, and the count data of the previous frame is input from The output of the shift chain output, the configuration data stream and the count data stream flow through the shift chain without overlapping. Repeat the above process until the frame refresh signal comes again.

Wherein, it should be noted that the configuration register is mainly used to store the working mode control bit information of each pixel, including threshold information, pixel enabling information, and charge polarity information. During the working period of each frame, the configuration information controls the working state of the analog circuit such as the discriminator in a static level manner, thereby adjusting and controlling the discrimination and judgment of the signal, which will affect the counting result; when the frame refresh signal arrives, it will be refreshed to the next The configuration state of the frame, thus controlling the new round of counting mode. Each bit of the shift chain can have a configuration register or no load, and is refreshed during the refresh signal when the frame signal arrives. The number of bits in the configuration register corresponding to each pixel is determined by specific application requirements, but not more than the length of the shift register chain, eight bits in this example. On the premise that the number of bits in the configuration register is not more than that of the shift register chain, and there is a one-to-one correspondence with the units of the shift chain, it can be connected with the shift register chain in any combination.

According to such a readout method, in each frame, the counter does not need to wait for the readout to be completed before starting counting of a new frame, that is, the counting and readout are completely independent. In each frame time, the counter is only occupied within 3.5 clock cycles of the arrival of the frame refresh signal, so the dead time is only 3.5 times the clock cycle. Calculated based on a typical clock of 20MHz, that is, the dead time of each frame is only 175ns. Compared with the typical dead time of 3ms per frame of the latest mainstream products, its performance index has been improved by at least ten times. And when the clock frequency increases, the dead time will decrease accordingly.

Since readout time and dead time are independent, it is no longer necessary to utilize high-speed clocks, and it is no longer necessary to challenge high-speed digital circuit design to minimize readout time. According to the readout structure of the present invention, the length of the shift register in the pixel unit needs to be exactly the same as the depth of the counter, and also represents the number of clock cycles per frame time. Assuming that the counter depth is N bits, the number of pixel units on the shift chain is M, and the clock frequency is F, then the number of clock cycles per frame is (M*N+1), that is, the frame refresh rate is F/(M* N+1). Among them, the counting depth N is generally less than 20 bits, and the number of pixel units M is usually 1000. Therefore, at a clock frequency of 20MHz, the frame refresh rate will reach 1kHz. Also increased tenfold. In this process, high-speed clocks are not used, so the crosstalk between the modulus and digital will be effectively controlled; at the same time, no complicated circuit design is required, and the implementability is strong. Considering that under the high frame refresh rate index, the counting depth can generally be shortened, such as 10 bits, then the frame refresh rate index will be further increased.

According to the working mode of the present invention, the configuration information of each frame of each pixel unit will be input through the shift register, and the updating of each frame will be realized. In this way, once a single-instance inversion event occurs, which causes an erroneous inversion of a certain configuration information latch bit during normal operation, the error effect caused by it will also be corrected in the next next frame. Due to the high frame refresh rate achieved at the same time, the impact is very limited. In this way, the configuration register can adopt a more conventional latch design, and avoid designing more complicated redundant logic, which occupies a large amount of layout space in the already very limited pixel unit circuit. On the other hand, the configuration information of a conventional pixel chip is usually only loaded once during the power-on stage, and is generally not updated during normal operation, and the triple-mode redundant circuit cannot detect two wrong flips. Therefore, once two wrong flips of the same point occur, the pixel chip will continue to work in the wrong state and continue to obtain wrong data. The present invention completely avoids the occurrence of this situation by adopting a frame refreshing method, limits the influence of errors in a very short time, and ensures that the circuit works in a normal working state most of the time.

Through two independently working counter chains 3 and shift chains, the dead time of reading is reduced, and at the same time, the frame refresh rate index of the chip is significantly improved. By configuring the frame refresh method of the register, the complex anti-radiation hardening design of the latch is avoided. The invention has the characteristics of reliable structure, strong implementability, strong expandability and the like.

Embodiment two

On the basis of the first embodiment, this embodiment proposes a pixel readout chip, which includes a plurality of pixel unit circuits as described in the first embodiment. Fig. 11 is a block diagram of the overall structure of a single-photon counting pixel readout chip according to the second embodiment of the present invention. As shown in Fig. 11, the pixel readout chip uses a plurality of pixel units as described in the first embodiment The circuit can realize the pixel reading of the pixels in all the pixel arrays contained in the chip.

In order to enable those skilled in the art to better understand the technical solution of the present invention, the product of the present invention will be further described below in conjunction with the embodiments and accompanying drawings.

According to the working method described in the present invention, the inventor has completed the design of a single photon counting pixel readout chip. The chip contains a pixel array of 104 rows x 72 columns, divided into 9 shift chains that work independently by column, that is, each shift chain contains 104 rows x 8 columns, a total of 832 pixels, and the pixel counting depth is 20 bits. After actual tape-out and testing, the chip can work well at a system clock frequency of 20MHz or higher, and no crosstalk between analog and digital circuits has been found. This shows that the readout chip can work at a frame refresh rate of 1.2kHz, and the dead time of each frame is less than 175ns. The scale of this pixel chip is comparable to that of mainstream chips currently on the market, and the measured performance indicators of the analog part are also the same as those of such chips. However, the frame refresh rate index and dead time index are nearly 10 times higher than mainstream chips, and the chip has not Rely on high-speed clock or high-speed circuit design. This proves that the structure and design method described in the present invention have good practicability.

In order to ensure that the pixel readout chip can process the weak signal of the detector, it is first necessary to ensure a good design of the analog front-end circuit in the pixel unit circuit, especially the charge-sensitive preamplifier, which determines the noise level and the minimum possible detected signal. The design of the analog front-end circuit can follow the classical circuit design method of nuclear electronics, carefully design the size of the input tube of the charge-sensitive preamplifier, so as to obtain the optimal signal-to-noise ratio level. Since a high frame refresh rate usually means a high case rate level, it is necessary to carefully design the feedback structure of the charge-sensitive preamp so that the bottom width of the output signal meets the required count rate level. The discriminator circuit requires the ability to fine-tune the discrimination threshold, which can usually be realized by a 4 to 6-bit digital-to-analog conversion circuit.

The unit digital circuit as a whole can be composed of three parts as shown in FIG. 9 : a counter, a shift register and a latch. Under the condition that the pixel unit area allows, each digital gate-level circuit can be realized by using a standard unit library. Preferably, each digital gate-level circuit can also be designed in a fully customized method, which will effectively save the area of the pixel unit, but also means a significant increase in the design workload, and may also sacrifice a certain level of the highest frame refresh rate. When the frame refresh signal arrives, a large amount of data will be exchanged between the units in a short period of time. Therefore, it is necessary to carefully plan the timing of this part and conduct sufficient simulation to avoid the occurrence of competitive risks.

As mentioned earlier, the number of bits of the counter and the shift latch in the unit should be exactly the same. The number of bits N should be determined by the target frame refresh rate Fr and the highest count rate level M of the pixel unit, that is, it should be such that: 2 ^N Fr>M, that is, N>log ₂ (M/Fr). The counting depth should be rounded up from the minimum value or increased by 1 bit. A deeper counting depth will not be used, and the frame refresh rate index will be lowered unnecessarily. Preferably, the counter depth can be designed to be optional, so that the highest frame refresh rate index can be obtained at different count rate levels.

The layout of the digital circuit of the unit needs to be carefully planned to avoid crosstalk to the analog circuit when the digital circuit is flipped. Preferably, the part of the circuit can be kept away from the analog circuit in order of operating frequency from low to high, so as to increase the physical isolation from the sensitive analog circuit. Usually there should be latches, counters, and shift registers whose operating frequencies are distributed from low to high in turn.

The input and output of the shift register chains of adjacent pixels are connected in sequence, usually distributed in the column direction, so that each column of pixels forms a long shift register chain. Since the frame refresh rate is directly related to the number of pixels on each shift chain, in the case of a certain pixel array size, in order to improve the frame refresh rate level, the preferred way is to divide the pixel array into several independent groups by columns Each group shares a shift chain, and the shift chains of different groups work independently of each other, thereby increasing parallelism and shortening the length of the shift chain. However, the number of parallel shift chains cannot be increased without limit, otherwise a large amount of chip pin resources will be occupied.

This embodiment aims at the problems that various products of current single-photon counting pixel readout chips have a large dead time, the frame refresh rate cannot meet the requirements, and it is difficult to further improve due to structural limitations. A pixel readout chip proposed has a high Frame refresh rate, the pixel readout chip can increase the frame refresh rate by more than ten times compared with the current mainstream product level while keeping other performance indicators unchanged, and significantly reduce the dead time, while reducing the system clock frequency. Require. In addition, it can also take into account the anti-radiation reinforcement design requirements of single-instance flipping, reduce the design complexity of configuration registers, and save the space occupied by a large number of redundant register circuits within a very limited pixel unit circuit area.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention in any form; all those skilled in the art can smoothly implement the present invention as shown in the attached drawings and the above descriptions. However, any equivalent change, modification and evolution that can be made by those skilled in the art without departing from the scope of the technical solution of the present invention by using the technical content disclosed above are all equivalent implementations of the present invention Example; at the same time, any modification, modification and evolution of any equivalent changes made to the above embodiments according to the substantive technology of the present invention still belong to the protection scope of the technical solution of the present invention.

Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention, and the present invention The scope is determined by the scope of the appended claims.

Claims (8)

1. A pixel unit circuit, characterized in that, comprising: A charge-sensitive preamplifier for low-noise amplification of the pixel detector signal; A discriminator, used to compare the low-noise amplified detection signal with a threshold value, and discriminate and judge the useful signal; A counter chain, including N-bit counters, for counting and counting useful signals according to the screening and judgment results, wherein N is an integer greater than 1; A shift register chain, including N-bit registers, respectively connected to the N-bit counters of the counter chain, when the frame refresh signal arrives, the count data in the N-bit counters of the counter chain is latched and loaded into the shift register. In the N-bit register of the bit register chain; a configuration register module connected to the shift register chain; Wherein the N of the counter and the register is determined by the target frame refresh rate Fr and the highest count rate level M of the pixel unit, N>log ₂ (M/Fr); When the frame refresh signal arrives, it includes: When the frame refresh signal arrives at the rising edge of the clock, the signal path between the discriminator and the counter chain is shielded, so that the counting statistics result of the previous frame in the counter chain is blocked; In the first clock cycle from the subsequent falling edge of the clock: the configuration register module becomes a transparent latch state, and the configuration information on the shift register chain is refreshed to each of the configuration register modules The corresponding configuration register is defined as the working state of the next frame of the pixel unit corresponding to the pixel unit circuit; In the second clock cycle starting from the falling edge of the clock: the counting statistics result of the last frame in the blocked counter chain is loaded into the shift register chain; In the third clock cycle from the falling edge of the clock: the counting statistics result of the counter chain is cleared, and at the same time, the lock of the counter chain is released. 2. The pixel unit circuit according to claim 1, wherein when the frame refresh signal arrives, it specifically includes: The configuration register module inputs the configuration information of the next frame to the input end of the shift register chain, and at the same time, the shift register chain outputs the counting result of the previous frame from the output end, the configuration information and the The count statistics are passed through the chain of shift registers without overlapping. 3. The pixel unit circuit according to claim 1, further comprising: after the lockout of the counter chain is released: The N-bit counter in the counter chain begins to count the useful signals that cross the threshold in a new frame, and the configuration information of the new frame is input from the input end of the shift register chain, and the configuration information of the previous frame is input at the same time. The count data is output from the output end of the shift chain, and the configuration data stream and the count data stream flow through the shift chain without overlapping. 4. The pixel unit circuit according to claim 1, characterized in that, between the charge-sensitive preamplifier and the discriminator, a shaping/amplification module is further included for amplifying the low-noise The detection signal is further amplified and filtered; The discriminator is configured to compare the amplified and filtered detection signal with a threshold, and to discriminate and judge useful signals. 5. The pixel unit circuit according to claim 1, wherein the N is an integer greater than or equal to 4 and less than or equal to 20. 6. A pixel readout chip, characterized in that it comprises a plurality of pixel unit circuits according to any one of claims 1-5. 7. The pixel readout chip according to claim 6, comprising: 104 row x 72 column pixel array; 9 pixel unit circuits according to any one of claims 1-5; Each pixel unit circuit includes pixels with 104 rows×72 columns, and the pixel depth is 20 bits. 8. The pixel readout chip according to claim 7, wherein the frame refresh rate of the pixel readout chip is greater than or equal to 1.2 kilohertz, and the clock frequency of the pixel readout chip is greater than or equal to 20 megahertz .