CN105097984A - Silicon-based heterojunction solar cell passivation layer early stage processing method - Google Patents
Silicon-based heterojunction solar cell passivation layer early stage processing method Download PDFInfo
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- CN105097984A CN105097984A CN201410196467.8A CN201410196467A CN105097984A CN 105097984 A CN105097984 A CN 105097984A CN 201410196467 A CN201410196467 A CN 201410196467A CN 105097984 A CN105097984 A CN 105097984A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 94
- 239000010703 silicon Substances 0.000 title claims abstract description 94
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 93
- 238000002161 passivation Methods 0.000 title claims abstract description 49
- 238000003672 processing method Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 55
- 238000001020 plasma etching Methods 0.000 claims abstract description 28
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 17
- 238000006243 chemical reaction Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 239000003344 environmental pollutant Substances 0.000 claims description 18
- 231100000719 pollutant Toxicity 0.000 claims description 18
- 230000000415 inactivating effect Effects 0.000 claims description 14
- 238000002360 preparation method Methods 0.000 claims description 14
- 230000001590 oxidative effect Effects 0.000 claims description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- 239000000376 reactant Substances 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 12
- 230000007547 defect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021645 metal ion Inorganic materials 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000002086 nanomaterial Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 235000008216 herbs Nutrition 0.000 description 1
- 230000002209 hydrophobic effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000010148 water-pollination Effects 0.000 description 1
- 210000002268 wool Anatomy 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Drying Of Semiconductors (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention provides a silicon-based heterojunction solar cell passivation layer early stage processing method. A plasma etching method is added after a silicon chip cleaning texturing step so as to make natural oxides or other impurities formed on the surface of a silicon chip removed. Meanwhile, micro etching is performed on the nanometer-sized tip of a pyramid textured structure of the silicon chip so as to make a smooth and round form thereof recovered. A passivation layer process is finally finished in a vacuum-maintained condition. Secondary pollution during the process is prevented. The passivation effects of an amorphous silicon passivation layer are thus improved. The passivation quality is guaranteed. The cell conversion efficiency is further improved.
Description
Technical field
The present invention relates to efficient silicon based hetero-junction area of solar cell, particularly relate to a kind of earlier stage processing method of silicon based hetero-junction solar cell inactivating layer.
Technical background
Silicon based hetero-junction solar cell is emerging third generation high performance solar batteries technology, it combines the advantage of first generation monocrystalline silicon and second generation silicon thin film, there is the series of advantages such as conversion efficiency is high, temperature coefficient is low, there is great development potentiality and wide application prospect, be expected to the developing direction leading whole silica-based solar cell.
The preparation of passivation layer is a processing step the most key in silicon based hetero-junction solar cell manufacturing process, high-quality passivation layer effectively can suppress charge carrier in the compound of silicon face and improve minority carrier life time, thus plays the effect improving cell photoelectric conversion efficiency.But, for the silicon nitride passivation thick relative to the about 80nm related in conventional crystalline silicon battery, the amorphous silicon passivation layer very thin thickness of silicon based hetero-junction solar cell, only has 5-10nm, this just requires the necessary easily overlay film of the step of silicon chip surface, therefore the nanoscale passivation layer to prepare high-quality just to the pyramid matte distribution of silicon chip surface and clean-up performance, must comprise oxide, organic substance, impurity metal ion etc., has especially high requirement.
On traditional silicon based hetero-junction manufacture of solar cells line, when silicon chip is after the cleaning step having carried out complete set, could arrive in PECVD reaction chamber prepare passivation layer because silicon chip needs to transmit in an atmosphere a segment distance, and the clean process ability of producing on line and the disposal ability of passivation technology are also difficult to accomplish to mate completely, so silicon chip has to place a period of time in an atmosphere, because being subject to the impact of the factors such as atmospheric oxygen, steam and other impurity in this process, silicon chip surface is easy to form one deck natural oxidizing layer (SiO
x) and adhere to some other impurity, the oxide layer of this insulation can stop charge carrier in the transmission at heterojunction boundary place, and the impurity at heterojunction boundary place also easily becomes the complex centre at interface, increase the recombination rate of minority carrier in interface, reduce the useful life of few son, thus make passivation layer degradation, eventually reduce the photoelectric conversion efficiency of battery.
In the prior art, for this problem, the method of usual employing is often silicon chip is turned back to cleaning machine again clean, or utilize the HF aqueous solution of 3-5% concentration to carry out prerinse easily, but these two kinds of methods all belong to wet-cleaned, process more complicated, simultaneously process controllability, repeatability are all poor.
On the other hand, after silicon chip completes wet-cleaned making herbs into wool, silicon chip surface can form pyramid suede structure, after further chemical polishing, the suede structure of silicon chip surface can become comparatively smooth mellow and full, is conducive to very thin passivation layer and covers pyramidal surface more equably.But, at silicon chip in the process of atmospheric environment, the top of silicon chip surface particularly its pyramid suede structure will form some other nano-scale structure, smooth mellow and full top is made to become sharply, add defect state density, thus have impact on the passivation effect of preparation amorphous silicon passivation layer.
For this problem, patent CN102779907A provides a kind of method introducing plasma etching in the wet treatment process of silicon chip, its main purpose is for optimizing wet-method texturing manufacturing process, surperficial light trapping structure is improved by micro etch process, but after plasma etching completes, this silicon chip have been got back to again in wet treatment process and has been proceeded wet-cleaned, therefore, if transferred to by silicon chip in vacuum PECVD device and carried out passivation layer overlay film, produce pollution problem same on line by facing with tradition.
As can be seen here, in order to improve the passivation layer growth of amorphous silicon and improve passivation effect, the pyramid suede structure on the pollutant needing more effective removal silicon chip surface and the surface of improving silicon chip.
Summary of the invention
The invention provides the method for a kind of silicon based hetero-junction solar cell inactivating layer process in early stage, by increasing the method for plasma etching after the cleaning and texturing step of silicon chip, the natural oxide formed silicon chip surface or other impurity are disposed, and micro etch process is carried out to the nanometer-scale tips of the pyramid suede structure of silicon chip simultaneously, it is made to recover smooth mellow and full pattern, finally under the condition of not vacuum breaker, complete passivation layer technique, avoid middle secondary pollution, thus improve the passivation effect of amorphous silicon passivation layer, ensure passivation quality, finally improve the conversion efficiency of battery.
In order to reach above object, the invention provides a kind of silicon based hetero-junction solar cell inactivating layer earlier stage processing method, mainly comprising the following steps:
The first step, cleans silicon chip and matte preparation, to obtain the clean silicon wafer that surface is pyramid suede structure;
Second step, in the first vacuum chamber, plasma etching is carried out to described silicon chip, in order to remove the pollutant of described silicon chip surface and to enable the surface of described silicon chip recover the pyramid suede structure presented at the end of the above-mentioned first step, described pollutant comprises natural oxidizing layer and other impurity;
3rd step, carries out amorphous silicon passivation layer preparation to described silicon chip in the second vacuum chamber realizing bonding in vacuum with described first vacuum chamber.
Alternatively, described first vacuum chamber carrying out plasma etch process is same vacuum PECVD reaction chamber with carrying out described second vacuum chamber prepared by amorphous silicon passivation layer.
Alternatively, described first vacuum chamber carrying out plasma etch process is two different vacuum reaction chambers from carrying out described second vacuum chamber prepared by amorphous silicon passivation layer.
Alternatively, describedly cleaning carried out to silicon chip comprise: prerinse, clean again, chemical polishing, any one or several step in removal oxide.
Alternatively, the plasma source of described plasma etching adopts and gas activation can be become reactant and any power source keeping reactant plasma.
Alternatively, the mode of described plasma etching can adopt remote plasma source to etch.
Alternatively, the process gas used in described plasma etching comprises fluoro-gas.
Alternatively, the process gas used in described plasma etching can be S
xf
y, N
xf
y, C
xf
y, C
xh
yf
z, H
2, A
r, O
2, Cl
2, Br
2in any one or a few combination.
Compared with prior art, the present invention has following technique effect:
1, in the process of propagation in atmosphere, silicon chip surface inevitably can form pollutant, comprise natural oxidizing layer and other impurity such as organic substance, metal ion, have impact on the passivation effect of amorphous silicon passivation layer, in the present invention, by adopting the method for carrying out plasma etching in the first vacuum chamber, effectively can remove the various pollutants of silicon chip surface, improve passivation effect.
2, the present invention carries out the method for plasma etching in the first vacuum chamber by adopting, can to the suede structure on the pyramid surface of silicon chip, especially by the nanometer-scale tips structure that oxygen, steam and other impurity component in air affect and produce, carry out effective micro etch process, make the top of its suede structure reproduce smooth mellow and full form, thus reduce defect state density, improve the growth quality of passivation layer.
3, in the present invention, the first vacuum chamber carrying out plasma etch process is bonding in vacuum with carrying out the second vacuum chamber prepared by amorphous silicon passivation layer, ensure that silicon chip can complete passivation layer technique after completing plasma etching under the condition of not vacuum breaker, avoid secondary pollution, contribute to obtaining high-quality passivation layer.
4, in a possibility of the present invention, the first vacuum chamber carrying out plasma etching can be same vacuum PECVD reaction chamber with preparation amorphous silicon passivation layer second vacuum chamber, namely successively can carry out two kinds of different PROCESS FOR TREATMENT in a cavity, save equipment cost.
5, in a possibility of the present invention, plasma etching can adopt remote plasma source to realize, and the ion energy that usual remote plasma source produces is relatively little, can avoid because plasma bombards the damage produced to silicon chip surface.
Accompanying drawing explanation
Fig. 1 is the flow chart of silicon based hetero-junction solar cell inactivating layer earlier stage processing method in the present invention.
Fig. 2 is the schematic diagram of the pyramid suede structure of silicon chip surface in the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from additive method described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
The invention provides a kind of silicon based hetero-junction solar cell inactivating layer earlier stage processing method, as shown in Figure 1, the method comprises the following steps its workflow:
Step S1, cleans silicon chip and matte preparation, to obtain the clean silicon wafer that surface is pyramid suede structure;
Step S2, in the first vacuum chamber, plasma etching is carried out to described silicon chip, in order to remove the pollutant of described silicon chip surface and to enable the surface of described silicon chip recover the pyramid suede structure presented at the end of the above-mentioned first step, described pollutant comprises natural oxidizing layer and other impurity;
Step S3, carries out amorphous silicon passivation layer preparation to described silicon chip in the second vacuum chamber realizing bonding in vacuum with described first vacuum chamber.
Below will describe in detail above-mentioned steps:
In step sl, the process of cleaning silicon chip can with reference to the cleaning of silicon chip in traditional silicon based hetero-junction solar cell processing procedure, it can comprise prerinse, cleans, chemical polishing, any one or several step in removal oxide.Silicon chip being cleaned and matte preparation, its objective is that can consult Fig. 2 (a), now the top of the suede structure of silicon chip surface has smooth mellow and full feature in order to obtain the clean silicon wafer of surface for pyramid suede structure.
After step S1 terminates, the silicon chip being placed in air is easy to oxidized generation such as natural oxidizing layer or other impurity such as organic substance, metal ion, when these pollutants are attached to the top of pyramid suede structure, the mellow and full top of its otherwise smooth will be made to become sharp-pointed nanometer-scale tips, as shown in Fig. 2 (b), add defect state density, be unfavorable for the preparation of follow-up amorphous silicon passivation layer, be therefore necessary the pollutant getting rid of these silicon chip surfaces.
In step s 2, provide the first vacuum chamber, for carrying out plasma etching to described silicon chip, its plasma source adopted is any one power source that gas activation can be become reactant and keep reactant plasmoid, such as, radio frequency (RF), direct current (DC), alternating current (AC) or microwave (MW) power discharge technology can be used.Preferably, radio frequency plasma body source can be adopted.Described plasma source can also use remote plasma source, namely again plasma is sent in treatment chamber produced the plasma of reactant by remote plasma generator after, described remote plasma generator can by such as MKSInstruments, and AdvancedEnergyIndustries Inc., etc. Inc. supplier provides, generally speaking, the ion energy produced due to remote plasma source is relatively little, so can avoid the damage that plasma produces because of bombardment silicon chip surface.
In the present invention, the process gas used in described plasma etching can be S
xf
y, any one or a few combination in NxFy, CxFy, CxHyFz, H2, Ar, O2, Cl2, Br2, after these process gass are ionized to plasma in the first vacuum chamber, it can be relied on to be peeled away from silicon chip by pollutant the bombardment of silicon chip surface pollutant.When described process gas comprises the fluoro-gas such as SxFy, NxFy, CxFy, CxHyFz, these fluoro-gas can be ionized to fluorine ion, and natural oxidizing layer (SiOx) or other pollutant generation chemical reaction, thus remove natural oxidizing layer or other pollutant better.When described process gas carries out plasma etching, the pollutant being positioned at suede structure bottom in Fig. 2 (b) is etched away, the sharp-pointed nano-scale structure being simultaneously positioned at suede structure top also can be etched away together, thus the smooth mellow and full pyramid suede structure recovered at the end of the above-mentioned first step, can Fig. 2 (c) be consulted.
Generally speaking, the natural oxidizing layer thickness that described silicon chip grows in an atmosphere, usually between 5-20A, although etching speed differs greatly according to technique difference, is generally 1-15A/s, and therefore the whole plasma etching time can control within 20s substantially.For different process conditions, its concrete etch period also can carry out by the following method: the silicon chip due to cleaning is hydrophobicity, and after silicon chip surface grows natural oxide or other impurity, silicon chip will become hydrophily, so etch period can be judged by the hydrophobicity of silicon chip, such as, after silicon chip is completely hydrophobic, can be extended 10-20% the process time again to come as etch period, the object done like this is to not damage pyramidal agent structure again more fully removing pollutant while.
As a rule, passivation layer quality can be judged by minority carrier life time, and name such as can be adopted to be called, and PhotoconductanceLifetimeTester minority carrier lifetime tester device (model SintonWCT-120) judges.Experiment records: in the clean room of 100,000 grades, constantly little when placing 0.5 after Wafer Cleaning in an atmosphere, silicon chip minority carrier life is 300-800us, and when we increase the processing step of plasma etching, such as with the mist of Ar/NF3 for process gas etches silicon chip, minority carrier life time can bring up to more than 1600us, the design parameter of above-mentioned experiment is: pressure limit is at 0.1-2mbar, plasma power density <200mw/cm2, process gas mol ratio row Ar/NF3=0-1, the vacuum requirement <0.5mbar of vacuum environment.
As can be seen here, the present invention carries out the method for plasma etching in the first vacuum chamber by adopting, can effectively remove silicon chip surface pollutant, improve passivation effect, and effective micro etch process can be carried out to the top of pyramid suede structure simultaneously, make the tip of its suede structure reproduce smooth mellow and full form, reduce defect state density, improve the growth quality of passivation layer.
In step s3, described second vacuum chamber is PECVD reaction chamber, and for the preparation of amorphous silicon passivation layer, described second vacuum chamber and the first vacuum chamber are bonding in vacuum relation, and the two is mutually isolated by the family of power and influence.Because concrete passivation layer preparation technology is identical with passivation layer preparation technology conventional in industry, be the knowledge that those skilled in the art know, so repeat no more herein.This bonding in vacuum of described second vacuum chamber and the first vacuum chamber can ensure that silicon chip can complete passivation layer technique after completing plasma etching under the condition of not vacuum breaker, avoids secondary pollution, contributes to obtaining high-quality passivation layer.
In a possibility, described first vacuum chamber and the second vacuum chamber can be same vacuum PECVD reaction chamber, namely in this PECVD reaction chamber, successively carry out plasma etching and passivation layer prepare these two kinds different PROCESS FOR TREATMENT, thus save equipment cost.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (8)
1. a silicon based hetero-junction solar cell inactivating layer earlier stage processing method, is characterized in that: the method comprises the following steps:
The first step, cleans silicon chip and matte preparation, to obtain the clean silicon wafer that surface is pyramid suede structure;
Second step, in the first vacuum chamber, plasma etching is carried out to described silicon chip, in order to remove the pollutant of described silicon chip surface and to enable the surface of described silicon chip recover the pyramid suede structure presented at the end of the above-mentioned first step, described pollutant comprises natural oxidizing layer and other impurity;
3rd step, carries out amorphous silicon passivation layer preparation to described silicon chip in the second vacuum chamber realizing bonding in vacuum with described first vacuum chamber.
2. according to a kind of silicon based hetero-junction solar cell inactivating layer earlier stage processing method shown in claim 1, it is characterized in that: described first vacuum chamber carrying out plasma etch process is same vacuum PECVD reaction chamber with carrying out described second vacuum chamber prepared by amorphous silicon passivation layer.
3. according to a kind of silicon based hetero-junction solar cell inactivating layer earlier stage processing method shown in claim 1, it is characterized in that: described first vacuum chamber carrying out plasma etch process is two different vacuum reaction chambers from carrying out described second vacuum chamber prepared by amorphous silicon passivation layer.
4. according to a kind of silicon based hetero-junction solar cell inactivating layer earlier stage processing method shown in claim 1, it is characterized in that: describedly cleaning is carried out to silicon chip comprise: prerinse, clean again, chemical polishing, any one or several step in removal oxide.
5. according to a kind of silicon based hetero-junction solar cell inactivating layer earlier stage processing method shown in claim 1, it is characterized in that: the plasma source of described plasma etching adopts and gas activation can be become reactant and any power source keeping reactant plasma.
6., according to a kind of silicon based hetero-junction solar cell inactivating layer earlier stage processing method shown in claim 1, it is characterized in that: the mode of described plasma etching can adopt remote plasma source to etch.
7., according to a kind of silicon based hetero-junction solar cell inactivating layer earlier stage processing method shown in claim 1, it is characterized in that: the process gas used in described plasma etching comprises fluoro-gas.
8. according to a kind of silicon based hetero-junction solar cell inactivating layer earlier stage processing method shown in claim 1, it is characterized in that: the process gas used in described plasma etching can be S
xf
y, N
xf
y, C
xf
y, C
xh
yf
z, H
2, A
r, O
2, Cl
2, Br
2in any one or a few combination.
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| CN201410196467.8A CN105097984A (en) | 2014-05-12 | 2014-05-12 | Silicon-based heterojunction solar cell passivation layer early stage processing method |
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| CN201410196467.8A CN105097984A (en) | 2014-05-12 | 2014-05-12 | Silicon-based heterojunction solar cell passivation layer early stage processing method |
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| CN105097984A true CN105097984A (en) | 2015-11-25 |
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ID=54578004
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108364866A (en) * | 2018-02-09 | 2018-08-03 | 信利（惠州）智能显示有限公司 | Amorphous silicon surfaces processing method and quasi-molecule laser annealing handle conveyer system |
| CN111312853A (en) * | 2019-12-31 | 2020-06-19 | 晋能光伏技术有限责任公司 | Film forming production process of heterojunction solar cell |
| CN114975650A (en) * | 2022-03-16 | 2022-08-30 | 江苏日托光伏科技股份有限公司 | Monocrystalline silicon pyramid and preparation method thereof |
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| US20070097383A1 (en) * | 2005-01-08 | 2007-05-03 | Nguyen Khiem K | Method and apparatus for integrating metrology with etch processing |
| CN102648533A (en) * | 2009-08-24 | 2012-08-22 | 综合工科学校 | Method of cleaning the surface of a silicon substrate |
| CN103022268A (en) * | 2011-09-22 | 2013-04-03 | 理想能源设备(上海)有限公司 | Method for manufacturing silicon-based thin-film solar cell and device for manufacturing same |
| CN103390682A (en) * | 2012-05-07 | 2013-11-13 | 吉富新能源科技(上海)有限公司 | Plasma clean heterojunction monocrystalline silicon thin-film solar cell |
-
2014
- 2014-05-12 CN CN201410196467.8A patent/CN105097984A/en active Pending
Patent Citations (4)
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| US20070097383A1 (en) * | 2005-01-08 | 2007-05-03 | Nguyen Khiem K | Method and apparatus for integrating metrology with etch processing |
| CN102648533A (en) * | 2009-08-24 | 2012-08-22 | 综合工科学校 | Method of cleaning the surface of a silicon substrate |
| CN103022268A (en) * | 2011-09-22 | 2013-04-03 | 理想能源设备(上海)有限公司 | Method for manufacturing silicon-based thin-film solar cell and device for manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108364866A (en) * | 2018-02-09 | 2018-08-03 | 信利（惠州）智能显示有限公司 | Amorphous silicon surfaces processing method and quasi-molecule laser annealing handle conveyer system |
| CN108364866B (en) * | 2018-02-09 | 2020-10-09 | 信利（惠州）智能显示有限公司 | Amorphous silicon surface treatment method |
| CN111312853A (en) * | 2019-12-31 | 2020-06-19 | 晋能光伏技术有限责任公司 | Film forming production process of heterojunction solar cell |
| CN114975650A (en) * | 2022-03-16 | 2022-08-30 | 江苏日托光伏科技股份有限公司 | Monocrystalline silicon pyramid and preparation method thereof |
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