CN105097700B - A kind of preparation method of semiconductor devices - Google Patents
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- CN105097700B CN105097700B CN201410166999.7A CN201410166999A CN105097700B CN 105097700 B CN105097700 B CN 105097700B CN 201410166999 A CN201410166999 A CN 201410166999A CN 105097700 B CN105097700 B CN 105097700B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000011248 coating agent Substances 0.000 claims abstract description 32
- 238000000576 coating method Methods 0.000 claims abstract description 32
- 238000001020 plasma etching Methods 0.000 claims abstract description 26
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 24
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- CEPICIBPGDWCRU-UHFFFAOYSA-N [Si].[Hf] Chemical compound [Si].[Hf] CEPICIBPGDWCRU-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical group [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 3
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 3
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- PDKGWPFVRLGFBG-UHFFFAOYSA-N hafnium(4+) oxygen(2-) silicon(4+) Chemical compound [O-2].[Hf+4].[Si+4].[O-2].[O-2].[O-2] PDKGWPFVRLGFBG-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 description 7
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
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- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
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- 238000000059 patterning Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Inorganic materials [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 description 1
- CSSYLTMKCUORDA-UHFFFAOYSA-N barium(2+);oxygen(2-) Chemical compound [O-2].[Ba+2] CSSYLTMKCUORDA-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
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- 238000001514 detection method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 229960002163 hydrogen peroxide Drugs 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
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- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Drying Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention proposes a kind of preparation method of semiconductor devices, including：Semiconductor substrate is provided；It is formed with isolation structure in the semiconductor substrate, semiconductor substrate is divided into the first device region and the second device region；High k dielectric layer, coating, dummy gate layer, hard mask layer are sequentially formed on a semiconductor substrate；The graphical high k dielectric layer, coating, dummy gate layer, hard mask layer, to form the first dummy gate structure and the second dummy gate structure；Offset side wall is formed on the side wall of first dummy gate structure and the second dummy gate structure；Plasma etching is executed to remove remaining coating and high k dielectric layer.The method provided according to the present invention does not influence the performance of semiconductor devices while efficiently solving the bridging and short circuit problem in semiconductor devices, to be obviously improved the yields of device.
Description
Technical field
The present invention relates to semiconductor fabrication process more particularly to a kind of preparation methods of semiconductor devices.
Background technology
In conventional SRAM device manufacturing technology, by pattern sedimentation in the high k dielectric layer of semiconductor substrate, covering
Layer, dummy gate layer, hard mask layer are respectively formed multiple dummy gate structures.In patterning process, what is pulled up transistor is virtual
The CD at the dummy gate structure interval of gate structure and transmission gate transistor is random less than normal (usually by mask error and photoetching exposure
Caused by optical path difference), therefore the process window smaller etched, it will cause often to remain coating in high k dielectric layer.And by
In the covering of residual coating, it is unfavorable for completely removing high k dielectric layer in subsequent step, it will form coating/high k dielectric
Layer (such as TiN/HfO2) residual.And the residual is difficult to be arrived by common Defect Scanning or electron beam Scanning Detction, therefore
The presence that can not avoid bridging and short circuit problem in semiconductor devices, to reduce the yields of device.To solve this problem,
The method of over etching coating/high k dielectric layer is used to remove its residual in the prior art, but over etching can be damaged and half-and-half be led again
Critically important coating/high k dielectric layer profile for body core devices.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to solve the problems in the existing technology, the present invention proposes a kind of preparation method of semiconductor devices, packet
It includes：Semiconductor substrate is provided；It is formed with isolation structure in the semiconductor substrate, semiconductor substrate is divided into the first device region and
Two device regions；High k dielectric layer, coating, dummy gate layer, hard mask layer are sequentially formed on a semiconductor substrate；It is graphical described
High k dielectric layer, coating, dummy gate layer, hard mask layer, to form the first dummy gate structure and the second dummy gate structure；
Offset side wall is formed on the side wall of first dummy gate structure and the second dummy gate structure；Execute plasma etching with
Remove remaining coating and high k dielectric layer.
In one embodiment, it is cleaned using DHF after the plasma etching.
In one embodiment, it is cleaned using DHF before the plasma etching, and is made after the plasma etching
It is cleaned with SC-1 solution.
In one embodiment, the gas that the plasma etching uses is HBr/O2Or Cl2/O2。
In one embodiment, the semiconductor devices is SRAM.
In one embodiment, the material of the high k dielectric layer be hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana,
One of zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide or its group
It closes.
In one embodiment, the material of the coating includes metal or metal nitride.
In one embodiment, the material of the coating is titanium nitride.
In one embodiment, the material of the dummy gate layer is polysilicon.
In one embodiment, the material of the hard mask layer is silicon nitride.
The method provided according to the present invention prepares semiconductor devices, the advantage is that：(1) LDD after offset side wall is formed
A plasma etching industrial is executed before injection, can fully be removed between the first dummy gate structure and the second dummy gate structure
Every interior remaining coating and high k dielectric layer；(2) there is higher selectivity to oxide due to plasma etching, it can
Keep the loss good, and that semiconductor substrate (such as silicon substrate) will not be caused excessive of profile of coating and high k dielectric layer；
(3) performance for not influencing semiconductor devices while efficiently solving the bridging and short circuit problem in semiconductor devices, from
And it is obviously improved the yields of device.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.In the accompanying drawings,
Fig. 1 a, 2a, 3a are each step in the technological process according to the making semiconductor devices of one embodiment of the present invention
The sectional view of the device obtained；
Fig. 1 b, the directions the AA sectional view that 2b, 3b are corresponding diagram 1a, 2a, 3a；
Fig. 4 is the flow chart according to the making semiconductor devices of one embodiment of the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to reality without one or more of these details
It applies.In other examples, in order to avoid obscuring with the present invention, some technical characteristics well known in the art are not carried out
Description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate of the present invention half
The preparation method of conductor device.Obviously, execution of the invention be not limited to semiconductor applications technical staff be familiar with it is special
Details.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can also have other
Embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in the present specification
When, indicate that there are the feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of one or more
Other a features, entirety, step, operation, element, component and/or combination thereof.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Element or layer between two parties may be present.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.
Now, exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Apply example can many different forms implement, and should not be construed to be limited solely to the embodiments set forth herein.It should manage
These embodiments that are to provide of solution are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary embodiments
Design be fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated
Degree, and make that identical element is presented with like reference characters, thus description of them will be omitted.
Fig. 4 is the flow chart that semiconductor devices (such as SRAM) is prepared according to one embodiment of the present invention, Fig. 1 a, 2a,
3a is obtained for each step in preparing the technological process of semiconductor devices (such as SRAM) according to one embodiment of the present invention
The sectional view of device, Fig. 1 b, the directions the AA sectional view that 2b, 3b are corresponding diagram 1a, 2a, 3a.Below in conjunction with Fig. 4 and Fig. 1 a-3b
Carry out the method that the present invention will be described in detail.
Step 301 is executed, semiconductor substrate 100 is provided, as illustrated in figs. 1A and ib, the composition material of semiconductor substrate 100
Undoped monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc. can be used in material.As an example, in this implementation
In example, the constituent material of semiconductor substrate 100 selects monocrystalline silicon.
Step 302 is executed, forms isolation structure 110 in semiconductor substrate 100, as an example, isolation structure 110 is shallow
Trench isolations (STI) structure or selective oxidation silicon (LOCOS) isolation structure, isolation structure 110, which divides semiconductor substrate 100, is
First device (such as pulling up transistor) area and the second device (such as transmission gate transistor) area.
Step 303 is executed, sequentially forms high k dielectric layer 201, coating 202, dummy gate layer on a semiconductor substrate 100
203, hard mask layer 204.The material of high k dielectric layer 201 includes material, metal oxide or its combination containing hafnium, such as is aoxidized
Hafnium, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide
One or a combination set of titanium, strontium oxide strontia titanium, aluminium oxide.It is hafnium oxide (HfO in the present embodiment2).The material of coating 202 includes
Metal or metal nitride are in the present embodiment titanium nitride (TiN).The material of dummy gate layer 203 is more in the present embodiment
Crystal silicon.The material of hard mask layer 204 can be nitride or other composite layers with laminated construction, be in the present embodiment nitrogen
SiClx (SiN).It forms above layers and the various suitable techniques that those skilled in the art are familiar with, such as chemical gaseous phase can be used
Depositing operation or physical gas-phase deposition.It should be noted that can between high k dielectric layer 201 and semiconductor substrate 100
A boundary layer is formed, to improve the interfacial characteristics between high k dielectric layer 201 and semiconductor substrate 100.
Step 304 is executed, graphically the high k dielectric layer 201, coating 202, dummy gate layer 203, hard mask layer 204,
To form the first dummy gate structure 210 and the second dummy gate structure 220, wherein the first dummy gate structure 210 is located at institute
The first device region is stated, the second dummy gate structure 220 is located at second device region, the first dummy gate structure 210 and second
Dummy gate structure 220 is located at interval at 110 top of isolation structure.Specifically, figure is formed first on the hard mask layer 204
The photoresist layer of case, the photoresist layer define the pattern of each dummy gate structure.Then with the photoresist layer
For mask, the hard mask layer 204 is etched, is transferred a pattern in the hard mask layer 204, later with the methods of ashing removal
Photoresist layer.Then with the hard mask layer 204 it is again mask, is sequentially etched dummy gate layer 203, coating 202, high k dielectric
Layer 201, but retain the high k dielectric layer 201 on isolation structure 110.Preferably, hard mask layer is etched using dry etch process
204, dummy gate layer 203, coating 202, high k dielectric layer 201, the dry etch process include but not limited to：Reactive ion is carved
Lose (RIE), ion beam etching, plasma etching or laser ablation.Single lithographic method can be used, or can also be used
More than one lithographic method.Such as endpoint Detection can be used in this step or control the method for etch period to control
Etching terminal processed can avoid follow-up so that 201 surface of high k dielectric layer of the dry etch process on isolation structure 110 stops
Destruction of the wet-etching technology to isolation structure 110.In patterning process, the first dummy gate structure 210 and second is empty
The CD that quasi- gate structure 220 is spaced is less than normal at random, and the process window smaller of etching is easy to form coating in subsequent step
202/ high k dielectric layer 201 (such as TiN/HfO2) residual.
Step 305 is executed, as shown in Figure 2 a and 2 b, in first dummy gate structure, 210 and second dummy gate
Offset side wall 205 is formed on the side wall of structure 220.Specifically, first in the semiconductor substrate 100, high k dielectric layer 201,
Side-wall material layer (not shown) is formed in one dummy gate structure 210, the second dummy gate structure 220, then etched sidewall material
The bed of material deviates side wall 205 to be formed.The material for deviating side wall 205 is, for example, silicon nitride, the insulation such as silica or silicon oxynitride
Material.It forms side-wall material layer and the various suitable techniques that those skilled in the art are familiar with, etched sidewall material layer can be used
Can be used any traditional deep dry etch process, for example, reactive ion etching, ion beam etching, plasma etching, laser ablation or
The arbitrary combination of these methods of person.Single lithographic method can be used, or more than one lithographic method can also be used.
Step 306 is executed, as shown in Figure 3a and Figure 3b shows, executes plasma etching to remove remaining coating 202 and high k
Dielectric layer 201.In the present embodiment, the gas that plasma etching uses is HBr/O2Or Cl2/O2, HBr or Cl2With O2Flow
Than for 30-50sccm:30-50sccm, power 100-1000W, pressure 2-10mTorr.The etching is exposing semiconductor
It is terminated when substrate 100, in order to avoid semiconductor substrate 100 is caused to damage.Specifically, (diluted using DHF before plasma etching
Hydrofluoric acid) it is cleaned to remove the foreign substance stayed on the surface of a substrate, and SC-1 solution (ammonia is used after plasma etching
The mixed liquor of solution/hydrogenperoxide steam generator) it is cleaned to remove the particle left by plasma etching.Selectively, only exist
It is cleaned using DHF to remove the foreign substance and particle that stay on the surface of a substrate after plasma etching.
So far, whole processing steps that method according to an exemplary embodiment of the present invention is implemented are completed.Next, can lead to
The making that subsequent technique completes entire semiconductor devices is crossed, the subsequent technique and traditional process for fabricating semiconductor device are complete
Identical, details are not described herein.
In order to solve the problems in the existing technology, the method provided according to the present invention prepares semiconductor devices, excellent
Point is：(1) plasma etching industrial is executed before LDD injections after offset side wall is formed, it is virtual can fully removes first
Remaining coating and high k dielectric layer in the interval of gate structure and the second dummy gate structure；(2) due to plasma etching pair
Oxide has higher selectivity, therefore coating and the profile of high k dielectric layer can be kept good, and will not lead to semiconductor
The excessive loss of substrate (such as silicon substrate)；(3) the same of bridging in semiconductor devices and short circuit problem is being efficiently solved
When do not influence the performance of semiconductor devices, to be obviously improved the yields of device.
Fig. 4 is the process flow chart according to one embodiment of the present invention, includes specifically：
Step 301, semiconductor substrate is provided；
Step 302, it is formed with isolation structure in the semiconductor substrate, semiconductor substrate is divided into the first device region and second
Device region；
Step 303, high k dielectric layer, coating, dummy gate layer, hard mask layer are sequentially formed on a semiconductor substrate；
Step 304, the graphical high k dielectric layer, coating, dummy gate layer, hard mask layer, to form the first virtual grid
Pole structure and the second dummy gate structure；
Step 305, offset side wall is formed on the side wall of first dummy gate structure and the second dummy gate structure；
Step 306, plasma etching is executed to remove remaining coating and high k dielectric layer.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
For member it will be appreciated that the invention is not limited in above-described embodiment, introduction according to the present invention can also make more kinds of modifications
And modification, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention is by attached
Claims and its equivalent scope defined.
Claims (9)
1. a kind of preparation method of SRAM semiconductor devices, including：
Semiconductor substrate is provided；
It is formed with isolation structure in the semiconductor substrate, semiconductor substrate is divided into the first device region and the second device region；
High k dielectric layer, coating, dummy gate layer, hard mask layer are sequentially formed on a semiconductor substrate；
The graphical high k dielectric layer, coating, dummy gate layer, hard mask layer, to form the first dummy gate structure and second
Dummy gate structure；
Offset side wall is formed on the side wall of first dummy gate structure and the second dummy gate structure；
It executes residual in interval of the plasma etching to remove first dummy gate structure and second dummy gate structure
The coating stayed and high k dielectric layer.
2. according to the method described in claim 1, it is characterized in that, being cleaned using DHF after the plasma etching.
3. according to the method described in claim 1, it is characterized in that, cleaned using DHF before the plasma etching, and
It is cleaned using SC-1 solution after the plasma etching.
4. according to the method described in claim 1, it is characterized in that, the plasma etching uses gas for HBr/O2Or Cl2/
O2。
5. according to the method described in claim 1, it is characterized in that, the material of the high k dielectric layer is hafnium oxide, hafnium oxide
Silicon, nitrogen oxidation hafnium silicon, lanthana, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia
One or a combination set of titanium, aluminium oxide.
6. according to the method described in claim 1, it is characterized in that, the material of the coating includes metal or nitride metal
Object.
7. according to the method described in claim 6, it is characterized in that, the material of the coating is titanium nitride.
8. according to the method described in claim 1, it is characterized in that, the material of the dummy gate layer is polysilicon.
9. according to the method described in claim 1, it is characterized in that, the material of the hard mask layer is silicon nitride.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410166999.7A CN105097700B (en) | 2014-04-24 | 2014-04-24 | A kind of preparation method of semiconductor devices |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410166999.7A CN105097700B (en) | 2014-04-24 | 2014-04-24 | A kind of preparation method of semiconductor devices |
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| Publication Number | Publication Date |
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| CN105097700A CN105097700A (en) | 2015-11-25 |
| CN105097700B true CN105097700B (en) | 2018-07-20 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040007561A1 (en) * | 2002-07-12 | 2004-01-15 | Applied Materials, Inc. | Method for plasma etching of high-K dielectric materials |
| JP4727170B2 (en) * | 2004-06-23 | 2011-07-20 | 東京エレクトロン株式会社 | Plasma processing method and post-processing method |
| US7550337B2 (en) * | 2007-06-07 | 2009-06-23 | International Business Machines Corporation | Dual gate dielectric SRAM |
| US7728392B2 (en) * | 2008-01-03 | 2010-06-01 | International Business Machines Corporation | SRAM device structure including same band gap transistors having gate stacks with high-K dielectrics and same work function |
| US8357617B2 (en) * | 2008-08-22 | 2013-01-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of patterning a metal gate of semiconductor device |
| JP5713808B2 (en) * | 2010-07-09 | 2015-05-07 | 東京エレクトロン株式会社 | Plasma processing method and semiconductor device manufacturing method |
| JP2012146891A (en) * | 2011-01-14 | 2012-08-02 | Sony Corp | Method for manufacturing semiconductor device |
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