CN105097558A - Chip packaging structure and manufacture method thereof, and chip packaging substrate - Google Patents

Abstract

A method for manufacturing a chip packaging structure, comprising the steps of: providing a carrier board, forming a first conductive circuit layer, a first dielectric layer, and a second conductive circuit layer sequentially on at least one side of the carrier board, and the first conductive circuit layer The circuit layer and the second conductive circuit layer are electrically connected through a plurality of first conductive columns; a second dielectric layer is formed on the side of the second conductive circuit layer away from the carrier board, and the second dielectric layer A plurality of second dielectric layer openings are formed in the layer, and a plurality of second conductive pillars are formed in the openings of the second dielectric layer by electroplating, wherein the second conductive circuit layer is in phase with the second conductive pillars. electrical connection, the surface of the second conductive column away from the first dielectric layer is approximately flush with the surface of the second dielectric layer away from the first dielectric layer; remove the carrier board and solder A chip, thereby forming the chip package structure. The invention also relates to a chip packaging substrate and structure.

Description

Chip packaging structure, manufacturing method and chip packaging substrate

technical field

The invention relates to the field of circuit board manufacturing, in particular to a chip packaging structure, a manufacturing method and a chip packaging substrate.

Background technique

The chip packaging substrate can provide the chip with electrical connection, protection, support, heat dissipation, assembly and other functions to achieve multi-pin, reduce the size of packaged products, improve electrical performance and heat dissipation, ultra-high density or multi-chip modularization. Generally, the chip packaging substrate forms an opening in the solder resist layer on the side where the chip is placed, so as to expose the solder pads, so that solder balls can be formed on the surface of the solder pads and soldered to the chip. Under the demand of high-density wiring, the line is getting thinner and thinner, and the opening of the solder mask is getting smaller and smaller, so the size of the pad defined by the opening of the solder mask is getting smaller and smaller, so that poor soldering occurs frequently. On the one hand, solder balls are not easy to fill into the opening of the solder mask, which will cause empty soldering. On the other hand, the diameter of the solder ball becomes smaller as the size of the solder mask opening becomes smaller, so that the soldering height is insufficient, resulting in a gap between the chip and the package substrate. The distance is not enough, it is difficult to fill the encapsulant, which leads to the fact that the chip cannot be firmly packaged on the package substrate.

Contents of the invention

Therefore, it is necessary to provide a chip packaging structure, a manufacturing method and a chip packaging substrate capable of improving welding yield.

A method for manufacturing a chip packaging structure, comprising the steps of: providing a carrier board, and sequentially forming a first conductive circuit layer, a first dielectric layer, and a second conductive circuit layer on at least one side of the carrier board, wherein the first A plurality of first dielectric layer openings are formed in a dielectric layer, a plurality of first conductive columns are formed in the first dielectric layer openings, the first conductive circuit layer and the The second conductive circuit layer is electrically connected through a plurality of first conductive columns; a second dielectric layer is formed on the side of the second conductive circuit layer away from the carrier board, and a second dielectric layer is formed in the second dielectric layer. There are a plurality of openings in the second dielectric layer; electroplating forms a plurality of second conductive pillars in the openings of the second dielectric layer, wherein the second conductive circuit layer is electrically connected to the second conductive pillars, the The surface of the second conductive column away from the first dielectric layer is approximately flush with the surface of the second dielectric layer away from the first dielectric layer; the carrier board is removed; and in each of the forming a first solder ball on the surface of the second conductive pillar away from the first conductive circuit layer; and soldering a chip on the surface of the plurality of first solder balls, so that the chip is electrically connected to the second conductive pillar, Thus forming the chip packaging structure.

A method for manufacturing a chip packaging structure, comprising the steps of: providing a carrier board, and sequentially forming a first conductive circuit layer, a first dielectric layer, and a second conductive circuit layer on at least one side of the carrier board, wherein the first A plurality of first dielectric layer openings are formed in a dielectric layer, a plurality of first conductive columns are formed in the first dielectric layer openings, the first conductive circuit layer and the The second conductive circuit layer is electrically connected through a plurality of first conductive columns; electroplating forms a plurality of second conductive columns on the surface of the second conductive circuit layer, and the second conductive circuit layer is connected to the second conductive circuit layer. The column phases are electrically connected; a second dielectric layer is formed on the side of the second conductive circuit layer away from the carrier board, and a plurality of second dielectric layer openings are formed in the second dielectric layer, wherein the The plurality of second conductive pillars are all formed in the opening of the second dielectric layer, the surface of the second conductive pillars away from the first dielectric layer is the same as the surface of the second dielectric layer far away from the first dielectric layer. The surface of the dielectric layer is substantially flush; the carrier plate is removed; a first solder ball is formed on the surface of each of the second conductive pillars away from the first conductive circuit layer; A chip is welded on the surface of the solder ball, so that the chip is electrically connected to the second conductive column, thereby forming the chip packaging structure.

A chip packaging structure includes a first dielectric layer, a first conductive circuit layer, a second conductive circuit layer, a second dielectric layer, a plurality of second conductive pillars and at least one chip. The first dielectric layer includes opposite first and second surfaces. The first conductive circuit layer is formed on the first surface of the first dielectric layer and embedded in the first dielectric layer, and the first conductive circuit layer is away from the surface of the second surface flush with the first surface. The second conductive circuit layer is formed on the second surface, and the second conductive circuit layer is electrically connected to the first conductive circuit layer through a plurality of first conductive columns. The second dielectric layer is formed on the second surface and the surface of the second conductive circuit layer. The second dielectric layer is provided with a plurality of second dielectric layer openings. The plurality of second conductive columns are formed in the opening of the second dielectric layer by electroplating, the plurality of second conductive columns are electrically connected to the second conductive circuit layer, and the second conductive columns A surface away from the first dielectric layer is substantially flush with a surface of the second dielectric layer away from the first dielectric layer. The chip is electrically connected to the second conductive column through a plurality of first solder balls.

A chip package substrate, including a first dielectric layer, a first conductive circuit layer, a second conductive circuit layer, a second dielectric layer, and a plurality of second conductive columns. The first dielectric layer includes opposite first and second surfaces. The first conductive circuit layer is formed on the first surface of the first dielectric layer and embedded in the first dielectric layer, and the first conductive circuit layer is away from the surface of the second surface flush with the first surface. The second conductive circuit layer is formed on the second surface, and the second conductive circuit layer is electrically connected to the first conductive circuit layer through a plurality of first conductive columns. The second dielectric layer is formed on the second surface and the surface of the second conductive circuit layer. The second dielectric layer is provided with a plurality of second dielectric layer openings. The plurality of second conductive columns are formed in the opening of the second dielectric layer by electroplating, the plurality of second conductive columns are electrically connected to the second conductive circuit layer, and the second conductive columns A surface away from the first dielectric layer is substantially flush with a surface of the second dielectric layer away from the first dielectric layer.

Compared with the prior art, in the embodiment of the present invention, the distance between the surface of the chip package structure, its manufacturing method and the surface of the second conductive pillar of the chip package substrate far away from the first dielectric layer and the distance from the second dielectric layer is The surface of the first dielectric layer is substantially flush with each other. Therefore, when solder balls are formed on the surface of the second conductive pillars and bonded to the chip, the solder balls do not need to fill the openings of the solder resist layer. Therefore, it is difficult for empty soldering to occur, and the solder balls The height is the distance between the bottom of the chip and the packaging substrate, so that the distance between the bottom of the chip and the packaging substrate is enough to fill the packaging gel, so that the chip can be firmly packaged on the packaging substrate, that is, the chip package in this case The structure, its manufacturing method and chip packaging substrate can improve the welding yield; further, in this case, the coreless chip packaging structure and chip packaging substrate are formed by using the carrier board, which can be made thinner.

Description of drawings

FIG. 1 is a cross-sectional view of a chip package structure provided by a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a second embodiment of the present invention after bonding copper foil on a carrier board.

FIG. 3 is a cross-sectional view of the copper foil in FIG. 2 after forming a first conductive circuit layer.

FIG. 4 is a cross-sectional view after forming a first dielectric layer on the surface of the first conductive circuit layer in FIG. 3 .

FIG. 5 is a cross-sectional view after forming a first patterned photoresist layer on the surface of the first dielectric layer in FIG. 4 .

FIG. 6 is a cross-sectional view after forming a first conductive pillar in the first dielectric layer in FIG. 5 and forming a second conductive circuit layer on the surface of the first dielectric layer.

FIG. 7 is a cross-sectional view after removing the first patterned photoresist layer in FIG. 6 .

FIG. 8 is a cross-sectional view after forming a second dielectric layer and forming an opening in the second dielectric layer on the surface of the second conductive circuit layer in FIG. 7 .

FIG. 9 is a schematic diagram of forming a second dielectric layer by injection molding on the surface of the second conductive circuit layer in FIG. 7 .

FIG. 10 is a cross-sectional view after forming a second conductive pillar in the opening of the second dielectric layer in FIG. 8 .

FIG. 11 is a schematic diagram of removing the carrier plate 110 in FIG. 10 to form two chip packaging substrates.

FIG. 12 is a cross-sectional view after forming a solder resist layer on the surface of the first conductive circuit layer of the chip package substrate in FIG. 11 .

13 is a cross-sectional view of the third embodiment of the present application after forming a first patterned photoresist layer on the surface of the first dielectric layer similar to that in FIG. 4 of the second embodiment, and forming a first conductive column and a second conductive circuit layer.

FIG. 14 is a cross-sectional view after forming a second patterned photoresist layer and forming second conductive pillars on the surface of the first patterned photoresist layer in FIG. 13 .

FIG. 15 is a cross-sectional view after removing the first and second patterned photoresist layers in FIG. 14 .

FIG. 16 is a cross-sectional view after forming a second dielectric layer on the side of the second conductive pillar in FIG. 15 .

FIG. 17 is a cross-sectional view after grinding the second dielectric layer in FIG. 16 to expose the second conductive pillars.

Explanation of main component symbols

Chip Package Structure 100

first dielectric layer 126,926

first surface 1261

second surface 1262

The first conductive circuit layer 124, 924

Second conductive circuit layer 134,934

The first conductive pillar 132, 932

Second dielectric layer 136, 936

Second dielectric opening 138, 938

The second conductive pillar 140, 940

chip 148

1st ball 150

Encapsulation colloid 154

Solder Mask 142

Solder mask opening 144

Pad 146

Second solder ball 152

Carrier plate 110, 910

Copper foil 120

First dielectric opening 128, 928

First circuit board intermediate 200,900

The first patterned photoresist layer 130, 930

Mold 300

Cavity 310

Glue injection channel 320

Second circuit board intermediate 210, 901

The second patterned photoresist layer 960

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

Detailed ways

Please refer to FIG. 1 , the first embodiment of the present invention provides a chip packaging structure 100, including: a first dielectric layer 126, the first dielectric layer 126 includes a first surface 1261 and a second surface 1262 opposite to each other; A first conductive circuit layer 124, the first conductive circuit layer 124 is formed on the first surface 1261 of the first dielectric layer 126 and embedded in the first dielectric layer 126, and the first A surface of a conductive circuit layer 124 away from the second surface 1262 is flush with the first surface 1261; a second conductive circuit layer 134, the second conductive circuit layer 134 is formed on the second surface 1262, The second conductive circuit layer 134 is electrically connected to the first conductive circuit layer 124 through a plurality of first conductive columns 132; a second dielectric layer 136 is formed on the first conductive circuit layer 136 The two surfaces 1262 and the surface of the second conductive circuit layer 134, the second dielectric layer 136 is provided with a plurality of second dielectric layer openings 138, part of the second conductive circuit layer 134 from the second dielectric layer The electrical layer opening 138 is exposed; a plurality of second conductive columns 140, the plurality of second conductive columns 140 are formed in the second dielectric layer opening 138, and are all in phase with the second conductive circuit layer 134 Electrical connection; at least one chip 148, the chip 148 is electrically connected to the second conductive column 140 through a plurality of first solder balls 150, and the side and bottom of the chip 148 are formed with encapsulant 154; a solder resist layer 142, the solder resist layer 142 is formed on the first surface 1261 and the surface of the first conductive circuit layer 124, the solder resist layer 142 is formed with a solder resist layer opening 144, part of the first conductive circuit layer 124 is formed from The solder mask opening 144 is exposed to form a plurality of solder pads 146 for electrical connection with other circuit boards, and second solder balls 152 are formed on the surface of the solder pads 146 .

In this embodiment, the plurality of first conductive pillars 132 are approximately in the shape of a truncated cone; the plurality of first conductive pillars 132, the second conductive pillars 140 and the second conductive circuit layer 134 are all formed by electroplating; A surface of the second conductive pillar 140 away from the first dielectric layer 126 is substantially flush with a surface of the second dielectric layer 136 away from the first dielectric layer 126 .

Referring to FIGS. 2-14, the second embodiment of the present invention provides a method for manufacturing the above-mentioned chip packaging structure 100, including the following steps:

The first step, referring to FIG. 2 , is to provide a carrier board 110 , and attach a copper foil 120 to opposite sides of the carrier board 110 respectively.

The carrying board 110 is flat. The carrying plate 110 may be a rigid supporting material such as a resin plate, a ceramic plate, or a metal plate. In this embodiment, the carrier board 110 is a double-sided copper-clad substrate.

In this embodiment, the two copper foils 120 are attached to opposite sides of the carrier board 110 through a thermoplastic colloid layer 122 respectively. Wherein, the reason for using thermoplastic colloid to bond the copper foil is to facilitate removal of the carrier board 110 in subsequent steps.

The second step, please refer to FIG. 3 , is to fabricate the copper foils 120 on both sides to form the first conductive circuit layer 124 .

In this embodiment, the first conductive circuit layer 124 is formed by an image transfer process and an etching process.

In the third step, please refer to FIG. 4, a first dielectric layer 126 is formed on the side of each layer of the first conductive circuit layer 124 away from the carrier board 110, and a first dielectric layer 126 is formed on the two layers of the first dielectric layer 124. A plurality of first dielectric layer openings 128 are formed on each layer 126 to expose a portion of the first conductive circuit layer 124 .

In this embodiment, firstly, the first dielectric layer 126 is formed by attaching a film on the side of each layer of the first conductive circuit layer 124 away from the carrier board 110 and curing the film by thermocompression, The first dielectric layer 126 covers the first conductive circuit layer 124 and the thermoplastic colloid layer 122 exposed from the first conductive circuit layer 124; after that, the first dielectric layer is formed by laser etching. A plurality of first dielectric layer openings 128 are formed on the electrical layer 126 , so that part of the first conductive circuit layer 124 is exposed from the first dielectric layer openings 128 .

The fourth step, referring to FIGS. 5-7 , is to form a first conductive column 132 in each opening 128 of the first dielectric layer, and form a second conductive line on a part of the surface of the first dielectric layer 126 Layer 134, so that the first conductive circuit layer 124 and the second conductive circuit layer 134 on the same side of the carrier board 110 are electrically connected through the first conductive column 132 on the same side, thereby obtaining a first Circuit board intermediate 200.

In this embodiment, the first conductive pillar 132 and the second conductive circuit layer 134 are formed simultaneously by selective electroplating.

Specifically, first, referring to FIG. 5 , a first patterned photoresist layer 130 is formed on the surfaces of the first dielectric layer 126 on both sides, wherein, all the openings 128 around each first dielectric layer The first dielectric layer 126 is exposed in the first patterned photoresist layer 130; then, referring to FIG. A conductive column 132, and the surface of the first dielectric layer 126 exposed from the first patterned photoresist layer 130 is covered with an electroplated metal material to form a second conductive circuit layer 134; after that, please refer to FIG. 7, remove The first patterned photoresist layer 130 .

The fifth step, referring to FIG. 8 , is to form a second dielectric layer 136 on the side away from the carrier board 110 of each layer of the second conductive circuit layer 134 , and form a second dielectric layer 136 on two layers of the second dielectric layer 136 . A plurality of openings 138 in the second dielectric layer are formed on each of them to expose part of the second conductive circuit layer 134 .

In this embodiment, firstly, the second dielectric layer 136 is formed by attaching a film on the side of each layer of the second conductive circuit layer 134 away from the carrier board 110 and curing the film by thermocompression; Then, the second dielectric layer opening 138 is formed on the second dielectric layer 136 by laser etching, so that part of the second conductive circuit layer 134 is removed from the second dielectric layer opening 138 exposed.

In other embodiments, the second dielectric layer 136 can also be formed by injection molding, specifically: please refer to FIG. The glue channel 320 accommodates the first circuit board intermediate 200 in the mold cavity 310, and the side of each layer of the second conductive circuit layer 134 away from the carrier board 110 has a gap relative to the mold Then, inject glue into the mold cavity 310 through the glue injection channel 320; then, solidify the glue so that the glue is coated on the second conductive surface on the opposite sides of the first circuit board intermediate body 200 The surface of the circuit layer 134 and the surface of the first dielectric layer 126 covered in the second conductive circuit layer 134, so that the colloid becomes the second dielectric layer 136; after that, it will be covered with the second dielectric layer The first circuit board intermediate 200 of the electrical layer 136 can be taken out from the mold cavity to perform subsequent processing on the second dielectric layer 136 , including forming the second dielectric layer opening 138 .

In addition, the second dielectric layer 136 can also be formed by using a photosensitive material. In this case, the opening 138 of the second dielectric layer is formed by exposure and development.

The sixth step, referring to FIG. 10 , is to form a second conductive column 140 in each opening 138 of the second dielectric layer, thereby obtaining a second circuit board intermediate 210, wherein, the same as the carrier board 110 The second conductive circuit layer 134 on the side is electrically connected to the second conductive pillar 140 .

In this embodiment, the second conductive pillars 140 are formed by electroplating. Preferably, the electroplating makes the surface of the second conductive pillar 140 away from the carrier board 110 substantially flush with the surface of the second dielectric layer 136 away from the carrier board 110 . The material of the second conductive pillar 140 can be copper, tin or a combination of both. Of course, after electroplating, the surface of the second conductive pillar 140 away from the carrier board 110 may also be roughly aligned with the surface of the second dielectric layer 136 away from the carrier board 110 by grinding or etching. flat.

The seventh step, please refer to FIG. 11 , is to separate and remove the carrier board 110 and the two thermoplastic colloid layers 122 from the second circuit board intermediate 210 to obtain two chip package substrates 220 .

In this embodiment, the second circuit board intermediate 210 is heated to the melting point of the thermoplastic colloid layer 122, and then the carrier board 110 and the two thermoplastic colloid layers 122 are separated from the second circuit board intermediary 210. remove.

Each of the chip packaging substrates 220 includes: a first dielectric layer 126, the first dielectric layer 126 includes an opposite first surface 1261 and a second surface 1262; a first conductive circuit layer 124, the The first conductive circuit layer 124 is formed on the first surface 1261 of the first dielectric layer 126 and embedded in the first dielectric layer 126, and because the first conductive circuit layer 124 and the The first dielectric layer 126 is formed on the basis of the carrier board 110 and adheres to the carrier board 110, so the surface of the first conductive circuit layer 124 away from the second surface 1262 is in contact with the second surface 1262. A surface 1261 is flush; a second conductive circuit layer 134, the second conductive circuit layer 134 is formed on the second surface 1262, and the second conductive circuit layer 134 passes through the first conductive circuit layer 124 A plurality of first conductive columns 132 are electrically connected; a second dielectric layer 136, the second dielectric layer 136 is formed on the second surface 1262 and the surface of the second conductive circuit layer 134, the first The second dielectric layer 136 is provided with a plurality of second dielectric layer openings 138, part of the second conductive circuit layer 134 is exposed from the second dielectric layer openings 138; a plurality of second conductive columns 140, the A plurality of second conductive posts 140 are formed in the second dielectric layer opening 138 and are electrically connected to the second conductive circuit layer 134 .

In this embodiment, the plurality of first conductive pillars 132 are approximately in the shape of a truncated cone; the plurality of first conductive pillars 132, the second conductive pillars 140 and the second conductive circuit layer 134 are all formed by electroplating; A surface of the second conductive pillar 140 away from the first dielectric layer 126 is substantially flush with a surface of the second dielectric layer 136 away from the first dielectric layer 126 .

The eighth step, referring to FIG. 12 , is to form a solder resist layer 142 on the side of the first conductive circuit layer 124 of the chip packaging substrate 220, and form a plurality of solder resist layer openings 144 on the solder resist layer 142 to expose part of the first conductive circuit layer 124.

In this embodiment, the solder mask opening 144 is formed through exposure and development processes. The first conductive circuit layer 124 exposed from the solder resist layer 142 is defined as a solder pad 146 , and the solder pad 146 is used to electrically connect the chip package substrate 220 with other circuit boards.

The function of the solder resist layer 142 is to protect the first conductive circuit layer 124 from being oxidized. It is understandable that the solder resist layer 142 may not be formed.

Of course, the chip package substrate 220 may include multiple circuit board units, or only one circuit board unit. In this embodiment, as shown by the dashed line in FIG. 12 , the chip package substrate 220 includes multiple circuit board units Units, the circuits between each circuit board unit are independent of each other.

Step 9, please refer to FIG. 1 , solder a chip 148 on the surface of the second conductive pillar 140 to electrically connect the chip 148 to the second conductive pillar 140 , thereby forming the chip package structure 100 .

In this embodiment, firstly, first solder balls 150 are formed on the surface of each of the second conductive pillars 140 away from the first conductive circuit layer 124, and then the chip 148 is soldered on the first solder balls 150 , so that the chip 148 is electrically connected to the second conductive pillar 140 .

In this embodiment, a second solder ball 152 is formed on the surface of the solder pad 146 ; and after the chip 148 is soldered, an encapsulant 154 is injected into the side and bottom of the chip 148 to fix the chip 148 .

Since the chip package substrate 220 in this case includes multiple circuit board units, in this embodiment, after the chips are soldered, they are cut along the boundaries of each circuit board unit, thereby forming multiple independent chip package structures 100 . Of course, if the chip packaging substrate 220 of this application only includes one circuit board unit, this cutting process is not required.

Please refer to Fig. 13-17, the third embodiment of the present invention provides another manufacturing method of the above-mentioned chip packaging structure, the manufacturing method of the chip packaging structure in this embodiment is roughly the same as that of the second embodiment, the difference lies in the fourth Step to the sixth step, the fourth step to the sixth step of the present embodiment are as follows:

The fourth step, referring to FIG. 13 , is to form a first patterned photoresist layer 930 on the surface of the first dielectric layer 926 and perform electroplating to form a first photoresist layer in each opening 928 of the first dielectric layer. Conductive columns 932, and a second conductive line layer 934 formed on the surface of the first dielectric layer 926 exposed to the first patterned photoresist layer 930, so that the first conductive line layer on the same side as the carrier plate 910 The circuit layer 924 and the second conductive circuit layer 934 are electrically connected through the first conductive pillar 932 on the same side, so as to obtain a first circuit board intermediate 900 . That is, the first patterned photoresist layer 930 is not removed in this step.

The fifth step, please refer to FIGS. 14-15 , is to form a second patterned photoresist layer 960 on both sides of the first circuit board intermediate 900; The second conductive column 940 is formed on the surface of the second patterned photoresist layer 960, so that the second conductive circuit layer 934 on the same side as the carrier plate 910 is electrically connected to the second conductive column 942; after that, remove The first patterned photoresist layer 930 and the second patterned photoresist layer 960 .

Wherein, the second patterned photoresist layer 960 is formed on the surface of the first patterned photoresist layer 930 and part of the surface of the second conductive circuit layer 934 on both sides of the first circuit board intermediate body 900 .

The sixth step, please refer to FIGS. 16-17 , form a second dielectric layer 936 on both sides of the first circuit board intermediate 900 where the second conductive pillar 940 is formed, and grind to expose the second conductive pillar 940 to obtain a second circuit board intermediate 901.

In this embodiment, please refer to FIG. 16 , the second dielectric layer 136 is formed by attaching a film on the side of the second conductive pillar 940 away from the carrier board 110 and curing the film by thermocompression; Referring to FIG. 17 , the second conductive post 940 is exposed by grinding, and the surface of the second conductive post 940 away from the carrier board 910 and the surface of the second dielectric layer 936 away from the carrier board The surface of the 910 is roughly flush.

In other embodiments, the second dielectric layer 936 can also be formed by injection molding referring to the second embodiment; after the second dielectric layer 936 is formed by injection molding, please refer to FIG. out of the second conductive pillar 940.

It can be understood that each embodiment of this case may include more conductive circuit layers and dielectric layers and their fabrication, thereby obtaining a chip package substrate 220 and a chip package structure 100 including more circuit layers; The first conductive circuit layer, the first dielectric layer and the build-up layer are only formed on one side of the carrier board.

Compared with the prior art, in the chip packaging structure, manufacturing method and chip packaging substrate of the embodiments of the present invention, the surface of the second conductive column far away from the first dielectric layer and the surface of the second dielectric layer far away from the The surface of the first dielectric layer is substantially flush, and when solder balls are formed on the surface of the second conductive pillars and bonded to the chip, the solder balls do not need to fill the openings of the solder resist layer, so it is difficult for empty soldering to occur, and the height of the solder balls is The distance between the bottom of the chip and the packaging substrate, so that the distance between the bottom of the chip and the packaging substrate is sufficient to fill the packaging gel, so that the chip can be firmly packaged on the packaging substrate, that is, the chip packaging structure of this case, its other The manufacturing method and the chip packaging substrate can improve the welding yield; moreover, in this case, two chip packaging substrates can be manufactured simultaneously by attaching two chip packaging substrates to a carrier board, which can save costs. Further, this case uses a thermoplastic adhesive layer The chip packaging substrate is attached to the carrier board, and the carrier board can be separated without destroying the carrier board only by heating to melt the thermoplastic adhesive layer, so that the carrier board can be reused and cost can be saved; The board forms a coreless chip packaging substrate and chip packaging structure, which can be made thinner.

It can be understood that those skilled in the art can make various other corresponding changes and modifications according to the technical concept of the present invention, and all these changes and modifications should belong to the protection scope of the claims of the present invention.

Claims (21)

1. a manufacture method for chip-packaging structure, comprises step:

One loading plate is provided, at least the first conductive circuit layer, the first dielectric layer, the second conductive circuit layer is formed successively in side at described loading plate, wherein, multiple first dielectric layer opening is formed in described first dielectric layer, multiple first conductive stud is formed in described first dielectric layer opening, and described first conductive circuit layer and described second conductive circuit layer that are positioned at described loading plate homonymy are electrically connected by multiple first conductive pole;

Form the second dielectric layer in described second conductive circuit layer away from the side of described loading plate, in described second dielectric layer, be formed with multiple second dielectric layer opening;

Plating forms multiple second conductive pole in described second dielectric layer opening, wherein, described second conductive circuit layer and described second conductive pole are electrically connected, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer;

Remove described loading plate;

At surface formation one first soldered ball of each described second conductive pole away from described first conductive circuit layer; And

Weld a chip at multiple described first solder ball surface, described chip is electrically connected with described second conductive pole, thus forms described chip-packaging structure.

2. the manufacture method of chip-packaging structure as claimed in claim 1, it is characterized in that, the formation method of described first conductive circuit layer comprises: at least to fit a Copper Foil and to be made by described Copper Foil by image transfer technique and etch process and form described first conductive circuit layer side at described loading plate.

3. the manufacture method of chip-packaging structure as claimed in claim 2, it is characterized in that, described Copper Foil closes the surface in described loading plate by a thermoplasticity colloid laminating; Remove in the step of described loading plate, make described thermoplasticity colloid layer arrive fusing point by heating, described loading plate is separated with described first conductive circuit layer, thus removes described loading plate.

4. the manufacture method of chip-packaging structure as claimed in claim 1, it is characterized in that, the formation method of described first dielectric layer comprises: at the side away from described loading plate of described first conductive circuit layer laminating film, and hot pressing solidifies described film, forms described first dielectric layer; On described first dielectric layer, multiple described first dielectric layer opening is formed by laser pit.

5. the manufacture method of chip-packaging structure as claimed in claim 4, is characterized in that, after forming described first dielectric layer, form a patterning photoresist layer on the surface of described first dielectric layer; Pass through selective electroplating, thus the first conductive pole is all formed in each described first dielectric layer opening, and form the second conductive circuit layer at the part surface of described first dielectric layer, described first conductive circuit layer and described second conductive circuit layer are electrically connected by described first conductive pole; Remove described patterning photoresist layer.

6. the manufacture method of chip-packaging structure as claimed in claim 5, it is characterized in that, after removing described patterning photoresist layer, at the side away from described loading plate of described second conductive circuit layer laminating film, and hot pressing solidifies described film, form described second dielectric layer; On described second dielectric layer, multiple described second dielectric layer opening is formed by laser pit.

7. the manufacture method of chip-packaging structure as claimed in claim 5, is characterized in that, after removing described patterning photoresist layer, form described second dielectric layer in the mode of injection mo(u)lding in the side away from described loading plate of described second conductive circuit layer; On described second dielectric layer, multiple described second dielectric layer opening is formed by laser pit.

8. the manufacture method of chip-packaging structure as claimed in claims 6 or 7, is characterized in that, plating, thus forms described second conductive pole in described second dielectric layer opening.

9. the manufacture method of chip-packaging structure as claimed in claim 1, is characterized in that, also form the second soldered ball on described first conductive circuit layer surface, described soldered ball is used for described chip-packaging structure and a circuit board to be electrically connected.

10. a manufacture method for chip-packaging structure, comprises step:

One loading plate is provided, at least the first conductive circuit layer, the first dielectric layer, the second conductive circuit layer is formed successively in side at described loading plate, wherein, multiple first dielectric layer opening is formed in described first dielectric layer, multiple first conductive stud is formed in described first dielectric layer opening, and described first conductive circuit layer and described second conductive circuit layer that are positioned at described loading plate homonymy are electrically connected by multiple first conductive pole;

Electroplate thus form multiple second conductive pole on described second conductive circuit layer surface, described second conductive circuit layer and described second conductive pole are electrically connected;

The second dielectric layer is formed away from the side of described loading plate in described second conductive circuit layer, multiple second dielectric layer opening is formed in described second dielectric layer, wherein, described multiple second conductive pole is all formed in described second dielectric layer opening, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer;

Remove described loading plate;

At surface formation one first soldered ball of each described second conductive pole away from described first conductive circuit layer; And

Weld a chip at multiple described first solder ball surface, described chip is electrically connected with described second conductive pole, thus forms described chip-packaging structure.

The manufacture method of 11. chip-packaging structures as claimed in claim 10, it is characterized in that, the formation method of described first conductive circuit layer comprises: at least to fit a Copper Foil and to be made by described Copper Foil by image transfer technique and etch process and form described first conductive circuit layer side at described loading plate.

The manufacture method of 12. chip-packaging structures as claimed in claim 11, is characterized in that, described Copper Foil closes the surface in described loading plate by a thermoplasticity colloid laminating; Remove in the step of described loading plate, make described thermoplasticity colloid layer arrive fusing point by heating, described loading plate is separated with described first conductive circuit layer, thus removes described loading plate.

The manufacture method of 13. chip-packaging structures as claimed in claim 10, it is characterized in that, the formation method of described first dielectric layer comprises: at the side away from described loading plate of described first conductive circuit layer laminating film, and hot pressing solidifies described film, forms described first dielectric layer; On described first dielectric layer, multiple described first dielectric layer opening is formed by laser pit.

The manufacture method of 14. chip-packaging structures as claimed in claim 13, is characterized in that, after forming described first dielectric layer, forms the first patterning photoresist layer on the surface of described first dielectric layer; Pass through selective electroplating, thus the first conductive pole is all formed in each described first dielectric layer opening, and form the second conductive circuit layer at the part surface of described first dielectric layer, described first conductive circuit layer and described second conductive circuit layer are electrically connected by described first conductive pole.

The manufacture method of 15. chip-packaging structures as claimed in claim 14, is characterized in that, after forming described first conductive pole and the second conductive circuit layer, forms the second patterning photoresist layer at described first patterning photoresist layer away from the side of described loading plate; Selective electroplating, thus form the second conductive pole on the surface being exposed to the second patterning photoresist layer of described second conductive circuit layer, described second conductive circuit layer and described second conductive pole are electrically connected; Remove described first patterning photoresist layer and the second patterning photoresist layer.

The manufacture method of 16. chip-packaging structures as claimed in claim 15, it is characterized in that, after removing described first patterning photoresist layer and the second patterning photoresist layer, at the side away from described loading plate of described second conductive circuit layer laminating film, and hot pressing solidifies described film, form described second dielectric layer.

The manufacture method of 17. chip-packaging structures as claimed in claim 15, it is characterized in that, after removing described first patterning photoresist layer and the second patterning photoresist layer, with the side away from described loading plate of the mode of injection mo(u)lding in described second conductive circuit layer, form described second dielectric layer.

The manufacture method of 18. chip-packaging structures as described in claim 16 or 17, it is characterized in that, after forming described second dielectric layer, grind described second dielectric layer, to expose described second conductive pole, and make described second conductive pole away from the surface of described loading plate and the surface away from described loading plate of described second dielectric layer substantially flush.

The manufacture method of 19. chip-packaging structures as claimed in claim 10, is characterized in that, also form the second soldered ball on described first conductive circuit layer surface, described soldered ball is used for described chip-packaging structure and a circuit board to be electrically connected.

20. 1 kinds of chip-packaging structures, comprising:

One first dielectric layer, described first dielectric layer comprises relative first surface and second surface;

One first conductive circuit layer, described first conductive circuit layer is formed at the first surface of described first dielectric layer and side is embedded in described first dielectric layer, and described first conductive circuit layer flushes away from the face of described second surface and described first surface;

One second conductive circuit layer, described second conductive circuit layer is formed at described second surface, and described second conductive circuit layer and described first conductive circuit layer are electrically connected by multiple first conductive pole;

One second dielectric layer, described second dielectric layer is formed at the surface of described second surface and described second conductive circuit layer, and described second dielectric layer is provided with multiple second dielectric layer opening;

Multiple second conductive pole, described multiple second conductive pole is formed in described second dielectric layer opening by plating, described multiple second conductive pole is all electrically connected with described second conductive circuit layer, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer; And

At least one chip, described chip is electrically connected by multiple first soldered ball and described second conductive pole.

21. 1 kinds of chip package base plates, comprising:

One first dielectric layer, described first dielectric layer comprises relative first surface and second surface;

One first conductive circuit layer, described first conductive circuit layer is formed at the first surface of described first dielectric layer and side is embedded in described first dielectric layer, and described first conductive circuit layer flushes away from the face of described second surface and described first surface;

One second conductive circuit layer, described second conductive circuit layer is formed at described second surface, and described second conductive circuit layer and described first conductive circuit layer are electrically connected by multiple first conductive pole;

One second dielectric layer, described second dielectric layer is formed at the surface of described second surface and described second conductive circuit layer, and described second dielectric layer is provided with multiple second dielectric layer opening; And

Multiple second conductive pole, described multiple second conductive pole is formed in described second dielectric layer opening by plating, described multiple second conductive pole is all electrically connected with described second conductive circuit layer, and described second conductive pole roughly flushes away from the surface of described first dielectric layer and the surface away from described first dielectric layer of described second dielectric layer.