TW201705311A - Package substrate, package structure and method for manufacturing same - Google Patents

Abstract

The present disclosure relates to a package structure. The package structure includes a conductive pattern layer, a plurality of conductive poles, a sealing colloid, a plurality of blocks, a plurality of conductive lugs and at least a chip. The conductive pattern layer includes a few conductive lines. The blocks and the conductive poles are formed in the two opposite surfaces of the conductive pattern layer. The blocks and the conductive poles are one to one corresponding and electric connected with the conductive lines respectively. The conductive lines and the conductive poles are clad by the sealing colloid. The exposed surfaces of the conductive lines and the conductive poles are coplanar with the sealing colloid. The conductive lugs are formed on the surface of the blocks and the surface of the blocks is far away from the conductive lines. The chip is welded on the surface of the conductive lugs and the surface of the conductive lugs is far away from the blocks. The present disclosure also relates to a method for manufacturing the package structure.

Description

Chip package substrate, chip package structure and manufacturing method thereof

The present invention relates to the field of circuit board manufacturing, and in particular to a chip package structure, a fabrication method, and a chip package substrate which are advantageous for line densification.

The chip package substrate can provide electrical connection, protection, support, heat dissipation, assembly and the like for the wafer to achieve multi-pin, reduce package volume, improve electrical performance and heat dissipation, ultra-high density or multi-chip modularization. . Conductive bumps on the conductive traces of the chip package substrate that facilitate electrical connection to the wafer are formed. At present, the conductive bumps are often meandered and have an expanded top, which is not conducive to dense circuit design and is prone to solder bridging. In addition, the conductive bumps are often formed by electroplating, which is difficult to control uniformity, and the coplanarity of the top of the conductive bumps is poor, which affects the reliability and yield of the flip chip.

In view of the above, the present invention provides a chip package substrate, a chip package structure, and a method of fabricating the same that can solve the above problems.

A method for fabricating a chip package structure, the method comprising: providing a substrate, the substrate comprising a carrier plate and at least one copper foil layer formed on the carrier plate, wherein a surface of the copper foil layer away from the carrier plate is formed a conductive layer formed on the surface of the barrier layer and having a conductive column electrically connected to the conductive line; forming a gel on the gap between the conductive line and the conductive column, so that the sealant is The opposite surfaces are coplanar with the exposed surfaces of the conductive lines and the conductive pillars respectively; the carrier plate is removed to obtain at least one chip package substrate intermediate; the chip package substrate intermediate body comprises a copper foil layer, a barrier layer, a colloid, a plurality of conductive lines and a plurality of conductive pillars; etching a portion of the copper foil layer and a portion of the barrier layer to form a barrier block in one-to-one correspondence with the conductive traces and electrically connecting the barrier blocks and the one-to-one correspondence with the barrier block Electrically connecting the conductive bumps to obtain a chip package substrate; providing a wafer; soldering the wafer to the conductive bump of the chip package substrate to obtain a crystal Package.

A chip package structure includes a conductive circuit layer, a plurality of conductive pillars, a gel, a plurality of barrier blocks, a plurality of conductive bumps, and at least one wafer. The conductive circuit layer includes a plurality of conductive lines, and the blocking block and the conductive pillar are formed on two opposite surfaces of the conductive line and are electrically connected to the conductive line, and the sealing body is coated with a plurality of strips. a conductive line and a plurality of the conductive pillars, the sealant being coplanar with the exposed surface of the conductive trace and the conductive pillar, the conductive bump being formed on a surface of the barrier block away from the conductive trace; the wafer is soldered The conductive bump is on a surface away from the blocking block.

A chip package substrate comprising a conductive circuit layer, a plurality of conductive pillars, a gel body, a plurality of barrier blocks and a plurality of conductive bumps; the conductive circuit layer comprises a plurality of conductive lines, the barrier block and the conductive pillars are formed And a plurality of electrically conductive lines and a plurality of the conductive columns are coated on the two opposite surfaces of the conductive circuit, and the sealing body covers the conductive lines and the conductive lines, and the conductive body and the conductive line The exposed surface of the conductive post is coplanar and the conductive bump is formed on a surface of the block away from the conductive trace.

The chip package structure, the manufacturing method and the chip package substrate provided by the invention form a trapezoid-like conductive bump, which reduces the solder bridging phenomenon and is beneficial to the conductive line dense design. In addition, the conductive bumps are formed by an etching method, which improves the top coplanarity of the conductive bumps, thereby improving the flip chip reliability and yield.

1 is a cross-sectional view of a substrate according to an embodiment of the present invention.

2 is a cross-sectional view showing a barrier layer formed on the surface of the substrate shown in FIG. 1.

3 is a cross-sectional view showing a first photoresist layer formed on the basis of the barrier layer shown in FIG. 2.

4 is a cross-sectional view showing the first conductive wiring layer formed on the basis of the first photoresist layer shown in FIG.

Figure 5 is a cross-sectional view showing a second photoresist layer formed on the basis of the first wiring layer shown in Figure 4 .

Figure 6 is a cross-sectional view showing a plurality of conductive pillars formed on the basis of the second photoresist layer shown in Figure 5 .

7 is a cross-sectional view showing the first photoresist package layer and the second photoresist layer removed to form a first wafer package substrate intermediate.

Fig. 8 is a cross-sectional view showing the seal body formed between the gaps of the first conductive wiring layer and the conductive post shown in Fig. 7.

FIG. 9 is a cross-sectional view showing the carrier plate and the release layer of FIG. 8 separated and obtained to obtain two second chip package substrate intermediate bodies.

Figure 10 is a cross-sectional view showing the formation of conductive bumps on the basis of the wafer package substrate intermediate of Figure 9.

Figure 11 is a cross-sectional view showing the formation of a barrier block on the basis of the conductive bumps shown in Figure 10 to obtain a wafer package substrate.

Figure 12 is a cross-sectional view of a wafer according to an embodiment of the present invention.

Figure 13 is a cross-sectional view showing the wafer of Figure 12 soldered to the surface of the conductive bump of the wafer package substrate shown in Figure 11 .

Fig. 14 is a cross-sectional view showing a state in which a primer is filled between a wafer and a chip package substrate.

Figure 15 is a cross-sectional view showing the second solder ball formed on the exposed surface of the conductive post shown in Figure 14.

A chip package structure, a manufacturing method, and a chip package substrate provided by the present invention are further described below with reference to FIGS. 1 to 15 and embodiments.

A method of fabricating a chip package structure, comprising the steps of:

In the first step, referring to FIG. 1, a substrate 10 is provided.

The substrate 10 has a flat shape. The substrate 10 includes a carrier plate 11, two release layers 12 and two copper foil layers 13. Two of the release layers 12 are formed on opposite surfaces of the carrier sheet 11, and two of the copper foil layers 13 are formed on the surfaces of the two release layers 12 away from the carrier sheet 11, respectively.

The carrier plate 11 may be a rigid support material such as a resin plate, a ceramic plate, or a metal plate. The release layer 12 can be a release film, a metal foil/board, or the like.

In the present embodiment, two of the copper foil layers 13 are bonded to the carrier plate 11 by a release film.

In other embodiments, the edges of the two copper foil layers 13 may be adhered to the carrier plate 11 by means of glue. When the carrier board 11 is removed, the copper foil layer 13 is bonded and bonded to the carrier board 11 . In part, the copper foil layer 13 is separated from the carrier plate 11.

In the second step, referring to FIG. 2, a relatively thin barrier layer 14 is formed on the surface of the copper foil layer 13 on both sides.

Preferably, the barrier layer 14 may be directly attached to the surface of the copper foil layer 13, or may be formed by other methods such as electroplating.

The barrier layer 14 may be a metal such as nickel or tin other than copper for protecting the conductive lines from being affected in subsequent processes.

In the third step, referring to FIG. 3 to FIG. 4, a conductive circuit layer 16 is formed on the surfaces of the barrier layer 14 on the both sides away from the copper foil layer 13.

The conductive circuit layer 16 includes a plurality of conductive lines 161. Each of the conductive lines 161 includes a first surface 1611 and a second surface 1612 opposite the first surface 1611. The first surface 1611 and the barrier layer 14 The surface away from the copper foil layer 13 is bonded. Specifically, first, referring to FIG. 3, a patterned first photoresist layer 15 is formed on the surfaces of the barrier layer 14 away from the copper foil layer 13 on both sides, so that a part of the barrier layer 14 is patterned from the pattern. The first photoresist layer 15 is exposed; after that, referring to FIG. 4, electroplating, thereby exposing the barrier layer 14 from the patterned first photoresist layer 15 A surface, that is, a patterned gap of the first photoresist layer 15, forms the conductive wiring layer 16, and the first photoresist layer 15 is coplanar with the conductive wiring layer 16.

In the fourth step, referring to FIG. 5 to FIG. 7 , a plurality of conductive pillars 18 are formed on a portion of the second surface 1612 of each of the conductive traces 161 on the two sides of the conductive circuit layer 16 to obtain a first chip package substrate. Intermediate 110.

Each of the conductive posts 18 includes a third surface 181 remote from each of the conductive traces 161. In this embodiment, the conductive pillars 18 are substantially cylindrical, and the conductive pillars 18 are formed on the second surface 1612, and are in one-to-one correspondence with the plurality of conductive lines 161 and are electrically connected. Specifically, first, referring to FIG. 5, a patterned second photoresist layer 17 is formed on a portion of the second surface 1612 and a portion of the surface of the first photoresist layer 15 to partially expose the conductive line 161. Exposed from the second photoresist layer 17; thereafter, referring to FIG. 6, electroplating, thereby exposing a plurality of conductive lines 161 from the patterned second photoresist layer 17 The surface, that is, the patterned gap of the second photoresist layer 17, forms a conductive pillar 18. Finally, the patterned first photoresist layer 15 and the second photoresist layer 17 are removed to form a first chip package substrate intermediate body 110.

In the fifth step, referring to FIG. 8 , a seal body 19 is formed on both sides of the first chip package substrate intermediate body 110 such that the sealant body 19 covers the conductive circuit layer 16 and the plurality of conductive pillars 18 .

In the present embodiment, the encapsulant 19 is formed by injection molding. The encapsulant 19 includes a second surface 191 and a fifth surface 192 that are opposite to each other. The fourth surface 191 is coplanar with the first surface 1611, and the fifth surface is coplanar with the third surface 181.

Specifically, a mold (not shown) is first provided, the abrasive tool includes a cavity and a glue injection channel, and the first chip package substrate intermediate body 110 is received in the cavity; and then, the glue injection channel is passed through Injecting a colloid into the cavity, the colloid is filled with a plurality of the conductive lines 161 and a plurality of the gaps between the plurality of conductive posts 18, such that the sealant 19 is coated with a plurality of the conductive lines 161 and the plurality of conductive posts 18; Next, the colloid is cured to form the encapsulant 19; thereafter, the first chip package substrate intermediate body 110 on which the encapsulant 19 is formed is taken out from the cavity.

In the present embodiment, the amount of injected colloid is controlled such that the third surface 181 is flush with the fifth surface 192.

In other embodiments, an excess of colloid may also be injected to cause the colloid to cover the third surface 181 of the conductive post 18. After molding, the third surface 181 is coplanar with the fifth surface 192 by grinding. .

In the sixth step, referring to FIG. 9, the carrier board 11 and the release layer 12 are separated and removed, thereby obtaining two second chip package substrate intermediate bodies 120.

In the present embodiment, the release layer 12 loses its viscosity, and the carrier plate 11 and the two release layers 12 are separated and removed.

In the seventh step, referring to FIG. 10 to FIG. 11 , a portion of the copper foil layer 13 and a portion of the barrier layer 14 (only partially shown in the drawing) are removed, and a plurality of conductive bumps 20 and a plurality of barrier blocks 30 are formed. A chip package substrate 130 is obtained.

Specifically, first, referring to FIG. 10, a portion of the copper foil layer 13 is removed by an exposure, development, and etching process to obtain a plurality of the conductive bumps 20. Then, referring to FIG. 11, a suitable etching solution (not shown) is disposed, and the excess barrier layer 14 is removed by an exposure, development, and etching process to form a blocking block 30 corresponding to the conductive bumps 20, thereby obtaining a chip package substrate. 130.

Since the material of the barrier layer 14 is not copper, the barrier layer 14 is not removed during the etching to form the conductive bumps 20, and the etching process for forming the conductive bumps 20 is avoided. Destruction of line 161.

The chip package substrate 130 includes a conductive circuit layer 16, a plurality of conductive pillars 18, a glue body 19, a plurality of barrier blocks 30, and a plurality of conductive bumps 20. The conductive circuit layer 16 includes a plurality of conductive lines 161, each of the conductive lines 161 including two opposite first surfaces 1611 and a second surface 1612. Each of the blocking blocks 30 is formed on the first surface 1611 of each of the conductive lines 161, and each of the conductive posts 18 is formed on the second surface 1612 of each of the conductive lines 161. The sealant 19 covers a plurality of the conductive lines 161 and the plurality of conductive posts 18, the sealant 19 includes two opposite fourth surfaces 191 and a fifth surface 192, the fourth surface 191 and the first surface The 1611 is coplanar, and the fifth surface 192 is coplanar with the third surface 181. The conductive bumps 20 are formed on a surface of the blocking block 30 away from the first surface 1611. The conductive bumps 20 are substantially trapezoidal in cross section perpendicular to the conductive circuit layer 16, and the conductive bumps have a width smaller than the conductive bumps. The width of the conductive column. The conductive bump 20 includes a sixth surface 21 that is parallel to the first surface 1611 and away from the first surface 1611.

In the eighth step, referring to FIG. 12, a wafer 140 is provided.

The wafer 140 includes two opposite seventh surfaces 141, an eighth surface 142, and a plurality of pads 143. A plurality of the pads 143 are formed on the eighth surface 142, and the plurality of pads 143 are in one-to-one correspondence with the plurality of the conductive bumps 20.

In the ninth step, referring to FIG. 13 to FIG. 15, the wafer 140 is soldered on the conductive bumps 20, and solder balls are formed on the conductive pillars 18, thereby obtaining the chip package structure 100.

In this embodiment, specifically, first, referring to FIG. 13, the pad 143 of the wafer 140 is soldered to the sixth surface 21 of the conductive bump 20 by solder 40; then, referring to FIG. A primer is filled between the wafer 140 and the fourth surface 191 of the chip package substrate 130 and the first surface 1611 to form a primer layer 50. The primer layer 50 covers a portion of the wafer 140 and the bonding pad 143. The solder 40, the blocking block 30, the conductive bumps 20 and the first surface 1611; afterwards, referring to FIG. 15, a plurality of ones and one corresponding to the conductive pillars 18 are electrically connected to the third surface 181. Solder balls 60 are used to electrically connect external electronic components (not shown) to obtain the chip package structure 100.

In the present invention, a very small portion of the conductive line 161 is exposed, the possibility of oxidation is small, and the price of the underfill is relatively expensive. Therefore, in other embodiments, the undercoat layer 50 may be omitted according to actual needs. A step of.

In summary, the chip package structure 100 includes a conductive circuit layer 16, a plurality of conductive pillars 18, a gel 19, a plurality of barrier blocks 30, a plurality of conductive bumps 20, a wafer 140, and a plurality of solder balls 60.

The conductive circuit layer 16 includes a plurality of conductive lines 161, each of the conductive lines 161 including two opposite first surfaces 1611 and a second surface 1612. Each of the blocking blocks 30 is formed on the first surface 1611 of each of the conductive lines 161, and each of the conductive posts 18 is formed on the second surface 1612 of each of the conductive lines 161.

The sealant 19 covers a plurality of the conductive lines 161 and the plurality of conductive posts 18, the sealant 19 includes two opposite fourth surfaces 191 and a fifth surface 192, the fourth surface 191 and the first surface The 1611 is coplanar, and the fifth surface 192 is coplanar with the third surface 181.

The conductive bumps 20 are formed on a surface of the blocking block 30 away from the first surface 1611. The conductive bumps 20 are substantially trapezoidal in cross section perpendicular to the conductive circuit layer 16, and the conductive bumps have a width smaller than the conductive bumps. The width of the conductive column. The conductive bump 20 includes a sixth surface 21 that is parallel to the first surface 1611 and away from the first surface 1611.

The wafer 140 includes two opposite seventh surfaces 141, an eighth surface 142, and a plurality of pads 143. A plurality of the pads 143 are formed on the eighth surface 142. The plurality of pads 143 are in one-to-one correspondence with the plurality of the conductive bumps 20, and are soldered to the sixth surface of the conductive bumps 20 by the solder 40. 21 on.

A plurality of the solder balls 60 are formed on the plurality of the third surfaces 181 of the plurality of conductive pillars 18, and the plurality of solder balls 60 are electrically connected to the plurality of the conductive pillars 18 in one-to-one correspondence for electrically connecting external electrons. Component (not shown).

In the present embodiment, the chip package structure 100 further includes a primer layer 50 covering a portion of the wafer 140, the pad 143, the solder 40, the barrier block 30, and the conductive bumps 20. And a first surface 1611. In other embodiments, the make layer 50 may not be included.

The chip package structure, the manufacturing method and the chip package substrate provided by the invention form the ladder-like conductive bumps by the etching method, thereby reducing the solder bridging phenomenon and facilitating the dense design of the conductive lines; the bumps formed by the etching method are coplanar Higher performance not only improves the reliability and yield of flip chip, but also facilitates electrical connection, and can reduce the amount of solder and easily control the distance between the wafer and the substrate. In addition, the chip package structure, the manufacturing method and the chip package substrate provided by the invention use the sealant as the substrate body, and the conductive line and the conductive column are covered, and the exposed surfaces of the conductive line and the conductive column are flush with the sealing body, so that the conductive convex The position of the block has a larger selection space so that the wafer can be electrically connected directly to the conductive line without the need to add connecting elements, and the process is simpler.

In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

100‧‧‧ Chip package structure

110‧‧‧First chip package substrate intermediate

120‧‧‧Second chip package substrate intermediate

130‧‧‧ Chip package substrate

10‧‧‧Substrate

11‧‧‧Loading board

12‧‧‧ release layer

13‧‧‧copper layer

14‧‧‧Block

15‧‧‧First photoresist layer

16‧‧‧ Conductive circuit layer

161‧‧‧Electrical circuit

1611‧‧‧ first surface

1612‧‧‧ second surface

17‧‧‧Second photoresist layer

18‧‧‧conductive column

181‧‧‧ third surface

19‧‧‧ Sealant

191‧‧‧ fourth surface

192‧‧‧ fifth surface

20‧‧‧Electrical bumps

21‧‧‧ sixth surface

30‧‧‧Block block

140‧‧‧ wafer

141‧‧‧ seventh surface

142‧‧‧ eighth surface

143‧‧‧ solder pads

40‧‧‧ solder

50‧‧‧Bottom

60‧‧‧ solder balls

no

100‧‧‧ Chip package structure

16‧‧‧ Conductive circuit layer

161‧‧‧Electrical circuit

1611‧‧‧ first surface

1612‧‧‧ second surface

18‧‧‧conductive column

181‧‧‧ third surface

19‧‧‧ Sealant

191‧‧‧ fourth surface

192‧‧‧ fifth surface

20‧‧‧Electrical bumps

21‧‧‧ sixth surface

30‧‧‧Block block

140‧‧‧ wafer

141‧‧‧ seventh surface

142‧‧‧ eighth surface

143‧‧‧ solder pads

40‧‧‧ solder

50‧‧‧Bottom

60‧‧‧ solder balls

Claims (19)

A method for fabricating a chip package structure includes:
Providing a substrate, the substrate includes a carrier plate and at least one copper foil layer formed on the carrier plate, and a barrier layer is formed on a surface of the copper foil layer away from the carrier plate;
Forming a conductive circuit layer and a conductive pillar on the surface of the barrier layer, the conductive circuit layer comprising a plurality of conductive lines, the conductive pillars are in one-to-one correspondence with the conductive lines and are electrically connected;
Forming a gel on the gap between the conductive line and the conductive post such that opposite surfaces of the sealant are coplanar with the exposed surface of the conductive line and the conductive post;
Removing the carrier plate;
Etching off a portion of the copper foil layer and a portion of the barrier layer, forming a blocking block electrically connected to the conductive line and electrically connecting the conductive bumps in one-to-one correspondence with the blocking block, thereby obtaining a chip package substrate;
Providing a wafer;
The wafer is soldered to the conductive bump of the chip package substrate to obtain a chip package structure. The method of fabricating a chip package structure as shown in claim 1, wherein the substrate further comprises a release layer formed between the carrier plate and the copper foil layer, the copper foil layer being bonded by the release layer On the carrier board, the release layer is removed together when the carrier board is removed. The method of fabricating a chip package structure according to claim 1, wherein the barrier layer is a conductive metal other than copper. The method for fabricating a chip package structure as shown in claim 1, wherein the step of forming the conductive circuit layer and the conductive pillar comprises:
Forming a patterned first photoresist layer on a surface of the barrier layer away from the copper foil layer on both sides, such that a portion of the copper foil layer is exposed from the patterned first photoresist layer come out;
Electroplating to form a plurality of the conductive lines in the gap of the patterned first photoresist layer, the first photoresist layer being coplanar with the plurality of conductive lines;
Forming a patterned second photoresist layer on a portion of the conductive line and a portion of the surface of the first photoresist layer to expose a portion of the conductive line from the second photoresist layer;
Electroplating to form a conductive pillar in the gap of the patterned second photoresist layer;
The patterned first photoresist layer and the second photoresist layer are removed. The method of fabricating a chip package structure as shown in claim 1, wherein the sealant is formed by injection molding. The method for fabricating a chip package structure according to claim 1, wherein a portion of the copper foil layer is removed by an exposure, development, and etching process to obtain a plurality of the conductive bumps; and excess is removed by an exposure, development, and etching process. The barrier layer forms a barrier block corresponding to the conductive bump, thereby obtaining a chip package substrate. The method for fabricating a chip package structure according to claim 1, wherein the step further comprises forming a plurality of solder balls on the third surface that are in one-to-one correspondence with the conductive pillars and electrically connected. The method of fabricating a chip package structure according to claim 1, wherein the step further comprises filling a primer between the opposite sides of the wafer and the chip package substrate to form a primer layer. A chip package structure comprising a conductive circuit layer, a plurality of conductive pillars, a glue body, a plurality of barrier blocks, a plurality of conductive bumps and at least one wafer; the conductive circuit layer comprises a plurality of conductive lines, the barrier block and The conductive pillars are formed on the two opposite surfaces of the conductive line and are electrically connected to the conductive lines. The sealant covers a plurality of the conductive lines and the plurality of conductive columns, and the sealant and the sealant The conductive line and the exposed surface of the conductive post are coplanar, and the conductive bump is formed on a surface of the blocking block away from the conductive line; the wafer is soldered on a surface of the conductive bump away from the blocking block. The chip package structure of claim 9, wherein each of the conductive lines comprises two opposite first surfaces and a second surface, each of the blocking blocks being formed on the first surface of each of the conductive lines Each of the conductive pillars is formed on the second surface of each of the conductive traces. The chip package structure of claim 9, wherein the conductive bump is substantially trapezoidal, and includes a sixth surface parallel to the first surface and away from the first surface, the conductive bump having a width smaller than The width of the conductive column. The chip package structure of claim 11, wherein the wafer comprises two opposite seventh surfaces, an eighth surface, and a plurality of pads, wherein the plurality of pads are formed on the eighth surface, The solder pads are in one-to-one correspondence with the plurality of conductive bumps, and are soldered on the sixth surface of the conductive bumps. The chip package structure of claim 9, wherein the chip package structure further comprises a plurality of solder balls formed on a surface of the plurality of conductive posts away from the conductive line, the plurality of solder balls and the plurality of solder balls The conductive posts are one-to-one and electrically connected for electrically connecting external electronic components. The chip package structure according to claim 9 is characterized in that the material of the barrier block is preferably a metal such as nickel or tin which does not react with an etching solution when the conductive wiring layer is formed. The chip package structure of claim 12, wherein the chip package structure further comprises a primer layer covering the wafer, the solder, the barrier block and the conductive bump. A chip package substrate comprising a conductive circuit layer, a plurality of conductive pillars, a gel body, a plurality of barrier blocks and a plurality of conductive bumps; the conductive circuit layer comprises a plurality of conductive lines, the barrier block and the conductive pillars are formed And a plurality of electrically conductive lines and a plurality of the conductive pillars, the sealant and the plurality of conductive lines are disposed on the two opposite surfaces of the conductive line and are electrically connected to the conductive lines. And the exposed surfaces of the plurality of conductive pillars are coplanar, and the conductive bumps are formed on a surface of the blocking block away from the conductive line. The chip package structure of claim 16, wherein each of the conductive lines comprises two opposite first surfaces and a second surface, each of the blocking blocks being formed on the first surface of each of the conductive lines Each of the conductive pillars is formed on the second surface of each of the conductive traces. The chip package structure of claim 16, wherein the conductive bump has a substantially trapezoidal cross section perpendicular to the conductive circuit layer, and the conductive bump has a width smaller than a width of the conductive pillar. The chip package substrate according to claim 16, wherein the barrier block is made of a metal such as nickel or tin that does not react with an etching solution when the conductive wiring layer is formed.