CN105074825B - Distribution based on integrated capacitor - Google Patents
Distribution based on integrated capacitor Download PDFInfo
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- CN105074825B CN105074825B CN201380073104.9A CN201380073104A CN105074825B CN 105074825 B CN105074825 B CN 105074825B CN 201380073104 A CN201380073104 A CN 201380073104A CN 105074825 B CN105074825 B CN 105074825B
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1697—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Embodiment is provided electric power (having low-voltage, high current and high current density) using distributed capacitor come the device to ultra low voltage based on non-CMOS, and the distributed capacitor is integrated on chip identical with the non-cmos device.For example, embodiment provides spin logic gate, the spin logic gate is adjacent with the dielectric substance of capacitor and the first pole plate and the second pole plate.The capacitor discharges low-voltage/high current to the spin logic gate using Buck switched-mode power supply, and the Buck switched-mode power supply charges (using the switch element configured in the first orientation) to multiple capacitors during a clock cycle and discharges electric power from the capacitor during the opposite clock cycle (using the switch element configured in the second orientation).The electric current is discharged into outside face and to the spin logical device by the capacitor, without crossing long power dissipation interconnection path.This document describes other embodiments.
Description
Technical field
The embodiment of the present invention belongs to field of semiconductor devices, and specifically, is the distribution based on integrated capacitor
System.
Background technique
Such as some magnetic memories of spin-transfer torque random access memory (STTRAM) etc utilize magnetic tunneling junction
(MTJ) switch and detect the magnetic state of memory.As shown in Figure 1, MTJ is by ferromagnetic (FM) layer 125,127 and tunneling barrier
126 (for example, MgO) composition.Bit line (BL) 105 is coupled to selection switch 120 (for example, transistor), wordline (WL) 110 by MTJ
With sense line (SL) 115.By assessment resistance (for example, tunnel magneto (TMR)) for the different opposite magnetizations of FM layer 125,127
Variation come " reading " memory 100.
STTRAM is only an example of " surmounting CMOS " technology (or " being not based on CMOS " technology), be related to not exclusively with
The device and technique that complementary metal oxide semiconductor (CMOS) technology is implemented.Surmounting CMOS technology may rely on spin polarization
(degree that its spin for being related to elementary particle or inherent angular momentum are aligned with assigned direction), and more generally useful, it is spin electricity
Son is learned and (is related to the electronics branch of the basic electron charge of the intrinsic spin of electronics, its related magnetic moment and electronics).Spin electricity
Sub- device can be related to TMR, separate ferromagnetic layer and STT using the quantum mechanics tunneling effect of electronics by thin insulator,
Wherein, the electric current of the electronics of spin polarization can be used for controlling the direction of magnetization of ferromagnetic electrode.
Surmount cmos device for example including the spin electric device implemented in the memory (such as 3 terminal STTRAM), from
Rotation logical device (for example, logic gate), tunneling field-effect transistor (TFET), ionization by collision MOS (IMOS) device, electromechanics of receiving are opened
Close (NEMS), negative grid FET, resonance tunnel-through diode (RTD), single-electronic transistor (SET), spin FET, magnet logic of receiving altogether
(NML), domain wall logical device, domain wall memory etc..
Detailed description of the invention
According to the appended claims, the specific embodiment of following one or more exemplary embodiments and corresponding attached
The characteristics of figure, the embodiment of the present invention and advantage can become apparent, in the accompanying drawings:
Fig. 1 shows conventional magnetic storage cell.
Fig. 2 shows the voltage planes in the embodiment of the present invention.
Fig. 3 shows the array of ground wire and power supply line in the embodiment of the present invention.
Fig. 4 shows the spin logic device integrated together with the distribution system based on capacitor in the embodiment of the present invention
Part.
Fig. 5 a shows the charge mode in the switched-mode power supply in the embodiment of the present invention and configures, and Figure 5b shows that
Discharge mode configuration in switched-mode power supply.
Fig. 6 includes the switch element in the switched-mode power supply in the embodiment of the present invention.
Fig. 7 includes the table being related to for the power supply operation characteristic based on non-CMOS technology.
Fig. 8 shows the system used together with embodiments of the present invention.
Specific embodiment
With reference to the drawings, wherein similar suffix reference label can be provided for similar structure.In order to apparent
Ground shows that the structure of each embodiment, drawings included herein are the graphical representations of integrated circuit structure.Thus manufacture is integrated
The actual look (such as in the micrograph) of circuit structure can seem different, and still comprising being required in illustrated embodiment
The structure of protection.In addition, attached drawing can only be shown for understanding the useful structure of illustrated embodiment.It can not include in this field
Known other structure, to keep the clear of attached drawing.The embodiment that the expressions such as " embodiment ", " each embodiment " so describe
It may include a particular feature, structure, or characteristic, but not each embodiment must include the special characteristic, structure or spy
Property.Some embodiments can have in feature described in other embodiments part, all or without the feature.
The common object of the descriptions such as " first ", " second " and " third ", and indicate to be referred to the different instances of analogical object.This shape
Hold word and do not imply that the object so described must be in time, space, sequence in or in any other way and gives
In sequence." connection " can indicate that element physically or electrically contacts directly with one another, and " coupling " can indicate element coordination with one another
Or contact, but they directly may or may not physically or electrically be contacted.In addition, although appended drawing reference similar or identical can be used
In indicating same or similar part in different figures, but does so and be not meant as including the complete of similar or identical appended drawing reference
Portion's attached drawing constitutes single or identical embodiment.The X-Z coordinate shown in come understand such as " higher " and " compared with
It is low ", " ... on " and " ... under " etc term, and can be managed by reference to X-Y coordinate or non-Z coordinate
The term of solution such as " adjacent " etc.
It (is 10mV- for domain wall memory for example, being 0.1V for TFET that many, which surmounts cmos device in ultra low voltage,
100mV, and for spin logical device be 1mV-10mV) under run.For appropriate power requirement (for example, each chip
1W), it requires (for example, 10A-100A) to produce distribution problem corresponding to the high current of low ultra low voltage, reduces by super
More advantage obtained from cmos device.For example, the electrochemical cell for directly generating 10mV, which does not have, provides the capacity of 100A electric current,
And due to electron density limits and it is generally desirable to runing time in (for example, 2-4 hours) enough charges cannot be provided
(that is, quantity that required charge is more than the free electron in the battery of reasonable size) (referring to the second row of Fig. 7).In another example using
Exist in the buck converter that 1V is converted to 10mV, but is not integrated in chip/substrate identical with cmos device is surmounted
(referring to the first row of Fig. 7), and enough charges cannot be provided due to identical aforementioned consideration.In addition, chip external conversion
Device from converter to target device transmission electric power distribution network in by power consumption (that is, electric power must cross resistance
Anti- interconnection, and result is by power consumption).Fig. 7, which is provided, for example to be had 4 hours in the thermal design point (TDP) of 1W
The summary of power requirement under the 10mV of battery life.Specifically, by 1V, 1A power supply be converted to 10mV (that is, ultralow electric power),
100A power supply (that is, second row that Fig. 7 is moved to from the first row of Fig. 7) must satisfy corresponding capacitor (1.4 × 104C) and close
Spend (in 100g, 40A- hours/kg) requirement.This by power supply is integrated in and surmount on cmos logic gate identical chips (that is,
One-piece substrate) system be difficult to complete.
However, embodiment is using the distributed capacitor being integrated on chip identical with non-MOS device come to ultralow electricity
The device based on non-MOS of pressure provides electric power (having low-voltage, high current and high current density).For example, embodiment provides
Spin logic gate, and the logic gate that spins and the dielectric substance of capacitor and the first pole plate are adjacent with the second pole plate.Capacitor makes
Low-voltage/high current is discharged to spin logic gate with Buck switched-mode power supply, the Buck switched-mode power supply is at one
It is charged multiple capacitors (using the switch element configured in the first orientation) during the clock period, and mutually anticlockwise
From capacitor discharge (using the switch element configured in the second orientation) during period.Electric current is discharged into outside face simultaneously by capacitor
And to spin logical device, without crossing long power dissipation interconnection path.This document describes other embodiments.
For example, embodiment obtains the low-down power supply electricity with high current transmission using switched-mode power supply (SMPS)
Pressure.The embodiment meets the current density, resistivity and capacitance requirements of available material and device (for example, with reference to the third of Fig. 7
Row).For example, embodiment provided by implementing the high capacitance layer that is integrated in CMOS stack sufficient current density (for example,
100A/cm2), and low power supply (for example, being less than 125mV) is still provided simultaneously.
Fig. 2 shows the high capacitance layers (that is, voltage plane) in the embodiment of the present invention.Device portions 200 include voltage plane
206.Voltage plane 206 provides capacitor, (hangs down with the horizontally disposed face in such as face 206 etc so that electric current is transmitted " to outside face "
Directly), to avoid the high resistance (for example, series resistance) in patterning wiring, otherwise the high resistance is for example just needed from chip
External power transmits electric power to the device (such as spin logic gate) being located on chip.Voltage plane 206 may include supercapacitor
Material, for example including one or more hafniums, such as setting (will be relevant to Fig. 3 and Fig. 4 to come to it into one below in layer 206
Step be described) in formed capacitor pole plate between hafnium oxide (HfO2), ruthenium-oxide (RuO), molybdenum oxide (MoO3)、
LiMn2O4Active carbon, metal composite oxide etc..
Voltage plane 206 setting dielectric layer 205 (for example, oxide), surmount cmos device layer 204 (e.g., including from
Revolve the magnetic memory etc. of the layer of logical device, STTRAM etc), dielectric layer 203, ground connection or absorbing surface 202 and CMOS
(for example, for generating CMOS transistor) "upper" of layer 201 or " top ".In one embodiment, face 206 includes the length of 1cm
The width 208 of 207 and 1cm generates 100mm wherein with 100 capacitor parts2Plane, below will be further to it
It explains.
Obviously, while figure 2 show that layer 206 is on layer 204, but other orientations are also possible, such as layer 204 is in layer
On 206 or on 206 side of layer (that is, system is rotated 200,180 or 90 degree respectively).
Fig. 3 shows the array of ground wire (302) and power supply line (303) in the embodiment of the present invention.Specifically, the figure
Show the frame (box) in region 310.Here 1 in 100 capacitors is where (that is, as shown in Fig. 2, in this hair
In bright one embodiment, face 206 may include 100 capacitors).Ground wire at node (junction)/capacitor 310
Corresponding to the layer 420 of Fig. 4, and node/capacitor 310 power supply line correspond to Fig. 4 layer 403.Insulating layer (the layer of Fig. 4
421) between ground wire and power supply line (and invisible in Fig. 3).In one embodiment, capacitor is configured in power supply
With metal-insulator-metal type (MiM) supercapacitor of high-g value (not shown) between face and ground plane.Voltage plane with connect
Ground line intersects (but being not directly contacted with each other), and via hole is allowed to form (for example, " sinking (dropping) ") and bigger gold
Belong to layer fill factor.Thus, (and for simplicity and clearly, many is not marked in crosspoint 310,311,312,313,314
Other crosspoints) at formed MiM capacitor.
Fig. 4 shows the spin logic device integrated together with the distribution system based on capacitor in the embodiment of the present invention
Part (for example, phase inverter based on spin logic gate).Specifically, system 400 may include crosspoint 310,311,312,
313, any intersection in 314.In other words, Fig. 2 provides the part 1cm × 1cm of chip.The part provides 100
Individual capacitor.Each capacitor has 2 pole plates (top crown and bottom crown are separated by insulating layer), they are with other 99
The pole plate of a capacitor is isolated.As used herein, " pole plate " needs not be metal polar plate, and can be the terminal for constituting capacitor
Or the film or layer or part thereof of node.Each capacitor then can surmount CMOS logic and/or memory device to thousands of
Electric power is provided.Fig. 4 shows the sub-fraction of 100 capacitors.This fraction to be just in this example spin logical inverse
One device of phase device provides electric power.Certainly, other embodiments, which are not limited to each chip or the part of chip, 100 capacitors
Device, and may include than the more or less quantity.
More specifically, system 400 includes top crown/layer 420 for capacitor, the insulating layer 421 for capacitor
With bottom crown/layer 403 for capacitor.Thus, layer 420,421,403 constitutes capacitor.Capacitor is by layer 422
Via hole to magnet 424,425 release currents.Do so that (they are in other embodiments in the copper part of layer 423 426,427,428
In be not limited to copper) in generate spin polarized current.Spin polarized current from magnet 424 is (with the spin from magnet 425
Polarization current is opposite) out-of-proportion amount can cause the reversion of the signal across magnet 425 and copper part 427,428
(inversion) (thus playing the role of phase inverter).Electric current can be transmitted to ground plane 404 from copper part 427.Ground plane
404 can be formed in so that in the common buildup layer of layer 404 (and 432) symbol, layer 404 is coupled to the symbol gold of such as layer 433
Belong to layer.The layer that oxide 431 is usually located at such as layer 422,430,434 neutralizes between copper part 426,427,428.Layer 404 can
To be coupled to 435/ substrate of cmos layer comprising switch element 436 (is formed) by the transistor in substrate based on CMOS.Following phase
It is discussed further switch element 436 about Fig. 6, it is charged and discharged MiM capacitor (being formed by layer 420,421,403).Layer
435 may include substrate or be formed on substrate.
In embodiment, substrate is the bulk semiconductor material of the part as wafer.In embodiment, semiconductor substrate
It is the bulk semiconductor material of the part as chip, chip is from wafer cutting.In embodiment, semiconductor substrate is shape
At the semiconductor material on insulator, such as semiconductor-on-insulator (SOI) substrate.In embodiment, semiconductor substrate
It is the bulge-structure of fin such as extended on bulk semiconductor material etc.
Although embodiment 400 include spin logic inverter, other embodiments be not limited to phase inverter, spin logic gate/
Circuit or even spinning electron memory.However, phase inverter is for illustrative purpose.
Embodiment 400 can in 1mV, 10mV, 100mV or bigger operating at voltages, and effectively by power supply with it is aforementioned
Spin logical device (it can be easily STTRAM or any other surmount cmos device) is integrated in one single chip (example
Such as, one-piece substrate) on.Integrated power supply includes with the first pole plate (face 420), dielectric (dielectric 421) and the second pole plate
The capacitor in (face 403).It is such as how mutual for layer is shown by the via hole that layer 403 is coupled to those of layer 433 via hole etc
Exemplary purpose even.This via hole may include in various embodiments of the present invention.Moreover, in the multiple portions of Fig. 4
Illustrative " broken line " is shown, so that following concept is better shown: the figure is only the slave individual devices (reverse phase of system
Device) the obtained a part of angle, and the face in such as face 403 etc can continue the range beyond the page for showing Fig. 4.
In embodiment, magnet 424,425 can be with length (Lm=50nm), width (20nm) and height/thickness
(Tm=3nm) ferromagnet.Copper section (copper length) 427 can have length (Lc=100-300nm), width
(20nm) and height/thickness (Tm=3-10nm).Other embodiments are without being limited thereto.
Such as above relative to shown in Fig. 2, in one embodiment, face 206 includes the length 207 of 1cm and the width of 1cm
208, to obtain the 100mm of the capacitor part with 100 1mm × 1mm2Face.It can be the capacitor of MiM capacitor
This array can the charging in the single time interval (for example, clock cycle).For example, some or all of capacitor capacitor
Device can charge in series with each other or parallel to each other.
Embodiment with the 1W chip for being subdivided into 100 parts for distribution can have low electricity seen in fig. 7
Pressure, series resistance, resistivity, electric current and current density characteristics (wherein, such as by via hole 429 and/or other via holes apply electric current
Density limitation).Specifically, Fig. 7 shows the use of 1V power supply in the first row, needs to be coupled to chip and be depressured conversion outside
Device, to generate for surmounting cmos device low-voltage requirement appropriate.Second hand-manipulating of needle is to 10mV power supply, such as battery.However, this
Kind of battery may during operation duration in cannot generate this high current density and total electrical charge (in 100g, 4000A- hours/
kg).The third line corresponds to embodiment (for example, Fig. 4), so that 1 volt of power voltage step down is converted (down- via distributed capacitor
Convert 10mV power supply) is arrived.Doing so provides 100A/cm2Acceptable current density, and avoid to such as in 100g
Under 4000A- hour/kg this high density or 1.4 × 106The needs for crossing multi-charge of C.
Fig. 5 a shows the configuration of the charge mode in SMPS, and Figure 5b shows that in the power supply in the embodiment of the present invention
Discharge mode configuration.Element 540,541,542 represents the capacitor (for example, parasitic capacitance) between layer in the chip.However,
Capacitor 510,511,512 corresponds to the capacitor 310,311,312 of Fig. 3.Moreover, any in capacitor 510,511,512
Capacitor can correspond to the capacitor being made of in Fig. 4 layer 420,421,403.As shown in the structure 500 of Fig. 5 a,
During SMPS charge mode, 510,511,512 serial connection charge of capacitor.As shown in the configuration 500 of Fig. 5 b, switching mechanism
(circuit) can be configured as to be converted to SMPS from series connection when being converted to discharge mode from charge mode and be connected in parallel,
Make 510,511,512 parallel discharge of capacitor whereby.The charge mode of arranged in series is that big partial pressure and current multiplication are prepared.Example
Such as, the 1V power supply for being applied to charge arrangement 500 can divide on 100 capacitors, to provide each capacitor 10mV.Instead of
Such as the charging current of 1A, each of capacitor provide the discharge current of 1A, to generate the total current of 100A on chip.
In addition, the discharge mode of parallel configuration realizes ultralow series resistance, because electric power is without crossing extended path, but
Device, the spin logic gate of such as Fig. 4 are directly deployed to outside face.
In embodiment, SMPS includes the charge cycle for example in 1KHz-10MHz, wherein a group capacitor (for example,
100 capacitors of Fig. 2) it is connected in series to be charged to 1V (Fig. 5 a).In embodiment, putting when SMPS includes 1KHz-10MHz
The electric period, wherein capacitor (each at 10mV) parallel discharge (for example, layer 423 of Fig. 4) (figure into device layer
5B).In one embodiment, in order to ensure continual power supply, a part (for example, 310) of on-chip capacitor can be located
In charge mode, and a part (such as 314) of capacitor may be at discharge mode.Then, switch SMPS, and invert and fill
Electricity and discharge mode.
Thus, Fig. 5 a and Figure 5b shows that how by entire SMPS together with spin logical device, spinning electron memory etc.
It is arranged on chip together.Although SMPS can cooperate with the battery being located at outside chip, SMPS itself is located on chip.
Fig. 6 includes the switch element in the switched-mode power supply in the embodiment of the present invention.Configuration 600 includes capacitor
610,611 (capacitors 310,311 corresponding to Fig. 3) and switch element (element 436 corresponding to Fig. 4), switch element includes
Switching device (for example, transistor) 650,651,652.Switch element is for 1V, 1A power supply to be converted to 10mV, 100A power supply
SMPS embodiment part (that is, the third line that Fig. 7 is moved to from the first row of Fig. 7), meet the resistivity and capacitor of Fig. 7
Those of it is required that (that is, listed in the third line).Transistor 650 is work during clock phase, and transistor 651,652 exists
It is that (for example, transistor 650 can be pFET, and transistor 651,652 can be for work during opposite SMPS clock phase
nFET)。
Embodiment includes per unit area capacitance characteristic below, to realize low resistance, low power supply, can with surmount
Cmos device (for example, spin logical device) works together.
In one embodiment, in spin logic voltage VSLWhen=0.01V and SMPS switching frequency is 10MHz, there is face
Product A=1mm2And Pd=1W/cm2Total electrical charge needed for the chip of power requirement (Q) is:
Wherein, TsmpsIt is the period of SMPS switch (frequency is reciprocal).
Thus, in voltage 0.01V, the effective capacitance of per unit area is:
Required effective capacitance value correspond to 10nm dielectric thickness conventional capacitive (that is, conventional dielectric materials, and
It is not such as HfO2、RuO、MoO3And LiMn2O4The super capacitor high-g value of active carbon etc).Embodiment is for dielectric constant
It is restricted, in dielectric thickness d=10nm, are as follows:
This is a selection to dielectric constant.Higher dielectric constant will be helpful to alleviate requirement to the thickness of layer,
The requirement of the area occupied by capacitor or the performance for increasing voltage plane.
Embodiment include for given dielectric constant (for example, silica be 3.9, HfO2For voltage plane 25) filling because
Son, wherein the fill factor of voltage plane is the gross area for the voltage plane of MiM capacitor divided by chip area.Voltage plane
Fill factor is given by:
For SiO2, it is worth for FSiO2=28.97%, and for HfO2, it is worth for FHfO2=4.52%.Therefore, voltage plane is filled out
Filling the factor can be that metal layer be reused for conventional wires or via hole sinking leaves enough spaces.
Embodiment includes series resistance, is the source electrode of the SMPS at output so as to the series resistance that logical device layer is seen
Resistance.In 10% fill factor, the series resistance of the via layer of per unit chip area is (it is assumed that via resistance rate is copper
10 times of resistivity):
Wherein, L is the length of via hole.
Effective series resistance voltage is reduced to 0.16nV on via hole (it is smaller compared with 10mV power supply).In Vdrop=1mV's
Voltage drop, total conductance of the switch of required per unit chip area:
Power switch transistor (for example, transistor 650,651,652) low-resistance region, be lower than supply voltage VddLower work
Make, wherein the per unit length resistance of transistor is less than:
Wherein, IdsatIt is from can be obtained in www*itrs.net/Links/2011ITRS/Home2011*htm
What 2011 editions of International Technology Roadmap for Semiconductors obtained.
In embodiment, total conductance GtotalNeed the grid length of the per unit area of chip are as follows:
The general power transistor gate length that embodiment can be used 21 meters is come with 1W/cm2Power budget is 100mm2Core
Piece power supply.
In embodiment, the accounting (fraction) of the area of (for example, the transistor 650,651,652) of power transistor
Are as follows:
Therefore, for power gating and the area overhead of conversion less than 3%.
In embodiment, the power transition loss in SMPS (transmit by the output of the SMPS of a part as input power
Power) as follows:
Or, in other words:
And the power efficiency of SMPS is given by:
Thus, embodiment have 85.88% power conversion efficiency and 2.5% area overhead (for high-k dielectric),
1mV on state landing, 25% voltage plane area fill factor and 400A/cm2Current density.Series resistance pressure drop
Less than 1nV, so as to avoid the interconnection loss such as summarized in conventional voltage network.
Embodiment can be used for many different types of systems.For example, in one embodiment, communication equipment is (for example, move
Mobile phone, smart phone, net book, notebook, personal computer, wrist-watch, camera and ultrabook) can be set to include this
Each embodiment described in text.Now referring to Figure 8, what is shown is the block diagram of the system according to embodiments of the invention.Multiprocessing
Device system 700 is point-to-point interconnection system, and the first processor 770 and second including coupling via point-to-point interconnection 750
Processor 780.Each of processor 770 and processor 780 processor can be multi-core processor.First processor 770
It may include memory controller hub (MCH) and point-to-point (P-P) interface.First processor 770 may include via point
The spin logic gate of cloth capacitor power supply.Similarly, second processor 780 may include MCH and P-P interface.MCH can will locate
Reason device is coupled to respective memory, i.e. memory 732 and memory 734, they, which can be, is being attached locally to respectively handle
The part (for example, dynamic random access memory (DRAM)) of the main memory of device.First processor 770 and second processor
780 can be respectively coupled to chipset 790 via P-P interconnection.Chipset 790 may include P-P interface.Moreover, chipset 790
The first bus 716 can be coupled via interfaces to.Multiple input/output (I/O) equipment 714 can be together with bus bridge 718
It is coupled to the first bus 716, the first bus 716 is coupled to the second bus 720 by bus bridge 718.In one embodiment, multiple
Equipment may be coupled to the second bus 720, for example including keyboard/mouse 722, communication equipment 726 and data storage element 728
(such as its may include code 730 disc driver or other mass storage devices).Code may include at one or
In multiple memories, memory includes memory 728,732,734, and the memory etc. of system 700 is coupled to via network.This
Outside, audio I/O 724 may be coupled to the second bus 720.
As further example, at least one machine readable media includes multiple instruction, in response to calculating equipment
On execution and to calculate equipment and execute any means as described herein.Device for process instruction can be configured to hold
Method in row any means as described herein.Device can also include the module for executing any means as described herein.
Embodiment can be implemented in code, and can store the machine-readable storage on it with the instruction of storage
On medium, instruction can be used for being programmed system to execute instruction.Storage medium can include but is not limited to any type
Disk, including floppy disk, CD, solid state drive (SSD), compact disc read-only memory (CD-ROM), rewritable CD (CD-RW) and
The semiconductor devices of magneto-optic disk, such as read-only memory (ROM), such as dynamic RAM (DRAM), static random-access
Random access memory (RAM), the Erasable Programmable Read Only Memory EPROM (EPROM), flash memory, electric erasable of memory (SRAM)
Programmable read only memory (EEPROM), magnetic or optical card, or be suitable for storing Jie of any other type of e-command
Matter.
Following example belongs to further embodiment.
Example 1 includes a kind of device, comprising: supply voltage face, the supply voltage face include the array of power voltage line；
Ground plane, the ground plane include the array of ground wire；The array of capacitor, the array of the capacitor by power voltage line battle array
The array of column and ground wire is constituted；First capacitor device, the first capacitor device are formed in including in the array of power voltage line
First power voltage line and include the first intersection between the first ground wire in the array of ground wire；Wherein, the capacitor
Device includes: the first pole plate, and first pole plate includes a part of the first power voltage line；Second pole plate, second pole plate
A part including the first ground wire；And first dielectric, first dielectric formation in the first pole plate and the second pole plate it
Between；Device, the device are electrically coupled to capacitor, including tunneling field-effect transistor, spin-transfer torque (STT) memory and from
Revolve at least one of logical device；And switch element, the switch element is coupled to capacitor, and is included in switching molding
In formula power supply；Wherein, (a) includes that the array, device and switch element of the capacitor of first capacitor device are all formed in single list
On piece substrate；And (b) switch element makes capacitor discharge, with the electric current between the first pole plate of driving and the second pole plate and so
The electric current is driven to device afterwards.
In example 2, the theme of example 1 can optionally include the second capacitor, and second capacitor is formed in packet
Include the second source pressure-wire in the array of power voltage line and include between the second ground wire in the array of ground wire
Two intersections；Wherein, second capacitor includes: the first other pole plate, and the first other pole plate includes second
A part of power voltage line；In addition the second pole plate, the second other pole plate include a part of the second ground wire；And
Second dielectric, second dielectric formation is between other the first pole plate and the second other pole plate；Wherein, the electricity
Source charges to the first capacitor device and the second capacitor that are one another in series during charge mode, and during discharge mode
Make the first capacitor device being connected in parallel to each other and the second capacitor discharge.
In example 3, the array that the theme of example 1-2 can optionally include capacitor is metal-insulator-metal type
(MiM) capacitor.
In example 4, the theme of example 1-3 can be optionally included wherein: the switch element includes first switch device
Part, second switch device and third switching device；Power supply charges to first capacitor device during the first clock phase, and
First capacitor device is set to discharge during the second clock phase opposite with the first clock phase；And first switch device is first
It is run during clock phase, and second switch device and third switching device are run during second clock phase.
In example 5, the theme of example 1-4 can be optionally included: where power supply makes first capacitor device to supply voltage
Face is vertically discharged, to drive the electric current between the first pole plate and the second pole plate and drive the electric current to device.
In example 6, the theme of example 1-5 can optionally include: where power supply is buck converter, the decompression
Supply voltage is depressured to from 1V is greater than less than 15mV by converter, and to be greater than 380A/cm2Current density offer be greater than
The electric current of 90A.
In example 7, the theme of example 1-6 can optionally include interconnection, and device is coupled to the first pole by the interconnection
One in plate and the second pole plate, wherein the axis orthogonal with the second pole plate intersects with the first pole plate and the second pole plate and device.
In example 8, the theme of example 1-7 can be optionally included wherein, and the first dielectric includes hafnium oxide, oxidation
Ruthenium, molybdenum oxide and LiMn2O4At least one of active carbon.
In example 9, the theme of example 1-8 can be optionally included: where entire power supply include on substrate, and
It is coupled to the battery being located at outside substrate.
Example 10 includes a kind of device, comprising: supply voltage face, the supply voltage face include multiple supply voltage line；
Ground plane, the ground plane include multiple ground wires；Multiple capacitors, the multiple capacitor respectively have by power voltage line
The first terminal that is formed of a power voltage line and the Second terminal that is formed by a ground wire in ground wire；And based on non-
The device of CMOS, the device based on non-CMOS are electrically coupled to including the capacitor in multiple capacitors；Wherein, capacitor
It is formed in single one-piece substrate with device.
In example 11, the theme of example 10 can optionally include the switch element for being coupled to capacitor.
In example 12, the theme of example 10-11 can be optionally included: where and switch element makes capacitor discharge, with
It drives the electric current between first terminal and Second terminal and the electric current is driven to pass through device.
In example 13, the theme of example 10-12 can be optionally included: where and switch element makes capacitor discharge, with
Electric current by electric current from power drives to capacitor and between driving first terminal and Second terminal.
In example 14, the theme of example 10-13 can be optionally included: where device be tunneling field-effect transistor,
At least one of spin-transfer torque (STT) memory and spin logical device.
Example 15 includes a kind of device, comprising: capacitor, the capacitor include: the first pole plate, the first pole plate packet
Include a part of pressure-wire；Second pole plate, second pole plate include a part of ground wire；And dielectric, the dielectric
It is formed between the first pole plate and the second pole plate；Spin electric device, the spin electric device are coupled to capacitor；And it opens
Element is closed, the switch element is coupled to capacitor, and is included in switched-mode power supply；Wherein, it capacitor, device and opens
Element is closed all to be formed in single one-piece substrate；And (b) switch element makes capacitor discharge, to drive the first pole plate and the
Electric current between two pole plates and then the electric current is driven to device.
In example 16, the theme of example 15 can optionally include other capacitor, the other capacitor packet
Include: the first pole plate in addition, the first other pole plate include a part of other pressure-wire；And the second other pole
Plate, the second other pole plate include a part of other ground wire；And other dielectric, the other dielectric
It is formed between the first pole plate and the second pole plate；Wherein, power supply carries out the first capacitor device being one another in series and the second capacitor
Charging, and make the first capacitor device being connected in parallel to each other and the second capacitor discharge.
In example 17, the theme of example 15-16 can optionally include: switch element includes the first transistor and second
Transistor: power supply charges to capacitor during the first clock phase, and makes capacitor during second clock phase
Electric discharge；And switching device is run during the first clock phase, and second switch device is run during second clock phase
In example 18, the theme of example 15-17 can be optionally included: where power supply makes capacitor to including voltage
It vertically discharges in the supply voltage face of line.
In example 19, the theme of example 15-18 can be optionally included: where power supply is buck converter, the drop
Supply voltage is depressured to from 1V is greater than less than 15mV by pressure converter, and to be greater than 380A/cm2Current density offer be greater than
The electric current of 90A.
In example 20, the theme of example 15-19 can be optionally included: where the axis orthogonal with the second pole plate and
One pole plate and the intersection of the second pole plate and device.
In example 21, the theme of example 15-20 can be optionally included: where dielectric includes hafnium oxide, oxidation
Ruthenium, molybdenum oxide and LiMn2O4At least one of active carbon.
In example 22, the theme of example 15-21 can be optionally included: where entire power supply include on substrate, and
And it is coupled to the battery outside substrate.
Although the embodiment for being directed to limited quantity describes the present invention, those skilled in the art can be thus from favorite
Know many modifications and variations.The appended claims be intended to cover fall into true spirit and scope of the present invention all this
A little modifications and variations.
Claims (19)
1. a kind of semiconductor device, comprising:
Supply voltage face, the supply voltage face include the array of power voltage line；
Ground plane, the ground plane include the array of ground wire；
The array of the array of capacitor, the capacitor is made of the array of the array of the power voltage line and the ground wire；
First capacitor device, the first capacitor device are formed in including the first supply voltage in the array of the power voltage line
Line and include the first intersection between the first ground wire in the array of the ground wire；Wherein, the first capacitor device packet
Include: the first pole plate, first pole plate include a part of first power voltage line；Second pole plate, second pole plate
A part including the first ground wire；And first dielectric, first dielectric formation is in first pole plate and described the
Between two pole plates；
Device, the device are electrically coupled to the first capacitor device, and the device includes tunneling field-effect transistor, spin transfer
At least one of square memory and spin logical device；Switch element, the switch element are coupled to the first capacitor device,
And it is included in switched-mode power supply；And
Second capacitor, second capacitor are formed in including the second source voltage in the array of the power voltage line
Line and include the second intersection between the second ground wire in the array of the ground wire；Wherein, the second capacitor packet
Include: the first pole plate in addition, the first other pole plate include a part of the second source pressure-wire；In addition second
Pole plate, the second other pole plate include a part of the second ground wire；And second dielectric, second dielectric formation
Between the first other pole plate and the second other pole plate；
Wherein, (a) includes array, the device and the switch element all shape of the capacitor of the first capacitor device
At in single one-piece substrate；And (b) switch element makes the capacitor discharge, to drive first pole plate and institute
It states the electric current between the second pole plate and then drives the electric current to the device, and
Wherein, the power supply carries out the first capacitor device being one another in series and second capacitor during charge mode
Charging, and make during discharge mode the first capacitor device and second capacitor discharge being connected in parallel to each other.
2. semiconductor device according to claim 1, wherein the array of the capacitor is metal-insulator-metal type electricity
Container.
3. semiconductor device according to claim 1, in which:
The switch element includes first switch device, second switch device and third switching device；
The power supply charges to the first capacitor device during the first clock phase, and with the first clock phase
The first capacitor device is set to discharge during the opposite second clock phase in position；And
The first switch device is run during first clock phase, and the second switch device and the third are opened
Device is closed to run during the second clock phase.
4. semiconductor device according to claim 1, wherein the power supply makes the first capacitor device to the power supply electricity
Pressure surface vertically discharges, to drive the electric current between first pole plate and second pole plate and arrive electric current driving
The device.
5. semiconductor device according to claim 4, wherein the power supply is buck converter, the buck converter
Supply voltage is depressured to from 1V is greater than less than 15mV, and to be greater than 380A/cm2Current density provide be greater than 90A electricity
Stream.
6. semiconductor device according to claim 1, described device includes interconnection, and the device is coupled to by the interconnection
One in first pole plate and second pole plate, wherein the axis and first pole plate orthogonal with second pole plate
Intersect with second pole plate and the device.
7. semiconductor device according to claim 1, wherein first dielectric includes hafnium oxide, ruthenium-oxide, oxygen
Change molybdenum and LiMn2O4At least one of active carbon.
8. semiconductor device according to claim 1, wherein the entire power supply includes and coupling over the substrate
Close the battery being located at outside the substrate.
9. a kind of semiconductor device, comprising:
Supply voltage face, the supply voltage face include multiple supply voltage line；
Ground plane, the ground plane include multiple ground wires；
Multiple capacitors, the multiple capacitor, which respectively has, to be formed by a power voltage line in the power voltage line
First terminal and the Second terminal formed by a ground wire in the ground wire；
Based on the device of non-CMOS, the device based on non-CMOS is electrically coupled to including the capacitor in the multiple capacitor
Device；And
It is coupled to the switch element of the capacitor；
Wherein, the capacitor and the device are formed in single one-piece substrate, and
Wherein, the switch element makes the capacitors charge in series.
10. semiconductor device according to claim 9, wherein the switch element makes the capacitor discharge, with driving
Electric current between the first terminal and the Second terminal and the electric current is driven to pass through the device.
11. semiconductor device according to claim 9, wherein the switch element makes the capacitor discharge, will be electric
Flow from power drives to the capacitor and drive electric current between the first terminal and the Second terminal.
12. semiconductor device according to claim 9, wherein the device is tunneling field-effect transistor, spin transfer
At least one of square memory and spin logical device.
13. a kind of semiconductor device, comprising:
Capacitor, the capacitor include: the first pole plate, and first pole plate includes a part of pressure-wire；Second pole plate, institute
State a part that the second pole plate includes ground wire；And dielectric, the dielectric formation is in first pole plate and described second
Between pole plate；
Spin electric device, the spin electric device are coupled to the capacitor；
Switch element, the switch element is coupled to the capacitor, and is included in switched-mode power supply；And
Other capacitor, the other capacitor include: the first other pole plate, and the first other pole plate includes another
A part of outer pressure-wire；With the second other pole plate, the second other pole plate includes a part of other ground wire；
And other dielectric, the other dielectric formation is between first pole plate and second pole plate；
Wherein, (a) described capacitor, the device and the switch element are all formed in single one-piece substrate；And (b)
The switch element makes the capacitor discharge, to drive electric current between first pole plate and second pole plate and so
The electric current is driven to the device afterwards, and
Wherein, the power supply charges to the capacitor and the other capacitor that are one another in series, and makes each other
The capacitor and the other capacitor discharge in parallel.
14. semiconductor device according to claim 13, in which:
The switch element includes the first transistor and second transistor；
The power supply charges to the capacitor during the first clock phase, and makes institute during second clock phase
State capacitor discharge；And
The first transistor is run during first clock phase, and the second transistor is in the second clock phase
It is run during position.
15. semiconductor device according to claim 13, wherein the power supply makes the capacitor to including the voltage
It vertically discharges in the supply voltage face of line.
16. semiconductor device according to claim 13, wherein the power supply is buck converter, the decompression conversion
Supply voltage is depressured to from 1V is greater than less than 15mV by device, and to be greater than 380A/cm2Current density provide greater than 90A
Electric current.
17. semiconductor device according to claim 13, wherein the axis orthogonal with second pole plate and first pole
Plate and the intersection of second pole plate and the device.
18. semiconductor device according to claim 13, wherein the dielectric includes hafnium oxide, ruthenium-oxide, oxidation
Molybdenum and LiMn2O4At least one of active carbon.
19. semiconductor device according to claim 13, wherein the entire power supply include over the substrate, and
It is coupled to the battery being located at outside the substrate.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2013/032369 WO2014143016A1 (en) | 2013-03-15 | 2013-03-15 | Integrated capacitor based power distribution |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105074825A CN105074825A (en) | 2015-11-18 |
| CN105074825B true CN105074825B (en) | 2019-01-08 |
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| US (1) | US9305629B2 (en) |
| JP (1) | JP6143936B2 (en) |
| KR (1) | KR102110859B1 (en) |
| CN (1) | CN105074825B (en) |
| DE (1) | DE112013006514T5 (en) |
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| KR102170104B1 (en) | 2019-06-26 | 2020-10-27 | 김기웅 | Coupling apparatus for non-welding of pile |
| CN111091862B (en) * | 2019-11-13 | 2022-02-11 | 杭州电子科技大学 | Nonvolatile programmable energy storage element array management system based on magnetic tunnel junction |
| KR20220050707A (en) | 2020-10-16 | 2022-04-25 | 삼성전자주식회사 | Semiconductor device and an operating method thereof |
| US12230569B2 (en) * | 2021-02-16 | 2025-02-18 | Intel Corporation | Apparatus and method to increase effective capacitance with layout staples |
| US11754444B2 (en) | 2021-03-19 | 2023-09-12 | Rockwell Collins, Inc. | Distributed integrate and dump circuit |
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2013
- 2013-03-15 CN CN201380073104.9A patent/CN105074825B/en not_active Expired - Fee Related
- 2013-03-15 DE DE112013006514.2T patent/DE112013006514T5/en active Pending
- 2013-03-15 GB GB1514058.5A patent/GB2526462B/en active Active
- 2013-03-15 JP JP2016500065A patent/JP6143936B2/en active Active
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040100835A1 (en) * | 2002-11-27 | 2004-05-27 | Nec Corporation | Magnetic memory cell and magnetic random access memory using the same |
| US20040264223A1 (en) * | 2003-06-30 | 2004-12-30 | Intel Corporation | Switched capacitor power converter |
| US20070285975A1 (en) * | 2006-05-18 | 2007-12-13 | Takayuki Kawahara | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105074825A (en) | 2015-11-18 |
| KR20150132106A (en) | 2015-11-25 |
| GB201514058D0 (en) | 2015-09-23 |
| JP6143936B2 (en) | 2017-06-07 |
| JP2016517166A (en) | 2016-06-09 |
| GB2526462A (en) | 2015-11-25 |
| US20140269034A1 (en) | 2014-09-18 |
| DE112013006514T5 (en) | 2015-10-15 |
| GB2526462B (en) | 2020-03-18 |
| KR102110859B1 (en) | 2020-05-14 |
| WO2014143016A1 (en) | 2014-09-18 |
| US9305629B2 (en) | 2016-04-05 |
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