CN115223612A - Arithmetic logic cache unit based on magnetic rotation logic tunnel junction and storage method thereof - Google Patents

Abstract

The invention provides an arithmetic logic cache unit based on a magnetic rotation logic tunnel junction and a storage method thereof, wherein the arithmetic logic cache unit comprises an MESO and an MTJ; the MESO of the horizontal bridging comprises a first interconnection electrode, a multiferroic layer is arranged on the first interconnection electrode, one end of a first ferromagnetic layer is positioned above the multiferroic layer, a spin injection layer and a spin charge conversion layer are sequentially arranged below the other end of the first ferromagnetic layer, and a second interconnection electrode is arranged on the side edge of the spin charge conversion layer; the vertical bridging MESO comprises a first interconnection electrode, wherein a multiferroic layer is arranged on the first interconnection electrode, a first ferromagnetic layer, a spin injection layer and a spin charge conversion layer are sequentially arranged above the multiferroic layer, and a second interconnection electrode is arranged on the side edge of the spin charge conversion layer; the MTJ comprises a core region and an electrode; the core region includes a first ferromagnetic layer, a tunneling barrier layer, and a second ferromagnetic layer, and the electrode includes: the third interconnected electrode is a top electrode, and the spin injection layer, the spin charge conversion layer and the second interconnected electrode jointly form a bottom electrode. The invention realizes the integration of ALU and Cache, namely an arithmetic logic storage unit ALCU.

Description

Arithmetic logic cache unit based on magnetic spin logic tunnel junction and its storage method

technical field

The invention belongs to the technical field of memory, and in particular relates to an arithmetic logic cache unit based on a magnetic spin logic tunnel junction and a storage method thereof.

Background technique

Over the past few decades, VLSI chips based on complementary metal oxide semiconductor (CMOS) transistors have followed Moore's Law, with increasing integration density and chip performance, laying the foundation for an information society The basics. However, as the size of transistors is further reduced, the quantum tunneling effect is becoming more and more obvious, and the leakage current caused by it is also increasing. On the other hand, the traditional computer is based on the von Neumann architecture, and its arithmetic logic unit (ALU) and cache (Cache) are separate, and the two are connected by a bus (Bus). When the central processing unit (CPU) is operating, the ALU needs to read data from the Cache through the Bus first. After the data is processed in the ALU, the processing result is returned to the Cache through the Bus. The frequent transmission of data brings serious energy consumption. (ie dynamic power) and latency issues.

Magnetic random access memory (MRAM) with non-volatile is a reliable way to solve the static power consumption of CMOS. By using MRAM as a cache (Cache), the device can be hot-swapped, that is, the device data will not be lost when the device is powered off or suddenly powered off, and the state after power on is exactly the same as the state before power off. The basic unit of MRAM is a magnetic tunnel junction (MTJ), and the core structure (excluding the electrode layer) can be equivalent to three layers, that is, the first ferromagnetic layer, the oxide isolation layer, and the second ferromagnetic layer. The magnetization of one ferromagnetic layer is more easily regulated by external magnetic fields or current conditions than the other layer. The ferromagnetic layer that is easy to control is called the free layer, and the ferromagnetic layer that is difficult to control is called the reference layer or the fixed layer. The magnetization directions of the two ferromagnetic layers can be both in-plane or out-of-plane. When the magnetization direction of the free layer is the same as that of the reference layer, the resistance of the MTJ is small; when the magnetization direction of the free layer and the reference layer are opposite, the resistance of the MTJ is large. Different data bits ("1" and "0") are stored by using the difference of high and low state resistances, and the resistance does not change after the power is turned off, that is, the data is not lost. In the traditional CMOS cache, the voltage is used to store data. After the power is turned off, the voltage difference disappears and the data is lost, so the device can only stand by when it is not in use. Using a large-scale MTJ array to form MRAM, it can be used as a computer cache to overcome CMOS static power consumption.

First, the input signal (current or magnetic field) and output signal (resistance) of the MTJ do not match, and the devices cannot be directly cascaded, making it difficult to directly use the arithmetic logic unit (ALU). MTJ is only used to store memory (including cache and flash memory), and there will still be dynamic power consumption.

Second, the current writing speed of MRAM as a Cache does not match the computing speed of ALU, resulting in a waste of computing power of ALU.

The magnetic spin logic device (MESO) has the characteristics of high speed, low power consumption, high integration density, and cascading, and is expected to replace CMOS as the basic unit of ALU. MESO is mainly composed of two parts: an information writing unit based on magnetoelectric coupling effect and an information reading unit based on spin-orbit coupling (SOC). The information writing unit of the magnetic spin logic device is composed of a multiferroic material (for example, BiFeO ₃ ) and a nanomagnet. When the input voltage is applied to the multiferroic material and is greater than its flip threshold, the ferroelectric order and ferromagnetic properties of the multiferroic material are changed. The order/antiferromagnetic order will be reversed, and the ferromagnetic order of the nanomagnet and the ferromagnetic order/antiferromagnetic order of the multiferroic material are coupled together through the exchange interaction, so the magnetization direction of the nanomagnet will also be flipped together to realize the information transfer. write. The information reading unit of the magnetic spin logic device is composed of a strong spin-orbit coupling (SOC) material and a nanomagnet. A working voltage is applied between the nanomagnet and the strong SOC material, carrying the information of the magnetization direction of the nanomagnet. The spin current is injected into the strong SOC material, and the inverse spin Hall effect or the inverse Rushba effect converts the spin current into a charge current, thereby realizing the conversion from the magnetization direction to the charge voltage, and completing the reading of information. There are two connection modes for the write and read parts of MESO, namely in-plane bridge and vertical bridge. Among them, vertical bridging is easier for micro-nano processing. The use of MESO for ALU does not solve the dynamic power consumption and latency problems of CPU.

SUMMARY OF THE INVENTION

The present invention provides an arithmetic logic cache unit based on a magnetic spin logic tunnel junction and a storage method thereof, aiming at solving the following problems: 1. The problem that MTJ cannot be cascaded and thus is difficult to be used in ALU; 2, MTJ is used in the Cache architecture, The problem of dynamic power consumption and delay; 3, MESO is used for ALU, the problem of dynamic power consumption and delay; 4, the problem of static power consumption of traditional CMOS integrated circuits.

An arithmetic logic cache unit based on a magnetic spin logic tunnel junction, including a MESO and an MTJ;

The horizontally bridged MESO includes a first interconnection electrode, a multiferroic layer is arranged on the first interconnection electrode, one end of the first ferromagnetic layer is located above the multiferroic layer, and the bottom of the other end is a spin injection layer and a spin charge conversion layer in sequence, The side of the spin charge conversion layer is the second interconnection electrode;

The vertically bridged MESO includes a first interconnection electrode, and a multiferroic layer is arranged on the first interconnection electrode. Above the multiferroic layer are a first ferromagnetic layer, a spin injection layer, and a spin-charge conversion layer. The spin-charge conversion layer is on the side. The side is the second interconnection electrode;

The MTJ includes a core region and electrodes; the core region includes a first ferromagnetic layer, a tunneling barrier layer, a second ferromagnetic layer, and the electrodes include: the third interconnection electrode is a top electrode, a spin injection layer, a spin charge conversion layer, The second interconnection electrodes together constitute a bottom electrode;

With the help of MESO, the data operation is completed, and the data is stored in the MTJ in situ, so that the functions of ALU and Cache are realized by a single device.

The multiferroic layer is a single-phase multiferroic material, or a mixed multiferroic material composed of piezoelectric materials and antiferromagnetic materials;

The first ferromagnetic layer and the second ferromagnetic layer include one or more of the following materials: iron, cobalt, nickel, manganese, chromium, and ruthenium.

The spin-charge conversion layer includes all kinds of strong spin-orbit coupling materials, topological insulator materials, two-dimensional electron gas or Rashbar surface materials, and Weyl semimetals.

The tunneling barrier layer includes various semiconductors (such as germanium), topological insulators (such as bismuth telluride, bismuth selenide, bismuth antimonide) and oxide insulators (such as magnesium oxide, aluminum oxide, hafnium dioxide, tantalum oxide, and bismuth oxide). silicon oxide).

The storage method of the above-mentioned arithmetic logic cache unit based on the magnetic spin logic tunnel junction is:

The first interconnection electrode, the multiferroic layer, and the first ferromagnetic layer constitute a data writing portion. By applying different potential levels on the first interconnection electrode, positive or negative voltages are generated at both ends of the multiferroic layer, the electrical polarization of the multiferroic layer is reversed accordingly, and the magnetization of the first ferromagnetic layer is reversed, thereby complete information writing;

The first ferromagnetic layer, the spin injection layer, the spin charge conversion layer, and the second interconnection electrode constitute the data output part. The layer is polarized and filtered through the spin injection layer to form a spin current, which is injected into the spin charge conversion layer, converted into a charge current, and forms a voltage output through the second interconnecting electrode. When the magnetization of the first ferromagnetic layer changes, the output voltage of the second interconnection electrode will be inverted. The output voltage of the second interconnection electrode is equivalent to the voltage across the multiferroic layer when the information is written in the previous step, so the output voltage can directly drive the next MESOTJ for information writing.

The first ferromagnetic layer, the oxide isolation layer, and the second ferromagnetic layer constitute the data storage part, and the change of the magnetization of the first ferromagnetic layer is reflected as the difference between the first ferromagnetic layer, the oxide isolation layer, and the second ferromagnetic layer. Changes in MTJ resistance.

Beneficial effects brought about by the technical solution of the present invention

MESOTJ can be directly cascaded and can be used for ALU;

MESOTJ uses MESO to realize data calculation, the data is stored in the MTJ structure of MESOTJ in situ, there is no transmission process, and there is no dynamic power consumption and delay;

The data is stored in the form of MTJ resistance value, there is no static power consumption, and hot swapping can be realized.

The invention realizes the integration of ALU and Cache, which can be regarded as an arithmetic logic storage unit (ALCU), and can only use ALCU as a core device and cooperate with basic auxiliary switches to construct a CPU.

Description of drawings

1 is a schematic diagram of a horizontal bridge structure of the present invention;

FIG. 2 is a schematic diagram of a vertical bridge structure of the present invention.

Detailed ways

The specific technical solutions of the present invention are described with reference to the accompanying drawings.

The present invention proposes an arithmetic logic cache unit, namely MESOTJ, based on a magnetic spin logic tunnel junction, which is directly used in the arithmetic logic unit ALU and has the function of cache, which is called the arithmetic logic cache unit ALCU.

As shown in FIG. 1 , the horizontally bridged MESO includes a first interconnection electrode 1 on which a multiferroic layer 2 is arranged. One end of the first ferromagnetic layer 3 is located above the multiferroic layer 2 , and the other end is below the multiferroic layer 2 in sequence. The spin injection layer 4, the spin charge conversion layer 5, and the side of the spin charge conversion layer 5 is the second interconnection electrode 6;

As shown in FIG. 2 , the vertically bridged MESO includes a first interconnection electrode 1 , a multiferroic layer 2 is arranged on the first interconnection electrode 1 , and above the multiferroic layer 2 are a first ferromagnetic layer 3 , a spin injection layer 4 , The spin charge conversion layer 5, the side of the spin charge conversion layer 5 is the second interconnection electrode 6;

As shown in FIG. 1 and FIG. 2, the MTJ includes a core region and electrodes; the core region includes a first ferromagnetic layer 3, a tunneling barrier layer 7, and a second ferromagnetic layer 8, and the electrodes include: the third interconnection electrode 9 is a top electrode , the spin injection layer 4 , the spin charge conversion layer 5 and the second interconnection electrode 6 together constitute the bottom electrode.

In MESOTJ, the operation of data can be completed with the help of MESO, and the data is stored in the MTJ in situ, thus realizing the functions of ALU and Cache by using a single device.

The first interconnection electrode 1, the second interconnection electrode 6, and the third interconnection electrode 9 can be any material suitable for VLSI interconnection technology, such as aluminum (Al), copper (Cu), gold (Au), titanium (Ti) , molybdenum (Mo), etc., may contain one or more of them.

The multi-ferrous layer 2 may be a single-phase multi-ferrous material, including but not limited to bismuth ferrite (BiFeO 3 ), bismuth ferrite (BiFeO ₃ ) doped with various elements (eg, lanthanum), terbium manganate (TbMnO _{3 )} ), hexagonal ferrite, hafnium oxide (HfOx), chromium oxide (Cr ₂ O ₃ ) and other materials; or piezoelectric materials (such as magnesium niobate-lead titanate PMN-PT, lead zirconate titanate PZT, etc.) Mixed multiferroic materials composed of antiferromagnetic materials (iridium manganese IrMn, platinum manganese PtMn, manganese gold Mn ₂ Au, manganese tin Mn ₃ Sn, manganese gallium Mn ₃ Ga, etc.), such as, PMN-PT/PtMn, PMN- PT/Mn ₂ Au, etc.

The first ferromagnetic layer 3 and the second ferromagnetic layer 8 include one or more of the following materials: iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), chromium (Cr), ruthenium (Ru).

The spin injection layer 4 may or may not be present. Its materials include metal materials such as copper Cu, aluminum Al, silver Ag; oxide materials such as magnesium oxide MgO, aluminum oxide Al ₂ O ₃ , hafnium dioxide HfO ₂ , tantalum oxide TaOx and silicon dioxide SiO ₂ and so on.

The spin charge conversion layer 5 includes various strong spin-orbit coupling materials, such as heavy metal materials platinum Pt, tantalum Ta, tungsten W, etc. and various tree material alloys; topological insulator materials such as bismuth telluride Bi2Te3 and antimony-doped bismuth telluride ( (Bi, Sb) ₂ Te ₃ ), bismuth selenide, Bi ₂ Se ₃ , etc., α-phase tin (α-Sn); two-dimensional electron gas or Rashiba surface materials such as rhenium aluminate (LaAlO3)/strontium titanate (SrTiO ₃ ), alumina (Al ₂ O ₃ )/potassium carbonate (KTaO ₃ ), bismuth (Bi)/silver (Ag), etc.; Weyl semimetals such as tungsten telluride (WTe ₂ ) and the like.

The tunneling barrier layer 7 includes but is not limited to germanium (Ge), bismuth telluride (Bi ₂ Te ₃ ), bismuth selenide (Bi ₂ Se ₃ ), bismuth antimonide (BiSb), magnesium oxide (MgO), aluminum oxide (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), tantalum oxide (TaOx), silicon dioxide (SiO ₂ ), and the like.

The first interconnection electrode 1, the multiferroic layer 2, and the first ferromagnetic layer 3 constitute a data writing portion. By applying different potential levels on the first interconnection electrode 1, positive or negative voltages are generated at both ends of the multiferroic layer 2, and the electrical polarization of the multiferroic layer 2 is reversed accordingly, driving the magnetization of the first ferromagnetic layer 3 to occur. reversed, thereby completing the writing of information.

The first ferromagnetic layer 3, the spin injection layer 4, the spin charge conversion layer 5, and the second interconnection electrode 6 constitute a data output part, and by injecting a constant working current at the top (or bottom) of the first ferromagnetic layer 3, The current is polarized by the first ferromagnetic layer 3 , filtered by the spin injection layer to form a spin current, injected into the spin charge conversion layer 5 , converted into a charge current, and passed through the second interconnection electrode 6 to form a voltage output. When the magnetization of the first ferromagnetic layer 3 is changed, the output voltage of the second interconnection electrode 6 will be reversed. The output voltage of the second interconnection electrode 6 is equivalent to the voltage across the multiferroic layer 2 during the information writing in the previous step, so the output voltage can directly drive the next MESOTJ for information writing.

The first ferromagnetic layer 3 , the oxide isolation layer 7 , and the second ferromagnetic layer 8 constitute a data storage part, and the change of the magnetization of the first ferromagnetic layer 3 is reflected by the first ferromagnetic layer 3 , the oxide isolation layer 7 , the Variation of the MTJ resistance of the second ferromagnetic layer 8 .

Claims (6)

1. an arithmetic logic buffer unit based on a magnetic spin logic tunnel junction, it is characterized in that, comprise a magnetic spin logic device MESO a magnetic tunnel junction MTJ, MESO comprises two kinds of horizontal bridge and vertical bridge; The horizontally bridged MESO comprises a first interconnection electrode (1), a multiferroic layer (2) is provided on the first interconnection electrode (1), one end of the first ferromagnetic layer (3) is located above the multiferroic layer (2), and the other Below one end are the spin injection layer (4) and the spin charge conversion layer (5) in sequence, and the side of the spin charge conversion layer (5) is the second interconnection electrode (6); The vertically bridged MESO comprises a first interconnection electrode (1), a multiferroic layer (2) is arranged on the first interconnection electrode (1), and a first ferromagnetic layer (3), a spin an injection layer (4), a spin-charge conversion layer (5), and the side of the spin-charge conversion layer (5) is a second interconnection electrode (6); The MTJ includes a core region and electrodes; the core region includes a first ferromagnetic (3), a tunneling barrier layer (7), and a second ferromagnetic layer (8), and the electrodes include: a third interconnecting electrode (9) is a top electrode, The spin injection layer (4), the spin charge conversion layer (5), and the second interconnection electrode (6) together form a bottom electrode; With the help of MESO, the operation of data is completed, and the data is stored in the MTJ in situ, so that the functions of the arithmetic logic unit ALU and the cache are realized by a single device. 2. The arithmetic logic cache unit based on a magnetic spin logic tunnel junction according to claim 1, wherein the multiferroic layer (2) is a single-phase multiferroic material, or is composed of a piezoelectric material and a Hybrid multiferroic materials composed of antiferromagnetic materials. 3. An arithmetic logic cache unit based on a magnetic spin logic tunnel junction according to claim 1, wherein the first ferromagnetic layer (3) and the second ferromagnetic layer (8) comprise the following materials One or more of: iron, cobalt, nickel, manganese, chromium, ruthenium. 4. The arithmetic logic buffer unit based on a magnetic spin logic tunnel junction according to claim 1, wherein the spin charge conversion layer (5) comprises various types of strong spin-orbit coupling materials, topological insulators material, 2D electron gas or Rashiba surface material, Weyl semimetal. 5. An arithmetic logic cache unit based on a magnetic spin logic tunnel junction according to claim 1, wherein the tunneling barrier layer (7) comprises various semiconductors, topological insulators and oxide insulators. 6. The storage method of an arithmetic logic cache unit based on a magnetic spin logic tunnel junction according to any one of claims 1 to 5, characterized in that, comprising the following steps: The first interconnection electrode (1), the multiferroic layer (2), and the first ferromagnetic layer (3) constitute a data writing part; by applying different potential levels on the first interconnection electrode (1), the multiferroic layer ( 2) A positive or negative voltage is generated at both ends, and the electric polarization of the multiferroic layer (2) is reversed accordingly, which drives the magnetization of the first ferromagnetic layer (3) to reverse, thereby completing the information writing; The first ferromagnetic layer (3), the spin injection layer (4), the spin charge conversion layer (5), and the second interconnection electrode (6) constitute a data output part, and the first ferromagnetic layer (3) is formed at the top of the Or the bottom end injects a constant working current, the current is polarized by the first ferromagnetic layer (3), filtered through the spin injection layer (4) to form a spin current, injected into the spin charge conversion layer (5), converted is charge flow, and forms a voltage output through the second interconnected electrode (6); when the magnetization of the first ferromagnetic layer (3) changes, the output voltage of the second interconnected electrode (6) will be reversed; the second interconnected electrode (6) ) The output voltage is equivalent to the voltage at both ends of the multiferroic layer (2) when the information is written in the previous step, so the output voltage can directly drive the next magnetic spin logic tunnel junction to write information; The first ferromagnetic layer (3), the tunneling barrier layer (7), and the second ferromagnetic layer (8) constitute a data storage part, and the change of the magnetization of the first ferromagnetic layer (3) is reflected by the first ferromagnetic Changes in the resistance of the MTJ formed by the layer (3), the tunneling barrier layer (7), and the second ferromagnetic layer (8).

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