CN104978940A - Pixel circuit - Google Patents

Abstract

The pixel circuit comprises a liquid crystal capacitor, a first storage capacitor, a driving unit, a compensation unit and a reset unit. The driving unit is electrically coupled with the liquid crystal capacitor, the driving unit is used for determining whether to enable the liquid crystal capacitor to store a display potential according to a driving unit control signal, the compensation unit is electrically coupled with the driving unit and is used for determining whether to compensate the driving unit control signal according to a first control signal, and the reset unit is electrically coupled with the driving unit, the compensation unit and the first storage capacitor and is used for determining whether to reset the driving unit control signal and the liquid crystal capacitor storage potential according to a second control signal.

Description

pixel circuit

【Technical field】

The present invention relates to a pixel circuit, in particular to a pixel circuit applied to a liquid crystal display device.

【Background technique】

In order to have a better display effect, the current display devices have increased the resolution and frame update rate of the display device one after another. However, in order to have a higher frame refresh rate, the time for charging the pixel units in the display device is shortened and the charging frequency is changed. High, and when the electric field frequency felt by the liquid crystal capacitor of the pixel unit is higher than a specific frequency when charging, the capacitance value of the liquid crystal capacitor will decrease because the dielectric coefficient becomes smaller. When the liquid crystal capacitor is turned off and returns to a steady state, the liquid crystal capacitor The frequency of the electric field felt decreases, so the capacitance value of the liquid crystal capacitor will increase, and at this time, the liquid crystal capacitor will cause the voltage of the liquid crystal capacitor to drop due to the principle of charge conservation, resulting in a loss of display brightness. In known display devices, storage capacitors are often used to compensate the brightness loss of liquid crystal capacitors. However, in display devices such as blue phase liquid crystal (Blue Phase LC) display devices and ferroelectric liquid crystal (Ferroelectric LC) display devices with extremely high operating frequencies, In order to effectively compensate the liquid crystal capacitors, the storage capacitors need to have a large amount of stored charge, and thus need to occupy a large hardware area and cost of the display device.

【Content of invention】

In order to solve the above shortcomings, the present invention proposes an embodiment of a pixel circuit, which includes a liquid crystal capacitor, a first storage capacitor, a driving unit, a compensation unit, and a reset unit. The liquid crystal capacitor has a first end and a second end, and the second end of the liquid crystal capacitor is electrically coupled to a common mode voltage; the first storage capacitor has a first end and a second end, and the second end of the first storage capacitor The end is electrically coupled with a first low voltage potential; the driving unit is electrically coupled with the first end of the liquid crystal capacitor, and the driving unit is used to determine whether to make the liquid crystal capacitor store a display potential according to a driving unit control signal; the compensation unit The electrical coupling with the driving unit is used to determine whether to compensate the driving unit control signal according to a first control signal; the reset unit is electrically coupled with the driving unit, the compensation unit and the first storage capacitor, and is used for determining whether to compensate the driving unit control signal according to a first control signal. The second control signal determines whether to reset the driving unit control signal and the voltage potential of the first terminal of the liquid crystal capacitor.

In other embodiments of the present invention, the driving unit further includes a first transistor, the first transistor has a first terminal, a second terminal and a control terminal, the first terminal of the first transistor is used to receive a potential signal, The control end of the first transistor is electrically coupled to the first end of the first storage capacitor for receiving the driving unit control signal, and the second end of the first transistor is electrically coupled to the first end of the liquid crystal capacitor.

In other embodiments of the present invention, the compensation unit further includes a second transistor and a third transistor. The second transistor has a first terminal, a second terminal and a control terminal, the second terminal and the control terminal of the second transistor are electrically coupled to the first terminal of the first storage capacitor, the third transistor has a first terminal, A second terminal and a control terminal, the first terminal of the third transistor receives a display data signal, the control terminal of the third transistor receives the first control signal, the second terminal of the third transistor is electrically connected to the first terminal of the second transistor Sexually coupled, the first control signal is an nth level gate control signal.

In other embodiments of the present invention, the reset unit further includes a fourth transistor, which has a first terminal, a second terminal and a control terminal, and the first terminal of the fourth transistor is used to receive a first high voltage Potential, the control end of the fourth transistor is used to receive the second control signal, the second end of the fourth transistor is electrically coupled to the first end of the first storage capacitor, and the second control signal is an n-1th gate pole control signal.

In the above-mentioned embodiment of the present invention, the third transistor is used for turning off in a first period, and the fourth transistor is used for turning on in the first period, so as to reset the driving unit control signal to the first high voltage potential, and the first transistor is used for To be turned on in the first period, to pass through a potential signal of a second low voltage potential, to reset the first end of the liquid crystal capacitor to the second low voltage potential; the fourth transistor is used to close in a second period, and the third transistor and the second transistor is used to turn on in a second period, so that the voltage of the first terminal of the first storage capacitor is charged/discharged from the first high voltage potential according to the potential of the display data signal; the potential signal is used for a third A second high voltage potential is provided during the period, and the first transistor is used to control the potential of the first terminal of the liquid crystal capacitor according to the potential of the first storage capacitor during the third period.

In another embodiment of the present invention, the pixel circuit further includes a display data signal input unit electrically coupled to the reset unit for determining whether to output a display data signal according to an nth level gate control signal.

In another embodiment of the present invention, the driving unit includes a first transistor, which has a first terminal, a second terminal and a control terminal, and the first terminal of the first transistor is electrically connected to the reset unit and the compensation unit. Coupling, the control end of the first transistor is used to receive the driving unit control signal and is electrically coupled with the compensation unit, and the second end of the first transistor is electrically coupled with the first end of the liquid crystal capacitor.

In another embodiment of the present invention, the reset unit further includes a second transistor, a third transistor and a fourth transistor, the second transistor has a first terminal, a second terminal and a control terminal, the second transistor The first end is electrically coupled to a first high voltage potential, the control end of the second transistor is used to receive the second control signal, the second end of the second transistor is electrically coupled to the first end of the first transistor and the compensation unit connected, the third transistor has a first terminal, a second terminal and a control terminal, the first terminal of the third transistor is electrically coupled with the display data signal input unit and the first terminal of the first storage capacitor, the third transistor The control terminal is used to receive the first control signal, the second terminal of the third transistor is electrically coupled with the first low voltage potential, the fourth transistor has a first terminal, a second terminal and a control terminal, the fourth transistor The first end of the fourth transistor is electrically coupled to the first end of the liquid crystal capacitor, the control end of the fourth transistor is used for receiving the first control signal, and the second end of the fourth transistor is electrically coupled to the first low voltage potential.

In another embodiment of the present invention, the compensation unit further includes a fifth transistor, which has a first terminal, a second terminal and a control terminal, the first terminal of the fifth transistor and the first terminal of the first transistor and The second end of the second transistor is electrically coupled, the second end of the fifth transistor is electrically coupled to the control end of the first transistor and the display data signal input unit, and the control end of the fifth transistor is used to receive the first control signal .

In another embodiment of the present invention, the display data signal input unit includes a sixth transistor and a second storage capacitor, the sixth transistor has a first terminal, a second terminal and a control terminal, the sixth transistor of the sixth transistor One end is used to receive the display data signal, the second end of the sixth transistor is electrically coupled to the first end of the third transistor and the first end of the first storage capacitor, and the control end of the sixth transistor is used to receive the nth stage Gate control signal, the second storage capacitor has a first end and a second end, the first end of the second storage capacitor is electrically coupled to the second end of the sixth transistor, the second end of the second storage capacitor is electrically coupled to the second end of the sixth transistor The second end of the fifth transistor is electrically coupled.

In the above-mentioned another embodiment of the present invention, the sixth transistor is used to be turned off during a first period, and the third transistor and the fourth transistor are used to be turned on during the first period to reset the first terminal of the liquid crystal capacitor and the second transistor. A storage potential of a storage capacitor is a first low voltage potential, and the second transistor and the fifth transistor are turned on during the first period to reset the driving unit control signal to a second high voltage potential; the second transistor and the sixth transistor are used The third transistor, the fourth transistor and the fifth transistor are used to be turned on during a second period, so that the driving unit control signal is discharged from the second high voltage potential to a compensation voltage potential; the sixth transistor For opening in a third period, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are used for closing in the third period, so that the voltage of the first terminal of the second storage capacitor is changed from the first low voltage The potential is charged/discharged according to the potential of the display data signal, and the potential of the drive unit control signal is charged/discharged by the compensation voltage potential according to the potential of the display data signal; the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are used for a The fourth period is off, and the second transistor is used to turn on during the fourth period, so that the first transistor is used to store the display voltage potential in the liquid crystal capacitor according to the potential of the driving unit control signal during the fourth period.

To sum up, since the liquid crystal capacitor of the present invention is not directly charged according to the gate control signal of the current stage, the liquid crystal capacitor does not need to be operated at a high frequency due to the high frame refresh rate, and the display device does not need a high-capacity The storage capacitor is used to assist the liquid crystal capacitor to maintain a stable voltage value, effectively reducing the consumption of hardware area and manufacturing cost.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with accompanying drawings.

【Description of drawings】

FIG. 1 is a schematic diagram of an embodiment of a display device.

FIG. 2A is a schematic diagram of Embodiment 1 of a pixel circuit of the present invention.

FIG. 2B is a timing schematic diagram of Embodiment 1 of the pixel circuit of the present invention.

FIG. 3A is a schematic diagram of Embodiment 2 of the pixel circuit of the present invention.

FIG. 3B is a timing diagram of the second embodiment of the pixel circuit of the present invention.

FIG. 4A is a schematic diagram of Embodiment 3 of the pixel circuit of the present invention.

FIG. 4B is a schematic timing diagram of Embodiment 3 of the pixel circuit of the present invention.

FIG. 5 is a schematic diagram of the steps of the pixel circuit operation method of the present invention.

【Symbol Description】

10 display device

11 timing controller

12 data drives

13 gate driver

14 pixels

121 data cable

131 grid line

21 drive unit

22 Display data signal input unit

31 drive unit

32 reset unit

33 compensation unit

41 drive unit

42 reset unit

43 Compensation unit

44 Display data signal input unit

T21, T22, T31, T32, T33, T34, T41, T42, T43, T44, T45, T46 transistors

T1, T11, T2, T3, T4 period

S1, S2 control signal

G[n] Level n gate control signal

G[n-1] Level n-1 gate control signal

DATA Display data signal

C _LC liquid crystal capacitor

C _ST storage capacitor

C _ST1 first storage capacitor

C _ST2 second storage capacitor

V _DD first high voltage potential

V _G drive unit control signal

V _S [n] nth level potential signal

GND The first low voltage potential

V _COM common mode voltage

V _DATA shows the voltage potential

【Detailed ways】

Please refer to FIG. 1. FIG. 1 is an embodiment of a display device 10. The display device 10 includes a timing controller 11, a data driver 12 and an AND gate driver 13. The data driver 12 passes through a plurality of data lines 121 and a plurality of pixels 14. Electrically coupled, the gate driver 13 is electrically coupled to a plurality of pixels 14 through a plurality of gate lines 131, wherein the display device 10 is used to transmit a plurality of display data signals DATA to the The data driver 12 and the timing controller 11 control the gate driver 13 to output the gate control signal at the correct time to drive the electrically coupled pixels 14, and the driven pixels 14 can be connected via multiple data lines 121 receives a plurality of display data signals DATA.

Please refer to FIG. 2A . FIG. 2A is a schematic diagram of a pixel circuit embodiment 1 of the present invention. The pixel 14 includes a driving unit 21 , a display data signal input unit 22 , a first storage capacitor C _ST1 , a liquid crystal capacitor C _LC and a storage capacitor C _ST . The display data signal input unit 22 includes a transistor T21, which has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T21 is used to be electrically coupled with the data line 121 to receive the display data signal DATA. The transistor T21 The control terminal is electrically coupled to the gate line 131, and is used to receive the nth level gate control signal G[n], and the transistor T21 is used to determine whether to display data according to the nth level gate control signal G[n]. The signal DATA is transmitted to the second terminal of the transistor T21. The first storage capacitor C _ST1 has a first end and a second end, the first end of the first storage capacitor C _ST1 is electrically coupled to the second end of the transistor T21, the second end of the first storage capacitor C _ST1 is connected to the first The low voltage potential GND is electrically coupled, and when the display data signal DATA is transmitted to the second terminal of the transistor T21, the first storage capacitor C _ST1 is used for storing the voltage value of the display data signal DATA. The drive unit 21 includes a transistor T22. The transistor T22 is a Source Follower structure. The transistor T22 has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T22 is used to receive the nth level potential The signal V _S [n], the control end of the transistor T22 is electrically coupled to the first end of the first storage capacitor C _ST1 , and is used to receive a drive unit control signal V _G , wherein the drive unit control signal V _G is the first A voltage value of the first terminal of the storage capacitor C _ST1 . The liquid crystal capacitor C _LC has a first end and a second end, the first end of the liquid crystal capacitor C _LC is electrically coupled to the second end of the transistor T22, and the second end of the liquid crystal capacitor C _LC is electrically coupled to the common mode voltage V _COM catch. The storage capacitor C _ST has a first end and a second end, the first end of the storage capacitor C _ST is electrically coupled to the second end of the transistor T22, and the second end of the storage capacitor C _ST is electrically coupled to the common-mode voltage V _COM , the storage capacitor C _ST is used to compensate the voltage lost by the liquid crystal capacitor C _LC when the liquid crystal capacitor C _LC is not charged by the transistor T22 in a steady state.

Please refer to FIG. 2B. FIG. 2B includes the timing diagram of the nth level gate control signal G[n], the nth level potential signal _VS [n] and the display data signal DATA, which will be described in conjunction with FIG. 2A and FIG. 2B The operation method of the first embodiment of the pixel circuit.

In the period T11 in the period T1 in FIG. 2B, the gate control signal G[n] of the nth stage is an operating voltage potential, which can be a logic high voltage potential, so the transistor T21 is turned on, and simultaneously displays data The signal DATA has a display voltage V _DATA for displaying. Therefore, the first storage capacitor C _ST1 stores the display voltage V _DATA of the display data signal DATA during the period T11 because the transistor T21 is turned on. In addition, the nth level potential signal V _S [n] is a low voltage potential, for example, a low voltage potential lower than the first low voltage potential GND, and the voltage at the first terminal of the liquid crystal capacitor C _LC can be reset through the transistor T22 is the low voltage potential of the nth level potential signal V _S [n]. Then in the period T2, the gate control signal G[n] of the nth stage is a low voltage potential, such as a logic low voltage potential, and the potential signal V _S [n] of the nth stage is higher than the voltage value of the drive unit control signal V _G voltage potential, the transistor 21 is turned off at this time because of the nth level gate control signal G[n], and because the nth level potential signal V _S [n] is a high voltage potential, the transistor T22 operates in the saturation region, so the transistor T22 controls The voltage value at the terminal is the drive unit control signal V _G to charge the voltage at the first terminal of the liquid crystal capacitor C _LC and the storage capacitor C _ST to the display voltage potential V _DATA minus the threshold voltage V _thT22 of the transistor T22, that is, V _DATA - With the voltage value of V _thT22 , the pixel 14 can display the display data signal DATA according to the voltage value of V _DATA -V _thT22 .

In this embodiment, since the display data signal DATA is stored by the first storage capacitor C _ST1 , after the gate control signal G[n] of the nth stage is disabled, the liquid crystal capacitor C _LC can still be continuously provided by the transistor T22. Charging/discharging, the liquid crystal capacitor C _LC will not be directly affected by the gate control signal G[n] of the nth stage, which can effectively reduce the decrease in the capacitance value of the liquid crystal capacitor C _LC due to too high electric field frequency.

Please refer to FIG. 3A. FIG. 3A is the second embodiment of the pixel circuit of the present invention. In this embodiment, the pixel 14 includes a liquid crystal capacitor C _LC , a first storage capacitor C _ST1 , a storage capacitor C _ST , a drive unit 31, a Setting unit 32 and compensation unit 33, wherein the liquid crystal capacitor C _LC has a first end and a second end, the second end of the liquid crystal capacitor C _LC is electrically coupled to the common mode voltage V _COM , and the first storage capacitor C _ST1 has a first end and a second end, the second end of the first storage capacitor C _ST1 is electrically coupled to the first low voltage potential GND, the storage capacitor C _ST has a first end and a second end, the first end of the storage capacitor C _ST is connected to The first end of the liquid crystal _capacitor C _LC is electrically coupled, and the second end of the storage capacitor C _ST is electrically coupled to the common mode voltage V _{COM .} Compensate the voltage lost by the liquid crystal capacitor C _LC in the steady state of charging.

The driving unit 31 includes a transistor T31. The transistor T31 is a source follower (SourceFollower) structure. The transistor T31 has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T31 is used to receive the nth level potential signal V _S [n], the control end of the transistor T31 is electrically coupled to the first end of the first storage capacitor C _ST1 , the control end of the transistor T31 is used to receive the drive unit control signal V _G , wherein the drive unit control signal V _G is the voltage value of the first terminal of the first storage capacitor C _ST1 , and the second terminal of the transistor T31 is electrically coupled to the first terminal of the liquid crystal capacitor C _LC , and the drive unit 31 is used to determine the drive unit according to the drive unit control signal V _G Whether to charge the liquid crystal capacitor C _LC . The reset unit 32 includes a transistor T32. The transistor T32 has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T32 is used to receive the first high voltage potential V _DD . The control terminal of the transistor T32 is used for The gate line 131 is electrically coupled to receive the n-1th stage gate control signal G[n-1], and the second end of the transistor T32 is electrically coupled to the first end of the first storage capacitor C _ST1 . The compensation unit 33 includes a transistor T33 and a transistor T34. The transistor T33 has a first terminal, a second terminal and a control terminal. The second terminal and the control terminal of the transistor T33 are connected to the second terminal of the transistor T32 and the first storage capacitor C _ST1 . Terminals are electrically coupled, the transistor T34 has a first terminal, a second terminal and a control terminal, the first terminal of the transistor T34 is electrically coupled to the data line 121 in FIG. 1 to receive the display data signal DATA, the control terminal of the transistor T34 is connected to the The gate line 131 in FIG. 1 is electrically coupled to receive the nth stage gate control signal G[n], and the second end of the transistor T34 is electrically coupled to the first end of the transistor T33 .

Please refer to Figure 3B, Figure 3B includes the n-1th level gate control signal G[n-1], the nth level gate control signal G[n], the nth level potential signal V _S [n] and the display data For the timing diagram of the signal DATA, the operation method of the second embodiment of the pixel circuit is described below with reference to FIG. 3A and FIG. 3B .

Firstly, in the time period T1 in FIG. 3B , the n-1th level gate control signal G[n-1] is an operating voltage potential, which can be a logic high voltage potential, and the nth level gate control signal G[n-1] ] is a low voltage potential, which may be a logic low voltage potential, and the nth level potential signal V _S [n] is a low voltage potential, for example, a low voltage potential lower than the first low voltage potential GND, so the transistor T32 at this time is is turned on, the transistor T34 is turned off, and since the transistor T32 is turned on, the voltage value of the first terminal of the first storage capacitor C _ST1 is charged to the voltage value of the first high voltage V _DD , that is, the driving unit control signal V _G is During the time period T1, the transistor T32 is boosted to the voltage value of the first high voltage V _DD , and the first terminals of the liquid crystal capacitor C _LC and the storage capacitor C _ST are reset to the n-level potential signal by the n-level potential signal V _S [n] The low voltage potential of V _S [n]. Then in the period T2, the n-1th level gate control signal G[n-1] is a low voltage potential, the nth level gate control signal G[n] is a high voltage potential, and the nth level potential signal V _S [ n] is a low voltage potential, and the display data signal DATA has a display voltage potential V _DATA for display, so the transistor T32 is turned off, and the transistor T34 is turned on, and since the voltage value of the first high voltage V _DD is greater than the display voltage potential V _DATA , so the current flows from the second terminal of the transistor T32 to the direction of the transistor T34, the voltage value of the drive unit control signal V _G is therefore pulled down from the voltage value of the first high voltage V _DD to the display voltage potential V _DATA plus the transistor The voltage value of the T33 threshold voltage V _thT33 , that is, V _G =V _DATA +V _thT33 . In the period T3, the n-1th level gate control signal G[n-1] is a low voltage potential, the nth level gate control signal G[n] is a low voltage potential, and the nth level potential signal V _S [n] is a high voltage potential, at this time, since the voltage value of the drive unit control signal V _G is V _DATA +V _thT33 , and the nth level potential signal V _S [n] is a high voltage potential greater than the voltage value of the drive unit control signal V _G , Therefore, the transistor T31 operates in the saturation region and its threshold voltage is V _thT31 , so the first terminal of the liquid crystal capacitor C _LC is charged to the voltage value of V _DATA +V _thT33 -V _thT31 .

In this embodiment, since the display data signal DATA is stored by the first storage capacitor C _ST1 , the liquid crystal capacitor C _LC will not be directly affected by the gate control signal G[n] of the nth stage, and the liquid crystal capacitor can be effectively reduced. C _LC decreases the capacitance value due to the high frequency of the electric field. In addition, in this embodiment, when the threshold voltage V _thT31 of the transistor T31 is the same or close to the threshold voltage V _thT33 of the transistor T33, that is, when the transistor T31 and the transistor T33 have the same device characteristics, the voltage stored in the liquid crystal capacitor C _LC The value is the display voltage potential V _DATA , and the pixel 14 can directly use the display voltage potential V _DATA stored in the liquid crystal capacitor C _LC to correctly display the data to be displayed, which can reduce the brightness of the display data signal DATA caused by the different characteristics of the elements in the pixel 14 recession etc.

Next, please refer to FIG. 4A. FIG. 4A is the third embodiment of the pixel circuit of the present invention. In this embodiment, the pixel 14 includes a liquid crystal capacitor C _LC , a first storage capacitor C _ST1 , a storage capacitor C _ST , a driving unit 41, a heavy setting unit 42, compensation unit 43 and display data signal input unit 44, wherein the liquid crystal capacitor C _LC has a first end and a second end, the second end of the liquid crystal capacitor C _LC is electrically coupled to the common mode voltage V _COM , the first The storage capacitor C _ST1 has a first terminal and a second terminal, the second terminal of the first storage capacitor C _ST1 is electrically coupled to the first low voltage potential GND, the storage capacitor C _ST has a first terminal and a second terminal, and stores The first end of the capacitor C _ST is electrically coupled to the first end of the liquid crystal capacitor C _LC , the second end of the storage capacitor C _ST is electrically coupled to the common mode voltage V _COM , and the storage capacitor C _ST is used to connect the liquid crystal capacitor C The voltage lost by the liquid crystal capacitor C _LC is compensated in a steady state when the _LC is no longer charged by the transistor T41 .

The driving unit 41 includes a transistor T41, the transistor T41 is a source follower (Source Follower) structure, the transistor T41 has a first terminal, a second terminal and a control terminal, the first terminal of the transistor T41 is connected to the reset unit 42 and the compensation The unit 43 is electrically coupled, the control terminal of the transistor T41 is used to receive the driving unit control signal V _G and is electrically coupled to the compensation unit 43, the second terminal of the transistor T41 is electrically coupled to the first terminal of the liquid crystal capacitor C _LC catch.

The reset unit 42 includes a transistor T42, a transistor T43, and a transistor T44. The transistor T42 has a first end, a second end, and a control end. The first end of the transistor T42 is electrically coupled to the first high voltage potential _VDD . The transistor T42 The control terminal receives the control signal S1, the second terminal of the transistor T42 is electrically coupled to the first terminal of the transistor T41 and the compensation unit 43, the transistor T43 has a first terminal, a second terminal and a control terminal, and the first terminal of the transistor T43 is connected to the first terminal of the transistor T43. The display data signal input unit 44 is electrically coupled to the first end of the first storage capacitor C _ST1 , the control end of the transistor T43 receives the control signal S2, the second end of the transistor T43 is connected to the second end of the first storage capacitor C _ST1 and The first low voltage potential GND is electrically coupled, the transistor T44 has a first terminal, a second terminal and a control terminal, the first terminal of the transistor T44 is electrically coupled to the first terminal of the liquid crystal capacitor C _LC , and the control terminal of the transistor T44 Receiving the control signal S2, the second end of the transistor T44 is electrically coupled to the second end of the first storage capacitor C _ST1 and the first low voltage potential GND.

The compensation unit 43 includes a transistor T45, which has a first terminal, a second terminal and a control terminal. The first terminal of the transistor T45 is electrically coupled to the first terminal of the transistor T41 and the second terminal of the transistor T42. The second terminal of the transistor T45 The terminal is electrically coupled to the control terminal of the transistor T41 and the display data signal input unit 44, and the control terminal of the transistor T45 is used to receive the control signal S2.

The display data signal input unit 44 includes a transistor T46 and a second storage capacitor C _ST2 , the transistor T46 has a first terminal, a second terminal and a control terminal, and the first terminal of the transistor T46 is electrically coupled to the data line 121 of FIG. 1 to receive The display data signal DATA, the second end of the transistor T46 is electrically coupled with the first end of the transistor T43 and the first end of the first storage capacitor C _ST1 , and the control end of the transistor T46 is used to connect with the gate line 131 of FIG. 1 Electrically coupled to receive the nth stage gate control signal G[n], the second storage capacitor C _ST2 has a first terminal and a second terminal, the second storage capacitor C _ST2 is electrically coupled to the first storage capacitor C _ST1 Between the transistor T45, the first end of the second storage capacitor C _ST2 is electrically coupled to the second end of the transistor T46, and the second end of the second storage capacitor C _ST2 is electrically coupled to the second end of the transistor T45, The voltage value of the second terminal of the second storage capacitor C _ST2 is equal to the voltage value of the aforementioned drive unit control signal V _G .

Please refer to FIG. 4B. FIG. 4B includes a timing diagram of the gate control signal G[n] of the nth level, control signal S1, control signal S2 and display data signal DATA. The implementation of the pixel circuit is described below in conjunction with FIG. 4A and FIG. 4B. How it works in Example 3.

Firstly, in the time period T1 in FIG. 4B , the control signal S1 and the control signal S2 are high voltage potentials, which can be logic high voltage potentials, and the nth stage gate control signal G[n] is low voltage potentials, the low voltage potentials The potential can be a logic low voltage potential, so the transistor T42, the transistor T43, the transistor T44 and the transistor T45 are turned on, the transistor T46 is turned off, and the second terminal of the transistor T42 is the voltage of the first high voltage potential V _DD because the transistor T42 is turned on. value, the transistor T45 is turned on and the driving unit control signal V _G is reset to the second high voltage potential V _GH which is slightly lower than the first high voltage potential V _DD , in addition, because the transistor T43 and the transistor T44 are turned on, the first The first terminals of the storage capacitor C _ST1 , the second storage capacitor C _ST2 , the storage capacitor C _ST and the liquid crystal capacitor C _LC are reset to the first low voltage level GND. Then in the period T2, the control signal S1 is at a low voltage potential, which can be a logic low voltage potential, the control signal S2 is at a high voltage potential, the nth stage gate control signal G[n] is at a low voltage potential, and the transistor T42 And the transistor T46 is turned off, the transistor T43, the transistor T44 and the transistor T45 are turned on, the voltage value of the drive unit control signal V _G is discharged from the second high voltage potential V _GH to a compensation voltage potential through the transistor T45, the transistor T41 and the transistor T44 , that is, the voltage value of the threshold voltage V _thT41 of the transistor T41. In addition, the transistor T43 and the transistor T44 are still turned on, so the first end of the first storage capacitor C _ST1 , the first end of the second storage capacitor C _ST2 , and the storage capacitor C The first terminal of the _ST and the first terminal of the liquid crystal capacitor C _LC are still reset to the first low voltage level GND. During the period T3, the first control signal S1 is at a low voltage level, the second control signal S2 is at a low voltage level, and the nth stage gate control signal G[n] is at a high voltage level, which may be a logic high voltage Potential, the display data signal DATA has a display voltage potential V _DATA for display, the transistor T46 is turned on, and the transistor T42, transistor T43, transistor T44, and transistor T45 are turned off. At this time, the first end of the first storage capacitor C _ST1 The voltage value is the display voltage potential V _DATA because the transistor T46 is turned on, and the voltage potential of the second terminal of the second storage capacitor C _ST2 is increased from the threshold voltage V _thT41 to the voltage of V _thT41 +V _DATA due to the coupling of the second storage capacitor C _ST2 value, that is, the voltage value of the driving unit control signal V _G is increased to V _thT41 +V _DATA . Then at time T4, the first control signal S1 is at a high voltage potential, the second control signal S2 is at a low voltage potential, the nth stage gate control signal G[n] is at a low voltage potential, the transistor T42 is turned on, the transistor T43, the transistor T44, the transistor T45 and the transistor T46 are closed, so the voltage value of the first terminal of the transistor T41 is higher than the first high voltage potential V _DD of the drive unit control signal V _G , so the transistor T41 operates in the saturation region, so that the drive unit control signal V _G charges the liquid crystal capacitor C _LC , and since the drive unit control signal V _G has been compensated to the voltage value of V _thT41 +V _DATA in the period T3, when the drive unit control signal V _G charges the liquid crystal capacitor C _LC via the transistor T41, the transistor The voltage drop of the critical voltage V _thT41 of T41 makes the first terminal of the liquid crystal capacitor C _LC charge to the voltage value of V _thT41 +V _DATA -V _thT41 , that is, the voltage value of the display voltage potential V _DATA .

In this embodiment, since the display data signal DATA is stored by the first storage capacitor C _ST1 , the liquid crystal capacitor C _LC will not be directly affected by the gate control signal G[n] of the nth stage, and the liquid crystal capacitor can be effectively reduced. The capacitance value of C _LC decreases due to the high frequency of the electric field. In addition, in this embodiment, the threshold voltage V _thT41 of the transistor T41 can be directly compensated without considering the characteristics of other components, so that the pixel 14 can be directly used by the liquid crystal capacitance C The display voltage potential V _DATA stored in the _LC correctly displays the data to be displayed, reducing the occurrence of brightness degradation or inconsistency of the display data signal DATA due to different device characteristics in the pixel 14 .

According to the above-mentioned content, the present invention can further summarize the operation method of the pixel circuit, please refer to FIG. 5, the steps include: using the reset unit to reset the liquid crystal capacitor C _LC to a low voltage potential (step 501); Compensate the drive unit control signal V _G (step 502); make the first storage capacitor store a storage potential, store the potential and associate with the above-mentioned display data signal (step 503); use the drive unit control signal V _G to make the liquid crystal capacitor C _LC A display potential is stored, the display potential being associated with the display data signal (step 504).

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the scope of the patent application to be paid later.

Claims (11)

1. an image element circuit, is characterized in that, it comprises:

One liquid crystal capacitance, it has a first end and one second end, this second end of this liquid crystal capacitance and a common mode voltage electric property coupling;

One first storage capacitors, it has a first end and one second end, this second end of this first storage capacitors and one first low voltage potential electric property coupling;

One driver element, with this first end electric property coupling of this liquid crystal capacitance, this driver element is the display current potential stored in order to control this liquid crystal capacitance according to a driver element control signal;

One compensating unit, with this driver element electric property coupling, in order to compensate this driver element control signal according to one first control signal; And

One reset cell, this driver element of electric property coupling, this compensating unit and this first storage capacitors, in order to reset the voltage potential of this first end of this driver element control signal and this liquid crystal capacitance according to one second control signal.

2. image element circuit as claimed in claim 1, it is characterized in that, this driver element more comprises:

One the first transistor, it has a first end, one second end and a control end, this first end of this first transistor receives an electric potential signal, this control end of this first transistor and this first end electric property coupling of this first storage capacitors, in order to receive this driver element control signal, this second end of this first transistor and this first end electric property coupling of this liquid crystal capacitance.

3. image element circuit as claimed in claim 2, it is characterized in that, this compensating unit more comprises:

One transistor seconds, it has a first end, one second end and a control end, this second end of this transistor seconds and this first end of this this first storage capacitors of control end electric property coupling; And

One third transistor, it has a first end, one second end and a control end, this first end of this third transistor receives a display data signal, this control end of this third transistor receives this first control signal, this the second end of this third transistor and this first end electric property coupling of this transistor seconds, this first control signal is one n-th grade of grid control signal.

4. image element circuit as claimed in claim 3, it is characterized in that, this reset cell more comprises:

One the 4th transistor, it has a first end, one second end and a control end, this first end of 4th transistor receives one first high voltage potential, this control end of 4th transistor receives this second control signal, this second end of 4th transistor and this first end electric property coupling of this first storage capacitors, this second control signal is one (n-1)th grade of grid control signal.

5. image element circuit as claimed in claim 4, it is characterized in that, this third transistor (t34) is used to the closedown of one first period, 4th transistor is used to the unlatching of this first period, be this first high voltage potential to reset this driver element control signal, this the first transistor is used to the unlatching of this first period, with this electric potential signal through one second low voltage potential, resets this first end of this liquid crystal capacitance for this second low voltage potential; 4th transistor is used to the closedown of one second period, this third transistor and this transistor seconds are used to the unlatching of this second period, to make the voltage of this first end of this first storage capacitors by the current potential charge/discharge of this first high voltage potential according to this display display data signal; This electric potential signal was used to for one the 3rd period provides one second high voltage potential, and this first transistor is used to the current potential of the 3rd period according to this first end of this liquid crystal capacitance of control of Electric potentials of this first storage capacitors.

6. image element circuit as claimed in claim 1, it is characterized in that, this image element circuit more comprises:

One display data signal input block, with this reset cell electric property coupling, in order to determine whether export a display data signal according to one n-th grade of grid control signal.

7. image element circuit as claimed in claim 6, it is characterized in that, this driver element comprises:

One the first transistor, it has a first end, one second end and a control end, this first end of this first transistor and this reset cell and this compensating unit electric property coupling, this control end of this first transistor be receive this driver element control signal and with this compensating unit electric property coupling, this second end of this first transistor and this first end electric property coupling of this liquid crystal capacitance.

8. image element circuit as claimed in claim 7, it is characterized in that, this reset cell more comprises:

One transistor seconds, it has a first end, one second end and a control end, this first end of this transistor seconds and one first high voltage potential electric property coupling, this control end of this transistor seconds in order to receive this second control signal, this second end of this transistor seconds and this first end of this first transistor and this compensating unit electric property coupling;

One third transistor, it has a first end, one second end and a control end, this first end of this third transistor and this first end electric property coupling of this display data signal input block and this first storage capacitors, this control end of this third transistor in order to receive this first control signal, this second end of this third transistor and this first low voltage potential electric property coupling; And

One the 4th transistor, it has a first end, one second end and a control end, this first end of 4th transistor and this first end electric property coupling of this liquid crystal capacitance, this control end of 4th transistor in order to receive this first control signal, this second end of the 4th transistor and this first low voltage potential electric property coupling.

9. image element circuit as claimed in claim 8, it is characterized in that, this compensating unit more comprises:

One the 5th transistor, it has a first end, one second end and a control end, this the second end electric property coupling of this first end of 5th transistor and this first end of this first transistor and this transistor seconds, this the second end of the 5th transistor and this control end of this first transistor and this display data signal input block electric property coupling, this control end of the 5th transistor is in order to receive this first control signal.

10. image element circuit as claimed in claim 9, it is characterized in that, this display data signal input block comprises:

One the 6th transistor, it has a first end, one second end and a control end, this first end of 6th transistor is in order to receive this display data signal, this first end electric property coupling of this second end of 6th transistor and this first end of third transistor and this first storage capacitors, this control end of the 6th transistor is in order to receive this n-th grade of grid control signal; And

One second storage capacitors, it has a first end and one second end, this first end of this second storage capacitors and this second end electric property coupling of the 6th transistor, this second end of this second storage capacitors and this second end electric property coupling of the 5th transistor.

11. image element circuits as claimed in claim 10, it is characterized in that, 6th transistor is used to the closedown of one first period, this third transistor and the 4th transistor are used to the unlatching of this first period, current potential is stored for this first low voltage potential with one of this first end and this first storage capacitors of resetting this liquid crystal capacitance, this transistor seconds and the 5th transistor were opened in this first period, were one second high voltage potential to reset this driver element control signal; This transistor seconds and the 6th transistor are used to the closedown of one second period, this third transistor, the 4th transistor and the 5th transistor are used to the unlatching of this second period, are discharged to a bucking voltage current potential to make this driver element control signal by this second high voltage potential; 6th transistor is used to the unlatching of one the 3rd period, this transistor seconds, this third transistor, the 4th transistor and the 5th transistor are used to the closedown of the 3rd period, to make the voltage of this first end of this second storage capacitors by the current potential charge/discharge of this first low voltage potential according to this display data signal, the current potential of this driver element control signal is by the current potential charge/discharge of this bucking voltage current potential according to this display data signal; This third transistor, the 4th transistor, the 5th transistor and the 6th transistor are used to the closedown of one the 4th period, this transistor seconds was used to for the 4th period and opens, and was used to for the 4th period makes this liquid crystal capacitance store this display voltage potential according to the current potential of this driver element control signal to make this first transistor.