CN104952715B - The forming method of semiconductor structure - Google Patents

Abstract

A method for forming a semiconductor structure, comprising: providing a semiconductor substrate, on which a plurality of floating gate structures and a control gate dielectric layer located on the top surface of the floating gate structures are formed; A first patterned control gate material layer with a continuous pattern, the first patterned control gate material layer covers part of the floating gate dielectric layer on several floating gate structures; a mask layer is formed on the semiconductor substrate, the The mask layer exposes part of the first patterned control gate material layer above the floating gate structure and the semiconductor substrate on both sides of the part of the first patterned control gate material layer; using the mask layer as a mask, removing the first patterned control gate material layer not covered by the mask layer to form mutually disconnected control gates; removing the mask layer; The wall surfaces form side walls. The method can improve the reliability of the flash memory.

Description

Formation method of semiconductor structure

technical field

The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor structure.

Background technique

In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuits, among which storage devices account for a considerable proportion of integrated circuit products, such as RAM (random access memory), DRAM (dynamic Random access memory), ROM (read-only memory), EPROM (erasable programmable read-only memory), FLASH (flash memory) and FRAM (ferroelectric memory), etc. The development of flash memory devices in memory is particularly rapid. Its main feature is that it can keep the stored information for a long time without power on. It has many advantages such as high integration, fast access speed and easy erasure, so it has been widely used in many fields such as microcomputer and automatic control. a wide range of applications.

The flash memory structure generally includes: a floating gate dielectric layer on the surface of the substrate, a floating gate on the surface of the floating gate dielectric layer, a control gate dielectric layer on the surface of the floating gate, and a control gate on the surface of the control gate dielectric layer. With the continuous improvement of the integration level of integrated circuits, the process nodes of semiconductors are also reduced. Due to the limitation of lithography resolution, a single patterning process cannot form a control gate with high morphology quality. In order to improve the topographical quality of the formed control gate, the control gate is usually formed by a double patterning method. Specifically, the double patterning method includes: after forming a control gate material layer on the surface of the control gate dielectric layer, performing first patterning on the control gate material layer to form a continuous control gate covering multiple memory cells. and then performing second patterning on the continuous control gates, so that the control gates between adjacent memory cells are disconnected to form independent control gates.

The flash memory formed by the prior art often has problems such as short circuit, and the reliability of the flash memory needs to be further improved.

Contents of the invention

The problem solved by the invention is to provide a method for forming a semiconductor structure, which can improve the reliability of flash memory devices.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, on which a plurality of floating gate structures and a control gate dielectric layer located on the top surface of the floating gate structures are formed, The floating gate structure includes a floating gate dielectric layer on the surface of the semiconductor substrate and a floating gate on the surface of the floating gate dielectric layer; forming a first patterned control gate material layer with a continuous pattern on the semiconductor substrate, The first patterned control gate material layer covers part of the floating gate dielectric layer on several floating gate structures; a mask layer is formed on the semiconductor substrate, and the mask layer exposes part of the first floating gate structure above the floating gate structure. A patterned control gate material layer and semiconductor substrates located on both sides of the part of the first patterned control gate material layer; using the mask layer as a mask to remove the first pattern not covered by the mask layer Thinning the control gate material layer to form mutually disconnected control gates; removing the mask layer; forming sidewalls on the floating gate structure, the control gate dielectric layer and the side wall surfaces of the control gate.

Optionally, an anisotropic etching process is used to remove the exposed first patterned control gate material layer.

Optionally, the anisotropic etching process is a dry etching process.

Optionally, the etching rate of the first patterned control gate material layer in the dry etching process is greater than the etching rate of the control gate dielectric layer.

Optionally, the control gate is etched using a plasma etching process.

Optionally, the etching gas used in the plasma etching process includes Cl ₂ and HBr, and the carrier gas is He, wherein the flow rate of Cl ₂ is 80 sccm-2000 sccm, the flow rate of HBr is 50 sccm-2000 sccm, and the flow rate of He is 100sccm～2000sccm.

Optionally, the mask layer also exposes part of the surface of the control gate dielectric layer not covered by the first patterned control gate material layer.

Optionally, the material of the control gate dielectric layer includes a first silicon oxide layer on the surface of the floating gate, a silicon nitride layer on the surface of the first silicon oxide layer, and a second silicon oxide layer on the surface of the silicon nitride layer.

Optionally, the method for forming the first patterned control gate material layer includes: forming a control gate material layer on the surface of the semiconductor substrate, the control gate material layer covering the control gate dielectric layer; Form a first patterned mask layer on the surface of the layer; use the first patterned mask layer as a mask to etch the control gate material layer to form a first patterned control gate material layer; remove the first patterned mask layer.

Optionally, the material of the control gate material layer is polysilicon.

Optionally, the first patterned control gate material layer on the surface of the control gate dielectric layer has a thickness of 1200 angstroms to 1700 angstroms.

Optionally, the material of the floating gate is polysilicon.

Optionally, the floating gate has a thickness of 900 angstroms to 1300 angstroms.

Optionally, the material of the floating gate dielectric layer includes silicon oxide, silicon oxynitride or hafnium oxide.

Optionally, the material of the sidewall includes one or more of silicon oxide, silicon nitride or silicon oxynitride.

Optionally, the forming method of the sidewall includes: on the surface of the semiconductor substrate, the top surface of the control gate dielectric layer, the top surface of the control gate, the sidewall surface of the floating gate dielectric layer, the sidewall surface of the floating gate, the control gate dielectric layer layer sidewall surface and control gate sidewall surface to form a sidewall material layer; using a maskless etching process to remove the sidewall material layer located on the top surface of the control gate, the top surface of the control gate dielectric layer and the surface of the semiconductor substrate to form a covering The floating gate dielectric layer, the floating gate, the control gate dielectric layer, and the side wall of the side wall surface of the control gate.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, after the floating gate structure is formed on the semiconductor substrate, a first patterned control gate material layer with a continuous pattern is formed on the semiconductor substrate, and the first patterned control gate material layer covers several floating gates. A part of the floating gate dielectric layer on the gate structure; then, a mask layer is formed on the semiconductor substrate, and the mask layer exposes a part of the first patterned control gate material layer above the floating gate structure and the Part of the semiconductor substrate on both sides of the first patterned control gate material layer; using the mask layer as a mask, after removing the first patterned control gate material layer not covered by the mask layer, and then on the The floating gate structure, the control gate dielectric layer and the side wall surfaces of the control gate form side walls. The opening of the mask layer is relatively large, so the mask layer not only exposes part of the first patterned control gate material layer but also exposes the semiconductor substrate on both sides of the part of the first patterned control gate material layer, When removing the uncovered first patterned control gate material layer, since the first patterned control gate material layer can be completely exposed to the etching gas, the uncovered first patterned The control gate material layer can be completely removed, so that the finally formed control gates are completely disconnected, avoiding problems such as short circuits between control gates between different memory cells, thereby improving the reliability of the formed flash memory.

Further, an anisotropic dry etching process can be used to remove the first patterned control gate material layer not covered by the mask layer, and the etching rate of the first patterned control gate material layer is greater than The etch rate of the control gate dielectric layer, so that in the process of removing the first patterned control gate material layer, the control gate dielectric layer and the floating gate below the control gate dielectric layer will not be damaged.

Description of drawings

1 to 4 are structural schematic diagrams of a process for forming a semiconductor structure according to an embodiment of the present invention;

5 to 14 are structural schematic diagrams of the process of forming a semiconductor structure according to another embodiment of the present invention.

detailed description

As mentioned in the background art, the flash memory formed in the prior art often has problems such as failure or short circuit.

The present invention provides an embodiment of the formation process of a semiconductor structure. Please refer to FIG. 1 to FIG. 4 , which are structural schematic diagrams of the semiconductor formation process of the embodiment.

Please refer to FIG. 1 , which is a schematic top view of a continuous control gate 20 after the first patterning is performed on the floating gate 10 . In FIG. 1 , the control gate dielectric layer, semiconductor substrate, etc. are not shown.

The floating gates 10 are arranged in parallel, and the continuous control gates 20 cover several floating gates 10. Since the control gates 20 belong to different memory cells, the second patterning of the control gates 20 is required to remove Part of the control gates 21 in the dotted frame in FIG. 1 is used to disconnect the continuous control gates 20, so as to avoid problems such as short circuits between control gates of different memory cells.

Please refer to FIG. 2 , which is a schematic cross-sectional view of FIG. 1 along the secant line AA'.

A floating gate dielectric layer 11 , a floating gate 10 , a control gate dielectric layer 22 , and a control gate 21 are formed on the semiconductor substrate 30 .

Referring to FIG. 3 , sidewalls 40 are formed on the floating gate dielectric layer 11 , the floating gate 10 , the control gate dielectric layer 22 , and the sidewall surfaces of the control gate 21 .

Usually, the spacer 40 is formed when the transistors in the peripheral circuit of the flash memory device form the spacer.

Referring to FIG. 4 , a second patterning process is performed to remove the control gate 21 (please refer to FIG. 3 ).

A mask layer is formed on the semiconductor substrate to cover other areas except the control gate 21 , and then the control gate 21 is etched to remove the control gate 21 .

Since the sidewalls 21 protect the sidewalls of the control gate 21 after the formation of the spacers 40, during the process of etching the control gate 21, as the thickness of the control gate 21 decreases, there will be gaps between the sidewalls 40. A groove appears, and since the width of the control gate 21 is small, the aspect ratio of the groove will gradually increase, and the concentration of the etching gas at the bottom of the groove will be smaller than the concentration of the etching gas at the top of the groove. After etching the control gate 21 to the surface of the control gate dielectric layer 22, part of the control gate material 21a that has not been removed will remain at the bottom sidewall and top corner of the groove, and the remaining control gate material 21a It is possible that the control gate 20 (please refer to FIG. 1 ) remains in a continuous state. After the memory is subsequently formed, a short circuit will occur between adjacent memory cells of the memory, resulting in failure of the memory.

In order to solve the above problems, in another embodiment of the present invention, another method for forming the semiconductor structure is proposed. After removing part of the control gate, the spacer is formed.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Please refer to FIG. 5 , a semiconductor substrate 100 is provided, and a floating gate structure is formed on the semiconductor substrate 100. The floating gate structure includes a floating gate dielectric layer 201 on the surface of the semiconductor substrate 100 and a floating gate dielectric layer on the surface of the floating gate dielectric layer. The floating gate 202 on the surface of 201.

The forming method for forming the floating gate structure includes: sequentially forming a floating gate dielectric material layer and a floating gate material layer on the surface of the floating gate dielectric material layer on the surface of the semiconductor substrate 100; forming a floating gate material layer on the surface of the floating gate material layer A mask layer, the mask layer defines the size and position of the subsequently formed floating gate structure; using the mask layer as a mask, the floating gate material layer and the floating gate dielectric material layer are etched to form floating gate structure.

The material of the floating gate dielectric layer 201 is an oxide such as silicon oxide, silicon oxynitride, or a high-K dielectric material such as hafnium oxide.

The material of the floating gate 202 is polysilicon. The thickness of the floating gate 202 is 900 angstroms to 1300 angstroms.

In this embodiment, several floating gate structures arranged in parallel are formed on the semiconductor substrate 100 as the floating gate structures of multiple memory cells of the flash memory.

Referring to FIG. 6 , a control gate dielectric layer 203 is formed on the surface of the floating gate 202 .

The method for forming the control gate dielectric layer 203 includes: forming a control gate dielectric material layer on the surface of the semiconductor substrate 100 and the surface of the floating gate structure; etching the control gate dielectric material layer to form a control gate on the surface of the floating gate 202. gate dielectric layer 203 .

In this embodiment, the control gate dielectric material layer is an ONO stack structure, including a first silicon oxide layer, a silicon nitride layer on the surface of the first silicon oxide layer, and a second silicon oxide layer on the surface of the silicon nitride layer. .

The control gate dielectric layer is used to isolate the subsequently formed control gate and the floating gate 202 .

Referring to FIG. 7 , a first patterned control gate material layer 204 is formed on the surface of the control gate dielectric layer 203 and the surface of the semiconductor substrate 100 . FIG. 7 is a schematic top view after forming the first patterned control gate material layer 204 .

In order to improve the topographic quality of the finally formed control gate, in this embodiment, a double patterning process is used to form the control gate, which specifically includes: after forming a control gate material layer on the semiconductor substrate 100 and the floating gate structure, forming the control gate The first patterning treatment is performed on the control gate material layer to form the first patterned control gate material layer 204; the second patterning treatment is performed on the first patterned control gate material layer 204 to form the final control gate. Compared with forming the control gate by single-patterning, the formation of the control gate by a double-patterning process can reduce the difficulty of the single-patterning process and improve the shape quality of the formed control gate.

The method for forming the first patterned control gate material layer 204 includes: forming a control gate material layer on the surface of the semiconductor substrate 100, the control gate material layer covering the control gate dielectric layer 203; A first patterned mask layer is formed on the surface; the control gate material layer is etched using the first patterned mask layer as a mask to form a first patterned control gate material layer 204 .

The material of the control gate material layer is polysilicon.

The first patterned control gate material layer 204 covers part of the control gate dielectric layer 203 above the floating gate structures. In this embodiment, the pattern of the first patterned control gate material layer 204 is a continuous pattern, and the second patterning process is required to disconnect the first patterned control gate material layer 204 to form an independent control grid. The first patterned control gate material layer 204 located on the surface of the control gate dielectric layer 203 has a thickness of 1200 angstroms to 1700 angstroms.

In this embodiment, part of the first patterned control gate material layer 204a within the dotted line box in FIG. pole. In other examples of the present invention, the removed part of the first patterned control gate material layer 204 may also be in other positions, and the position of the disconnection can be adjusted according to the requirements of the actually formed flash memory device.

Please refer to FIG. 8 , which is a schematic cross-sectional view along the secant line BB' in FIG. 7 .

Referring to FIG. 9 , a second patterned mask layer 300 is formed on the semiconductor substrate 100 (please refer to FIG. 7 ), and the second patterned mask layer 300 exposes a portion of the second layer located on the control gate dielectric layer. A patterned control gate material layer 204a and part of the semiconductor substrate 100 on both sides of the first patterned control gate material layer 204a. Fig. 10 is a schematic cross-sectional view along line CC' in Fig. 9 .

In this embodiment, the opening of the second patterned mask layer 300 is relatively large, exposing the first patterned control gate material layer 204a and the semiconductor substrate 100 on both sides thereof, and also exposing the adjacent first patterned control gate material layer 204a. The control gate dielectric layer 203 on the surface of the floating gate 202 between the control gate material layers 204a.

The material of the second patterned mask layer 300 is a mask material such as silicon nitride, silicon oxide or photoresist. The opening of the second patterned mask layer 300 is relatively large, which can improve the process window of the photolithography or etching process in the process of forming the mask layer 300, and reduce the cost of forming the second patterned mask layer 300. difficulty.

Please refer to FIG. 11, using the second patterned mask layer 300 (please refer to FIG. 9) as a mask, remove the first patterned control gate material layer 204a (please refer to FIG. 9), and the remaining part of the first The patterned control gate material layer 204 serves as a control gate. Please refer to FIG. 12 , which is a schematic cross-sectional view along the secant line DD' in FIG. 11 .

The first patterned control gate material layer 204a may be removed by using an anisotropic dry etching process. In the anisotropic dry etching process, there is a relatively high etching selectivity between the material of the first patterned control gate material layer 204a and the control gate dielectric layer 203, thus, during the etching process, The uncovered control gate dielectric layer 203 on both sides of the first patterned control gate material layer 204a will not be damaged.

In this embodiment, the anisotropic dry etching process is a plasma etching process. The etching gas used in the plasma etching process is a mixed gas of Cl ₂ and HBr, and the carrier gas is He, wherein the flow rate of Cl ₂ is 80 sccm-2000 sccm, the flow rate of HBr is 50 sccm-2000 sccm, and the flow rate of He is 100 sccm ~2000 sccm.

Due to the large opening of the second patterned mask layer 300, during the etching process, the etching gas can fully contact the first patterned control gate material layer 204a, so that the first pattern can be completely removed. control gate material layer 204a to completely disconnect the remaining first patterned control gate material layer 204 (please refer to FIG. The performance of the formed flash memory device is improved.

In this embodiment, since the material of the first patterned control gate material layer 204a is polysilicon, the material of the semiconductor substrate 100 is silicon, and the second patterned mask layer 300 also exposes the Part of the semiconductor substrate 100 on both sides of the first patterned control gate material layer 204a, so in the process of etching the first patterned control gate material layer 204a, the semiconductor substrate 100 will also be etched to a certain extent. However, since there is a large height difference between the first patterned control gate material layer 204a and the semiconductor substrate 100, the concentration of the etching gas in contact with the first patterned control gate material layer 204a is relatively high. It has a higher etching rate, so when the first patterned control gate material layer 204a is etched and removed, the semiconductor substrate 100 on both sides thereof is less etched. Moreover, the semiconductor substrate 100 on both sides of the first patterned control gate material layer 204a does not constitute a part of the flash memory unit, so it has no influence on the performance of the flash memory device.

Referring to FIG. 13 , the second patterned mask layer 300 (please refer to FIG. 11 ) is removed.

The second patterned mask layer 300 is removed by a wet etching process, and an appropriate etching solution is selected according to the material of the second patterned mask layer 300, which may be hydrofluoric acid, phosphoric acid or nitric acid solution. one or several. When the material of the second patterned mask layer 300 is photoresist, the second patterned mask layer 300 may also be removed by an ashing process.

After removing the second patterned mask layer 300, the disconnected control gate 204b is exposed, and the control gate 204b is the remaining part after removing the part of the first patterned control gate material layer 204a (please refer to FIG. 9 ). The first patterned control gate material layer. The control gates 204b are disconnected from each other and serve as control gates of different memory cells respectively.

Referring to FIG. 14 , sidewalls 400 are formed on the surface of the sidewalls of the floating gate dielectric layer 201 , the floating gate 202 , the control gate dielectric layer 203 , and the control gate 204 b (please refer to FIG. 12 ). FIG. 14 is a schematic diagram after forming sidewalls 400 on the surface of the sidewalls of the floating gate dielectric layer 201 , the floating gate 202 , and the control gate dielectric layer 203 in FIG. 12 .

The material of the sidewall 400 is one or more of silicon oxide, silicon nitride or silicon oxynitride. The formation method of the spacer 400 includes: on the surface of the semiconductor substrate 100, the top surface of the control gate dielectric layer 203, the top surface of the control gate 204b, the side wall surface of the floating gate dielectric layer 201, the side wall surface of the floating gate 202, the control gate The sidewall surface of the dielectric layer 203 and the sidewall surface of the control gate 204b form a sidewall material layer; using a maskless etching process, remove the sidewalls located on the top surface of the control gate 204b, the top surface of the control gate dielectric layer 203 and the surface of the semiconductor substrate 100 The wall material layer forms the sidewall 400 covering the sidewall surfaces of the floating gate dielectric layer 201, the floating gate 202, the control gate dielectric layer 203, and the control gate 204b.

In this embodiment, after the first patterned control gate material layer 204 is formed, a second patterning treatment is performed on the first patterned control gate material layer 204 to remove part of the first patterned control gate material layer 204a, A completely disconnected control gate 204b is formed, and then spacers 400 are formed. However, if the sidewalls are first formed and the first patterned control gate material layer is etched, since the sidewalls are formed first, both sides of the part of the first patterned control gate material layer that need to be removed are protected by the sidewalls. Only the surface can be exposed to the etching gas, and as the etching process continues, a groove will be formed between the sidewalls. Since the width of the first patterned control gate material layer is generally small, the groove's The aspect ratio is large, and the etching gas concentration at the bottom of the groove is small, so it is easy to leave part of the control gate material at the bottom of the groove, so that the finally formed control gates cannot be completely disconnected and affect the performance of the flash memory device. In this embodiment, the second patterning process is performed before forming the sidewall 400. During the process of removing part of the first patterned control gate material layer 204a, there are no sidewalls on both sides of the part of the first patterned control gate material layer 204a. protection, can be fully in contact with the etching gas, so that the part of the first patterned control gate material layer 204a can be completely removed, so that the control gates of different cells that are finally formed are completely disconnected, which can improve the performance of the formed flash memory. reliability.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (16)

1. A method for forming a semiconductor structure, comprising: A semiconductor substrate is provided, on which a number of floating gate structures and a control gate dielectric layer located on the top surface of the floating gate structure are formed, and the floating gate structure includes a floating gate dielectric layer located on the surface of the semiconductor substrate and a control gate dielectric layer located on the surface of the semiconductor substrate. a floating gate on the surface of the floating gate dielectric layer; A first patterned control gate material layer having a continuous pattern is formed on the semiconductor substrate, and the first patterned control gate material layer covers part of the floating gate dielectric layer on several floating gate structures; A mask layer is formed on the semiconductor substrate, and the mask layer exposes a part of the first patterned control gate material layer above the floating gate structure and parts of the first patterned control gate material layer on both sides of the part of the first patterned control gate material layer. semiconductor substrate; Using the mask layer as a mask, removing the first patterned control gate material layer not covered by the mask layer to form mutually disconnected control gates; removing the mask layer; A side wall is formed on the surface of the floating gate structure, the control gate dielectric layer and the side wall of the control gate. 2 . The method for forming a semiconductor structure according to claim 1 , wherein an anisotropic etching process is used to remove the exposed first patterned control gate material layer. 3 . 3. The method for forming a semiconductor structure according to claim 2, wherein the anisotropic etching process is a dry etching process. 4 . The method for forming a semiconductor structure according to claim 3 , wherein the etching rate of the first patterned control gate material layer in the dry etching process is greater than the etching rate of the control gate dielectric layer. 5 . The method for forming a semiconductor structure according to claim 4 , wherein the first patterned control gate material layer is etched by a plasma etching process. 6. The method for forming a semiconductor structure according to claim 5, wherein the etching gas used in the plasma etching process comprises Cl ₂ , HBr, and the carrier gas is He, wherein the flow rate of Cl ₂ is 80 sccm ~2000 sccm, the flow rate of HBr is 50 sccm-2000 sccm, and the flow rate of He is 100 sccm-2000 sccm. 7 . The method for forming a semiconductor structure according to claim 1 , wherein the mask layer also exposes a part of the surface of the control gate dielectric layer that is not covered by the first patterned control gate material layer. 8. The method for forming a semiconductor structure according to claim 1, wherein the material of the control gate dielectric layer comprises a first silicon oxide layer located on the surface of the floating gate, a silicon nitride layer located on the surface of the first silicon oxide layer layer, a second silicon oxide layer on the surface of the silicon nitride layer. 9. The method for forming a semiconductor structure according to claim 1, wherein the method for forming the first patterned control gate material layer comprises: forming a control gate material layer on the surface of the semiconductor substrate, the control gate material layer The gate material layer covers the control gate dielectric layer; a first patterned mask layer is formed on the surface of the control gate material layer; the control gate material layer is etched using the first patterned mask layer as a mask to form a second A patterned control gate material layer; removing the first patterned mask layer. 10 . The method for forming a semiconductor structure according to claim 9 , wherein the material of the control gate material layer is polysilicon. 11 . 11 . The method for forming a semiconductor structure according to claim 9 , wherein the first patterned control gate material layer on the surface of the control gate dielectric layer has a thickness of 1200 angstroms to 1700 angstroms. 12. The method for forming a semiconductor structure according to claim 1, wherein the material of the floating gate is polysilicon. 13 . The method for forming a semiconductor structure according to claim 1 , wherein the floating gate has a thickness of 900 angstroms to 1300 angstroms. 14. The method for forming a semiconductor structure according to claim 1, wherein the material of the floating gate dielectric layer comprises silicon oxide, silicon oxynitride or hafnium oxide. 15. The method for forming a semiconductor structure according to claim 1, wherein the material of the sidewall comprises one or more of silicon oxide, silicon nitride, or silicon oxynitride. 16. The method for forming the semiconductor structure according to claim 1, wherein the method for forming the sidewall comprises: on the surface of the semiconductor substrate, the top surface of the control gate dielectric layer, the top surface of the control gate, the floating gate The sidewall surface of the dielectric layer, the sidewall surface of the floating gate, the sidewall surface of the control gate dielectric layer, and the sidewall surface of the control gate form a sidewall material layer; the maskless etching process is used to remove the top surface of the control gate and the control gate dielectric layer. The top surface and the sidewall material layer on the surface of the semiconductor substrate form sidewalls covering the floating gate dielectric layer, the floating gate, the control gate dielectric layer, and the sidewall surfaces of the control gate.