CN104934491B - Photodiode, its preparation method and image sensing device - Google Patents
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Abstract
本申请公开了一种光电二极管、其制作方法及图像传感器件。其中光电二极管包括:N型掺杂区,形成在衬底的内部;第一P型掺杂区,形成在N型掺杂区的内部;第二P型掺杂区,形成在衬底中,位于N型掺杂区上方,且下表面与N型掺杂区相连。该制作方法包括:对衬底的上表面进行掺杂形成N型掺杂预备区;对N型掺杂预备区的内部进行掺杂,形成第一P型掺杂区;对衬底的上表面进行二次掺杂,以在第一P型掺杂区的上方形成第二P型掺杂区,并形成与第二P型掺杂区下表面相连的N型掺杂区。上述光电二极管中第一P型掺杂区会在N型掺杂区中形成PN结耗尽层,进而能够提高光电二极管的光电转换效率。
The application discloses a photodiode, its manufacturing method and an image sensing device. The photodiode includes: an N-type doped region formed inside the substrate; a first P-type doped region formed inside the N-type doped region; a second P-type doped region formed in the substrate, It is located above the N-type doped region, and the lower surface is connected to the N-type doped region. The manufacturing method includes: doping the upper surface of the substrate to form an N-type doping preparation area; doping the inside of the N-type doping preparation area to form a first P-type doping area; Perform secondary doping to form a second P-type doped region above the first P-type doped region, and form an N-type doped region connected to the lower surface of the second P-type doped region. In the photodiode, the first P-type doped region will form a PN junction depletion layer in the N-type doped region, thereby improving the photoelectric conversion efficiency of the photodiode.
Description
技术领域technical field
本申请涉及半导体集成电路制作技术领域,具体而言,涉及一种光电二极管、其制作方法及图像传感器件。The present application relates to the technical field of manufacturing semiconductor integrated circuits, in particular, to a photodiode, its manufacturing method and an image sensing device.
背景技术Background technique
光电二极管作为光电转换器件,可应用于CMOS图像传感器中。CMOS图像传感器的基本单元称为像素,其由1个光电二极管和3个或4个MOS晶体管构成,简称为3T类型或4T类型。其中,光电二极管用于将光信号转换成相应的电流信号,而MOS晶体管用于读取光电二极管转换的电流信号。As a photoelectric conversion device, a photodiode can be applied to a CMOS image sensor. The basic unit of a CMOS image sensor is called a pixel, which consists of a photodiode and 3 or 4 MOS transistors, referred to as 3T type or 4T type for short. Among them, the photodiode is used to convert the light signal into a corresponding current signal, and the MOS transistor is used to read the current signal converted by the photodiode.
图1为现有技术中一种4T类型的CMOS图像传感器的结构示意图。如图1所示,这种CMOS图形传感器包括:衬底10′和依次形成在该衬底10′上的光电二极管20′、转移晶体管30′和势阱40′,其中光电二极管20′包括朝向远离衬底10′的方向依次形成的N型掺杂区21′和P型掺杂区23′;在势阱40′上形成有源跟随器晶体管50′、复位晶体管60′、选择晶体管70′和浅沟槽隔离结构80′。转移晶体管30′位于光电二极管20′和势阱40′之间,且转移晶体管30′的源区与光电二极管20′相连接,转移晶体管30′的漏区与源跟随器晶体管50′相连接。FIG. 1 is a schematic structural diagram of a 4T type CMOS image sensor in the prior art. As shown in FIG. 1, this CMOS image sensor includes: a substrate 10', a photodiode 20', a transfer transistor 30' and a potential well 40' sequentially formed on the substrate 10', wherein the photodiode 20' includes a direction toward An N-type doped region 21' and a P-type doped region 23' are sequentially formed away from the substrate 10'; an active follower transistor 50', a reset transistor 60', and a selection transistor 70' are formed on the potential well 40' and shallow trench isolation structure 80'. The transfer transistor 30' is located between the photodiode 20' and the potential well 40', and the source region of the transfer transistor 30' is connected to the photodiode 20', and the drain region of the transfer transistor 30' is connected to the source follower transistor 50'.
图像传感器的性能(比如灵敏度、光谱响应等)与光电二极管的光电转换效率相关。然而,现有光电二极管的光电转换效率较低,导致光电二极管中的光电流较小,进而影响图像传感器的性能。技术人员尝试通过增加感光表面的粗糙度等方法来增加光电二极管的有效感光面积,但是该方法并不能解决光电二极管的光电转换效率较低的问题。The performance of the image sensor (such as sensitivity, spectral response, etc.) is related to the photoelectric conversion efficiency of the photodiode. However, the photoelectric conversion efficiency of existing photodiodes is low, resulting in a small photocurrent in the photodiodes, which in turn affects the performance of image sensors. Technologists try to increase the effective photosensitive area of the photodiode by increasing the roughness of the photosensitive surface, but this method cannot solve the problem of low photoelectric conversion efficiency of the photodiode.
发明内容Contents of the invention
本申请旨在提供一种光电二极管、其制作方法及图像传感器件,以解决现有技术中光电二极管的光电转换效率较低的问题。The purpose of the present application is to provide a photodiode, its manufacturing method and image sensing device, so as to solve the problem of low photoelectric conversion efficiency of the photodiode in the prior art.
为了实现上述目的,根据本申请的一个方面,提供了一种光电二极管,该光电二极管包括:N型掺杂区,形成在衬底的内部;第一P型掺杂区,形成在N型掺杂区的内部;第二P型掺杂区,形成在衬底中,位于N型掺杂区上方,且下表面与N型掺杂区相连。In order to achieve the above object, according to one aspect of the present application, a photodiode is provided, the photodiode includes: an N-type doped region formed inside the substrate; a first P-type doped region formed in the N-type doped Inside the impurity region; the second P-type doping region is formed in the substrate, located above the N-type doping region, and the lower surface is connected to the N-type doping region.
进一步地,在本申请上述的光电二极管中,光电二极管中包括一个或多个第一P型掺杂区,且第一P型掺杂区的总体积与N型掺杂区的体积之比<0.2。Further, in the photodiode mentioned above in this application, the photodiode includes one or more first P-type doped regions, and the ratio of the total volume of the first P-type doped regions to the volume of the N-type doped regions< 0.2.
进一步地,在本申请上述的光电二极管中,第一P型掺杂区中P型离子的掺杂量与N型掺杂区中N型离子的掺杂量之比为1.05~1.2。Further, in the photodiode mentioned above in the present application, the ratio of the doping amount of P-type ions in the first P-type doping region to the doping amount of N-type ions in the N-type doping region is 1.05˜1.2.
进一步地,在本申请上述的光电二极管中,光电二极管包括一个第一P型掺杂区时,第一P型掺杂区位于垂直于衬底表面的N型掺杂区的中心线上;包括多个第一P型掺杂区时,多个第一P型掺杂区对称地设置在垂直于衬底表面的N型掺杂区的中心线的两侧。Further, in the photodiode mentioned above in this application, when the photodiode includes a first P-type doped region, the first P-type doped region is located on the centerline of the N-type doped region perpendicular to the substrate surface; including When there are multiple first P-type doped regions, the multiple first P-type doped regions are symmetrically arranged on both sides of the center line of the N-type doped region perpendicular to the surface of the substrate.
进一步地,在本申请上述的光电二极管中,第二P型掺杂区的厚度为N型掺杂区厚度的1/10~1/20。Further, in the photodiode mentioned above in the present application, the thickness of the second P-type doped region is 1/10-1/20 of the thickness of the N-type doped region.
根据本申请的另一方面,提供了一种光电二极管的制作方法,该制作方法包括:对衬底的上表面进行掺杂形成N型掺杂预备区;对N型掺杂预备区的内部进行掺杂,形成第一P型掺杂区;对衬底的上表面进行二次掺杂,以在第一P型掺杂区的上方形成第二P型掺杂区,并形成与第二P型掺杂区下表面相连的N型掺杂区。According to another aspect of the present application, a method for manufacturing a photodiode is provided. The method includes: doping the upper surface of the substrate to form an N-type doping preparation area; Doping to form a first P-type doped region; doping the upper surface of the substrate twice to form a second P-type doped region above the first P-type doped region, and to form a second P-type doped region The N-type doped region connected to the lower surface of the N-type doped region.
进一步地,在本申请上述的光电二极管的制作方法中,形成N型掺杂预备区的步骤中,掺杂离子的浓度为1.0E+17~1.0E+21atoms/cm3,掺杂离子的注入能量为100~400Kev。Further, in the above-mentioned photodiode manufacturing method of the present application, in the step of forming the N-type doping preparatory region, the concentration of dopant ions is 1.0E+17~1.0E+21atoms/cm 3 , and the implantation of dopant ions The energy is 100-400Kev.
进一步地,在本申请上述的光电二极管的制作方法中,形成第一P型掺杂区的步骤中,对N型掺杂预备区的内部进行掺杂,形成与N型掺杂区的体积之比<0.2的第一P型掺杂区。Further, in the above-mentioned photodiode manufacturing method of the present application, in the step of forming the first P-type doped region, the inside of the N-type doped preparatory region is doped to form a The first P-type doped region with ratio<0.2.
进一步地,在本申请上述的光电二极管的制作方法中,形成第一P型掺杂区的步骤中,掺杂离子的浓度为1.05E+17~1.2E+21atoms/cm3,掺杂离子的注入能量为300~600Kev。Further, in the above-mentioned photodiode manufacturing method of the present application, in the step of forming the first P-type doped region, the concentration of doped ions is 1.05E+17~1.2E+21atoms/cm 3 , and the concentration of doped ions The injection energy is 300-600Kev.
进一步地,在本申请上述的光电二极管的制作方法中,形成第二P型掺杂区和N型掺杂区的步骤中,对衬底的上表面进行二次掺杂,形成厚度为N型掺杂区的厚度1/10~1/20的第二P型掺杂区。Further, in the above-mentioned photodiode manufacturing method of the present application, in the step of forming the second P-type doped region and N-type doped region, the upper surface of the substrate is doped twice to form a thickness of N-type The thickness of the doped region is 1/10-1/20 of the second P-type doped region.
本申请还提供了一种图像传感器件,包括设置于衬底上的光电二极管,其中光电二极管为本申请所提供的光电二极管。The present application also provides an image sensing device, including a photodiode disposed on a substrate, wherein the photodiode is the photodiode provided in the present application.
应用本申请的技术方案一种光电二极管、其制作方法及图像传感器件,在光电二极管的N型掺杂区形成第一P型掺杂区。该第一P型掺杂区会在N型掺杂区中形成PN结耗尽层,进而提高光电二极管的光电转换效率。Applying the technical solution of the present application to a photodiode, its manufacturing method and image sensing device, a first P-type doped region is formed in the N-type doped region of the photodiode. The first P-type doping region will form a PN junction depletion layer in the N-type doping region, thereby improving the photoelectric conversion efficiency of the photodiode.
附图说明Description of drawings
构成本申请的一部分的说明书附图用来提供对本申请的进一步理解,本申请的示意性实施例及其说明用于解释本申请,并不构成对本申请的不当限定。在附图中:The accompanying drawings constituting a part of the present application are used to provide further understanding of the present application, and the schematic embodiments and descriptions of the present application are used to explain the present application, and do not constitute improper limitations to the present application. In the attached picture:
图1示出了现有图像传感器件的剖面结构示意图;FIG. 1 shows a schematic cross-sectional structure diagram of an existing image sensor device;
图2示出了根据本申请所提供的光电二极管的剖面结构示意图;Fig. 2 shows a schematic cross-sectional structure diagram of a photodiode provided according to the present application;
图3示出了根据本申请所提供的光电二极管的制作方法流程示意图;Fig. 3 shows a schematic flow chart of the fabrication method of the photodiode provided according to the present application;
图4示出了本申请实施方式所提供的光电二极管的制作方法中,对衬底的上表面进行掺杂形成N型掺杂预备区后的基体剖面结构示意图;FIG. 4 shows a schematic cross-sectional structure diagram of the substrate after doping the upper surface of the substrate to form an N-type doping preparation region in the method for manufacturing a photodiode provided by an embodiment of the present application;
图5示出了对图4所示N型掺杂预备区的内部进行掺杂,形成第一P型掺杂区后的基体剖面结构示意图;FIG. 5 shows a schematic diagram of the cross-sectional structure of the substrate after doping the inside of the N-type doped preparation region shown in FIG. 4 to form the first P-type doped region;
图6示出了对图5所示衬底的上表面进行二次掺杂,以在第一P型掺杂区的上方形成第二P型掺杂区,并形成与第二P型掺杂区下表面相连的N型掺杂区后的基体剖面结构示意图;以及FIG. 6 shows that the upper surface of the substrate shown in FIG. 5 is doped twice to form a second P-type doped region above the first P-type doped region, and to form a second P-type doped region. Schematic diagram of the cross-sectional structure of the substrate behind the N-type doped region connected to the lower surface of the region; and
图7示出了根据本申请实施例所提供的图像传感器件的剖面结构示意图。FIG. 7 shows a schematic cross-sectional structure diagram of an image sensing device provided according to an embodiment of the present application.
具体实施方式detailed description
需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.
需要注意的是,这里所使用的术语仅是为了描述具体实施方式,而非意图限制根据本申请的示例性实施方式。如在这里所使用的,除非上下文另外明确指出,否则单数形式也意图包括复数形式,此外,还应当理解的是,当在本说明书中使用属于“包含”和/或“包括”时,其指明存在特征、步骤、操作、器件、组件和/或它们的组合。It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprising" and/or "comprising" are used in this specification, it indicates There are features, steps, operations, means, components and/or combinations thereof.
为了便于描述,在这里可以使用空间相对术语,如“在……之上”、“在……上方”、“在……上表面”、“上面的”等,用来描述如在图中所示的一个器件或特征与其他器件或特征的空间位置关系。应当理解的是,空间相对术语旨在包含除了器件在图中所描述的方位之外的在使用或操作中的不同方位。例如,如果附图中的器件被倒置,则描述为“在其他器件或构造上方”或“在其他器件或构造之上”的器件之后将被定位为“在其他器件或构造下方”或“在其他器件或构造之下”。因而,示例性术语“在……上方”可以包括“在……上方”和“在……下方”两种方位。该器件也可以其他不同方式定位(旋转90度或处于其他方位),并且对这里所使用的空间相对描述作出相应解释。For the convenience of description, spatially relative terms may be used here, such as "on ...", "over ...", "on the surface of ...", "above", etc., to describe the The spatial positional relationship between one device or feature shown and other devices or features. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, devices described as "above" or "above" other devices or configurations would then be oriented "beneath" or "above" the other devices or configurations. under other devices or configurations”. Thus, the exemplary term "above" can encompass both an orientation of "above" and "beneath". The device may be oriented differently (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.
正如背景技术中所介绍的,现有技术中存在光电二极管的光电转换效率较低的问题。本申请的申请人针对上述问题进行研究,提出了一种光电二极管。如图2所示,该光电二极管20包括:N型掺杂区21,形成在衬底10的内部;第一P型掺杂区22,形成在N型掺杂区21的内部;第二P型掺杂区23,形成在衬底10中,位于N型掺杂区21上方,且下表面(部分)与N型掺杂区21的上表面相连。As introduced in the background art, there is a problem of low photoelectric conversion efficiency of photodiodes in the prior art. The applicant of the present application conducted research on the above problems and proposed a photodiode. As shown in FIG. 2, the photodiode 20 includes: an N-type doped region 21 formed inside the substrate 10; a first P-type doped region 22 formed inside the N-type doped region 21; a second P-type doped region 21 formed inside the substrate 10; The N-type doped region 23 is formed in the substrate 10 , located above the N-type doped region 21 , and the lower surface (part) is connected to the upper surface of the N-type doped region 21 .
在上述的光电二极管中,在光电二极管的N型掺杂区21的内部形成第一P型掺杂区22。该第一P型掺杂区22会在N型掺杂区21中形成PN结耗尽层,即在N型掺杂区21中形成光电复合中心,从而增加N型掺杂区21中的光生载流子的数量,进而提高光电二极管的光吸收能力,最终提高光电二极管的光电转换效率。In the above photodiode, the first P-type doped region 22 is formed inside the N-type doped region 21 of the photodiode. The first P-type doped region 22 will form a PN junction depletion layer in the N-type doped region 21, that is, form a photoelectric recombination center in the N-type doped region 21, thereby increasing the light generation in the N-type doped region 21. The number of carriers increases, thereby improving the light absorption ability of the photodiode, and finally improving the photoelectric conversion efficiency of the photodiode.
在上述的光电二极管中,第一P型掺杂区22的体积越小,光电二极管的光吸收能力越强,进而使得光电二极管的光电转换效率越高。在本申请的一种优选实施方式中,第一P型掺杂区22的体积与N型掺杂区21的体积之比<0.2。将第一P型掺杂区22的体积设置在上述范围内,可以在不影响光电二极管的势阱容量的同时,提高光电二极管的性能。In the above photodiode, the smaller the volume of the first P-type doped region 22 is, the stronger the light absorption capability of the photodiode is, and thus the higher the photoelectric conversion efficiency of the photodiode is. In a preferred embodiment of the present application, the ratio of the volume of the first P-type doped region 22 to the volume of the N-type doped region 21 is <0.2. Setting the volume of the first P-type doped region 22 within the above range can improve the performance of the photodiode without affecting the potential well capacity of the photodiode.
在上述的光电二极管中,第一P型掺杂区22中P型离子的掺杂量需要大于N型掺杂区21中掺杂离子的掺杂量,以在N型掺杂区21中形成P型掺杂区。在本申请的一种优选实施方式中,第一P型掺杂区22中P型离子的掺杂量与N型掺杂区中N型离子的掺杂量之比为1.05~1.2。将两者的掺杂量之比设置在上述范围内,能够在不影响N型掺杂区21效果的情况下,提高位于N型掺杂区21中的第一P型掺杂区22的光吸收能力,进而提高光电二极管的光电转换效率。In the above-mentioned photodiode, the doping amount of P-type ions in the first P-type doped region 22 needs to be greater than the doping amount of dopant ions in the N-type doped region 21, so as to form in the N-type doped region 21 P-type doped region. In a preferred embodiment of the present application, the ratio of the doping amount of P-type ions in the first P-type doping region 22 to the doping amount of N-type ions in the N-type doping region is 1.05˜1.2. Setting the ratio of the doping amounts of the two within the above-mentioned range can improve the light intensity of the first P-type doped region 22 located in the N-type doped region 21 without affecting the effect of the N-type doped region 21. absorption capacity, thereby improving the photoelectric conversion efficiency of the photodiode.
在上述的光电二极管中,可以根据N型掺杂区21的大小和位置设置第一P型掺杂区22的个数和位置,以在不影响N型掺杂区21效果的情况下,提高光电二极管20的光电转换效率。在一种优选实施方式中,光电二极管20中仅包括一个第一P型掺杂区22时,第一P型掺杂区22位于垂直于衬底10表面的N型掺杂区21的中心线上;光电二极管20中包括多个第一P型掺杂区22时,多个第一P型掺杂区22对称地设置在垂直于衬底10表面的N型掺杂区21的中心线的两侧。处于上述位置的第一P型掺杂区22能够使得光电复合中心均匀地分布在N型掺杂区21中,进而提高N型掺杂区21中光生载流子的均匀性,并进一步提高光电二极管的光电转换效率。In the above-mentioned photodiode, the number and position of the first P-type doped region 22 can be set according to the size and position of the N-type doped region 21, so as to improve the effect of the N-type doped region 21 without affecting the effect. The photoelectric conversion efficiency of the photodiode 20. In a preferred embodiment, when only one first P-type doped region 22 is included in the photodiode 20, the first P-type doped region 22 is located on the centerline of the N-type doped region 21 perpendicular to the surface of the substrate 10 When the photodiode 20 includes a plurality of first P-type doped regions 22, the plurality of first P-type doped regions 22 are symmetrically arranged on the center line of the N-type doped region 21 perpendicular to the surface of the substrate 10 sides. The first P-type doped region 22 in the above-mentioned position can make the photoelectric recombination center evenly distributed in the N-type doped region 21, thereby improving the uniformity of photogenerated carriers in the N-type doped region 21, and further improving the photoelectricity. Photoelectric conversion efficiency of the diode.
在上述的光电二极管中,第二P型掺杂区23为光电二极管的光吸收面,本领域技术人员可以根据CMOS图像传感器的尺寸合理的设置第二P型掺杂区23的厚度。在本申请的一种优选实施方式中,第二P型掺杂区23的厚度为N型掺杂区的厚度的1/10~1/20。如果第二P型掺杂区23的厚度太小,光电二极管的光电转换效率增加可能不太明显;如果第二P型掺杂区23的厚度太大,会减小光电二极管的势阱的容量,进而可能影响光电转化效率。在本申请中优选第二P型掺杂区23的厚度为N型掺杂区的厚度的1/10~1/20,在该范围内有利于提高光电二极管的光电转化效率。In the above photodiode, the second P-type doped region 23 is the light absorption surface of the photodiode, and those skilled in the art can reasonably set the thickness of the second P-type doped region 23 according to the size of the CMOS image sensor. In a preferred embodiment of the present application, the thickness of the second P-type doped region 23 is 1/10˜1/20 of the thickness of the N-type doped region. If the thickness of the second P-type doped region 23 is too small, the photoelectric conversion efficiency increase of the photodiode may not be obvious; if the thickness of the second P-type doped region 23 is too large, the capacity of the potential well of the photodiode will be reduced , which may affect the photoelectric conversion efficiency. In this application, it is preferred that the thickness of the second P-type doped region 23 is 1/10-1/20 of the thickness of the N-type doped region, which is beneficial to improve the photoelectric conversion efficiency of the photodiode.
本申请还提供了一种光电二极管的制作方法。如图3所示,该制作方法包括:对衬底的上表面进行掺杂形成N型掺杂预备区;在N型掺杂预备区的内部进行掺杂,形成第一P型掺杂区;对衬底的上表面进行二次掺杂,以在第一P型掺杂区的上方形成第二P型掺杂区,并形成与第二P型掺杂区的下表面相连的N型掺杂区。The application also provides a method for manufacturing the photodiode. As shown in FIG. 3, the manufacturing method includes: doping the upper surface of the substrate to form an N-type doped preparatory region; performing doping inside the N-type doped preparatory region to form a first P-type doped region; The upper surface of the substrate is doped twice to form a second P-type doped region above the first P-type doped region, and an N-type doped region connected to the lower surface of the second P-type doped region is formed. Miscellaneous area.
下面将更详细地描述根据本申请的示例性实施方式。然而,这些示例性实施方式可以由多种不同的形式来实施,并且不应当被解释为只限于这里所阐述的实施方式。应当理解的是,提供这些实施方式是为了使得本申请的公开彻底且完整,并且将这些示例性实施方式的构思充分传达给本领域普通技术人员,在附图中,为了清楚起见,扩大了区和区域的厚度,并且使用相同的附图标记表示相同的器件,因而将省略对它们的描述。Exemplary embodiments according to the present application will be described in more detail below. These example embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of these exemplary embodiments to those of ordinary skill in the art. and the thickness of the region, and the same reference numerals are used to designate the same devices, and thus their descriptions will be omitted.
图4至图6示出了本申请提供的光电二极管的制作方法中,经过各个步骤后得到的基体的剖面结构示意图。下面将结合图4至图6,进一步说明本申请所提供的光电二极管的制作方法。FIG. 4 to FIG. 6 show schematic cross-sectional structure diagrams of the substrate obtained after various steps in the method for manufacturing the photodiode provided in the present application. The fabrication method of the photodiode provided by the present application will be further described below with reference to FIG. 4 to FIG. 6 .
首先,对衬底10的上表面进行掺杂形成N型掺杂预备区21′,进而形成如图4所示的基体结构。上述掺杂步骤中,掺杂离子的能量及掺杂浓度可以按照现有技术进行选择。优选地,掺杂离子的浓度为1.0E+17~1.0E+21atoms/cm3,掺杂离子注入的能量为100~400Kev。上述掺杂的离子可以为磷离子,掺杂工艺可以包括但不限于采用离子注入。需要注意的是,上述衬底10可以为单晶硅、绝缘体上硅(SOI)或锗硅(SiGe)等,且衬底10为P型衬底,或在衬底10中形成有P阱。Firstly, the upper surface of the substrate 10 is doped to form an N-type doped preparation region 21 ′, and then the base structure as shown in FIG. 4 is formed. In the above doping step, the energy and doping concentration of the doping ions can be selected according to the prior art. Preferably, the concentration of dopant ions is 1.0E+17˜1.0E+21 atoms/cm 3 , and the energy of dopant ion implantation is 100˜400 KeV. The above-mentioned doped ions may be phosphorous ions, and the doping process may include but not limited to ion implantation. It should be noted that the above substrate 10 may be single crystal silicon, silicon on insulator (SOI) or silicon germanium (SiGe), etc., and the substrate 10 is a P-type substrate, or a P well is formed in the substrate 10 .
在上述形成N型掺杂预备区21′的步骤中,对上述衬底10的上表面进行掺杂时会在衬底10中引入缺陷。因此,在上述掺杂步骤之后,还可以对衬底10进行退火以去除衬底10中的缺陷。在本申请的一种可选实施方式中,上述退火的工艺条件为:退火温度为900~1200℃,退火时间为30~60秒。采用上述工艺条件进行退火既能去除衬底10中的缺陷,还不会在衬底10中引入新的缺陷(比如应力引起的晶格畸变等)。In the step of forming the N-type doping preparation region 21 ′, defects will be introduced into the substrate 10 when doping the upper surface of the substrate 10 . Therefore, after the above-mentioned doping step, the substrate 10 may also be annealed to remove defects in the substrate 10 . In an optional implementation manner of the present application, the above annealing process conditions are as follows: the annealing temperature is 900-1200° C., and the annealing time is 30-60 seconds. Annealing under the above process conditions can remove defects in the substrate 10 and will not introduce new defects (such as lattice distortion caused by stress, etc.) into the substrate 10 .
完成对衬底10的上表面进行掺杂形成N型掺杂预备区21′的步骤之后,对N型掺杂预备区21′的内部进行掺杂,形成第一P型掺杂区22,进而形成如图5所示的基体结构。上述掺杂步骤中,采用具有较高能量(远高于形成N型掺杂预备区21′步骤中掺杂离子的能量)的掺杂离子对N型掺杂预备区21′进行掺杂,以在N型掺杂预备区21′的内部掺杂形成第一P型掺杂区22;优选地,第一P型掺杂区22的掺杂离子浓度高于成N型掺杂预备区21′步骤中掺杂离子的浓度,以形成P型掺杂区。优选地,该步骤中掺杂离子的浓度为1.05E+17~1.2E+21atoms/cm3,掺杂离子的注入能量为300~600Kev。上述掺杂的离子可以为硼离子,掺杂工艺可以包括但不限于采用离子注入。After completing the step of doping the upper surface of the substrate 10 to form an N-type doped preparatory region 21', doping the inside of the N-type doped preparatory region 21' to form a first P-type doped region 22, and then Form the base structure as shown in Figure 5. In the above doping step, the N-type doping preparation region 21' is doped with doping ions having higher energy (much higher than the energy of the doping ions in the step of forming the N-type doping preparation region 21'), so as to The first P-type doped region 22 is formed by doping inside the N-type doped preparation region 21'; preferably, the doping ion concentration of the first P-type doped region 22 is higher than that of the N-type doped preparation region 21' The concentration of doping ions in the step is to form a P-type doping region. Preferably, the concentration of dopant ions in this step is 1.05E+17˜1.2E+21 atoms/cm 3 , and the implantation energy of dopant ions is 300˜600 KeV. The above-mentioned doped ions may be boron ions, and the doping process may include but not limited to ion implantation.
在上述形成第一P型掺杂区22的步骤中,对上述N型掺杂预备区21′进行掺杂时会在N型掺杂预备区21′中引入缺陷。因此,在上述对N型掺杂预备区21′进行掺杂之后,还可以以对衬底10进行退火以去除衬底10中的缺陷。在本申请的一种可选实施方式中,上述退火的工艺条件为:退火温度为900~1200℃,退火时间为30~60秒。采用上述工艺条件进行退火既能去除N型掺杂预备区21′中的缺陷,还不会在N型掺杂预备区21′中引入新的缺陷(比如应力引起的晶格畸变等)。In the above step of forming the first P-type doped region 22 , when doping the above-mentioned N-type doped preparatory region 21 ′, defects will be introduced into the N-type doped preparatory region 21 ′. Therefore, after the above-mentioned doping of the N-type doping preparation region 21 ′, the substrate 10 may also be annealed to remove defects in the substrate 10 . In an optional implementation manner of the present application, the above annealing process conditions are as follows: the annealing temperature is 900-1200° C., and the annealing time is 30-60 seconds. Annealing under the above process conditions can remove defects in the N-type doped preparatory region 21 ′, and will not introduce new defects (such as lattice distortion caused by stress, etc.) into the N-type doped preparatory region 21 ′.
在上述形成第一P型掺杂区22的步骤中,所形成第一P型掺杂区22的体积越小,光电二极管的光吸收能力越强,进而使得光电二极管的光电转换效率越高。在本申请的一种优选实施方式中,对N型掺杂预备区21′的内部进行掺杂形成的第一P型掺杂区22的体积与N型掺杂区的体积之比<0.2。如果第一P型掺杂区22的体积大于上述体积,会影响光电二极管的势阱容量,进而降低光电二极管的性能。In the above step of forming the first P-type doped region 22 , the smaller the volume of the formed first P-type doped region 22 , the stronger the light absorption capability of the photodiode, and thus the higher the photoelectric conversion efficiency of the photodiode. In a preferred embodiment of the present application, the ratio of the volume of the first P-type doped region 22 formed by doping the inside of the N-type doped preparation region 21 ′ to the volume of the N-type doped region is <0.2. If the volume of the first P-type doped region 22 is larger than the above-mentioned volume, the potential well capacity of the photodiode will be affected, thereby reducing the performance of the photodiode.
完成对N型掺杂预备区21′的内部进行掺杂,形成第一P型掺杂区22的步骤之后,对衬底10的上表面进行二次掺杂,以在第一P型掺杂区22的上方形成第二P型掺杂区23,并形成与第二P型掺杂区23下表面相连的N型掺杂区21,进而形成如图6所示的基体结构。在二次掺杂的步骤中掺杂元素部分进入N型掺杂预备区21′,部分进入N型掺杂预备区21′周围的衬底中。经过二次掺杂的步骤将部分N型掺杂预备区21′变为第二P型掺杂区23,剩余的部分形成N型掺杂区21。优选地,该步骤中掺杂离子的浓度为1.05E+17~1.2E+21atoms/cm3,掺杂离子的能量为300~600Kev。上述掺杂的离子可以为硼离子,掺杂工艺可以包括但不限于采用离子注入。After completing the step of doping the inside of the N-type doping preparatory region 21' to form the first P-type doping region 22, the upper surface of the substrate 10 is doped twice to form the first P-type doping region 22. A second P-type doped region 23 is formed above the region 22, and an N-type doped region 21 connected to the lower surface of the second P-type doped region 23 is formed, thereby forming a base structure as shown in FIG. 6 . In the second doping step, the dopant elements partly enter the N-type doping preparatory region 21 ′, and partly enter the substrate around the N-type doping preparatory region 21 ′. After the second doping step, part of the N-type doped preparatory region 21 ′ becomes the second P-type doped region 23 , and the remaining part forms the N-type doped region 21 . Preferably, the concentration of the dopant ions in this step is 1.05E+17˜1.2E+21 atoms/cm 3 , and the energy of the dopant ions is 300˜600 KeV. The above-mentioned doped ions may be boron ions, and the doping process may include but not limited to ion implantation.
在上述形成第二P型掺杂区23和N型掺杂区的步骤中,对衬底10的上表面进行二次掺杂时可能会在衬底10中引入缺陷。因此,在上述对衬底10的上表面进行掺杂形成第二P型掺杂区23和N型掺杂区之后,还可以对衬底10进行退火以去除衬底10中的缺陷。在本申请的一种可选实施方式中,上述退火的工艺条件为:退火温度为900~1200℃,退火时间为30~60秒。采用上述工艺条件进行退火既能去除衬底10中的缺陷,还不会在衬底10中引入新的缺陷(比如应力引起的晶格畸变等)。In the above step of forming the second P-type doped region 23 and the N-type doped region, defects may be introduced into the substrate 10 when the upper surface of the substrate 10 is doped twice. Therefore, after the above-mentioned doping of the upper surface of the substrate 10 to form the second P-type doped region 23 and the N-type doped region, the substrate 10 may also be annealed to remove defects in the substrate 10 . In an optional implementation manner of the present application, the above annealing process conditions are as follows: the annealing temperature is 900-1200° C., and the annealing time is 30-60 seconds. Annealing under the above process conditions can remove defects in the substrate 10 and will not introduce new defects (such as lattice distortion caused by stress, etc.) into the substrate 10 .
形成第二P型掺杂区23和N型掺杂区的步骤中,掺杂形成的第二P型掺杂区23的厚度会影响光电二极管的光电转换效率。在本申请的一种优选实施方式中,对衬底10的上表面进行掺杂,使得形成第二P型掺杂区23的厚度与N型掺杂区的厚度比为1/10~1/20。如果第二P型掺杂区23的厚度小于上述范围的最小值,光电二极管的光电转换效率增加可能不明显;如果第二P型掺杂区23的厚度大于上述范围的最大值,光电二极管的势阱容量将会明显受影响,进而可能影响光电转化效率。In the step of forming the second P-type doped region 23 and the N-type doped region, the thickness of the second P-type doped region 23 formed by doping will affect the photoelectric conversion efficiency of the photodiode. In a preferred embodiment of the present application, the upper surface of the substrate 10 is doped so that the ratio of the thickness of the second P-type doped region 23 to the thickness of the N-type doped region is 1/10˜1/10. 20. If the thickness of the second P-type doped region 23 is less than the minimum value of the above range, the photoelectric conversion efficiency of the photodiode may not increase significantly; if the thickness of the second P-type doped region 23 is greater than the maximum value of the above range, the photodiode The potential well capacity will be significantly affected, which may affect the photoelectric conversion efficiency.
本申请还提供了一种图像传感器件。该图像传感器包括:设置于衬底10上的光电二极管,其中光电二极管为本申请所提供的光电二极管。其中,图像传感器的基本单元为像素,由1个光电二极管和3个或4个MOS晶体管构成,简称为3T类型或4T类型。本领域的技术人员可以根据图像传感器实际应用的领域,选择采用3T类型或4T类型。The present application also provides an image sensing device. The image sensor includes: a photodiode disposed on a substrate 10, wherein the photodiode is a photodiode provided in this application. Among them, the basic unit of an image sensor is a pixel, which is composed of a photodiode and 3 or 4 MOS transistors, referred to as 3T type or 4T type for short. Those skilled in the art can choose to use the 3T type or the 4T type according to the actual application field of the image sensor.
在本申请的一种优选实施方式中,上述图像传感器的基本单元由1个光电二极管和4个MOS晶体管构成,如图7所示。该CMOS图形传感器包括:衬底10和依次形成在该衬底10上的光电二极管20、转移晶体管30和势阱40,其中光电二极管20包括形成在衬底10内部的N型掺杂区,形成在N型掺杂区内部的第一P型掺杂区,以及形成在衬底10中,位于N型掺杂区上方的第二P型掺杂区,该第二P型掺杂区的上表面可以裸露在衬底10的外侧,也可以处于N型掺杂区内部,下表面与N型掺杂区的上表面相连,;在势阱40上形成有源跟随器晶体管50、复位晶体管60、选择晶体管70和浅沟槽隔离结构80。转移晶体管30位于光电二极管20和势阱40之间,且转移晶体管30的源区与光电二极管20相连接,转移晶体管30的漏区与源跟随器晶体管50相连接。上述图像传感器中,MOS晶体管的组成为现有技术,在此不再赘述。具有上述结构的图像传感器的光电转换效率得到提高,进而提高了图像传感器的光电性能。In a preferred implementation manner of the present application, the basic unit of the image sensor is composed of one photodiode and four MOS transistors, as shown in FIG. 7 . The CMOS image sensor includes: a substrate 10 and a photodiode 20, a transfer transistor 30, and a potential well 40 sequentially formed on the substrate 10, wherein the photodiode 20 includes an N-type doped region formed inside the substrate 10, forming The first P-type doped region inside the N-type doped region, and the second P-type doped region formed in the substrate 10 above the N-type doped region, the upper part of the second P-type doped region The surface can be exposed on the outside of the substrate 10, or it can be inside the N-type doped region, and the lower surface is connected to the upper surface of the N-type doped region; an active follower transistor 50 and a reset transistor 60 are formed on the potential well 40 , select the transistor 70 and the shallow trench isolation structure 80 . The transfer transistor 30 is located between the photodiode 20 and the potential well 40 , and the source region of the transfer transistor 30 is connected to the photodiode 20 , and the drain region of the transfer transistor 30 is connected to the source follower transistor 50 . In the above image sensor, the composition of the MOS transistor is a prior art, and will not be repeated here. The photoelectric conversion efficiency of the image sensor with the above structure is improved, thereby improving the photoelectric performance of the image sensor.
下面将结合实施例进一步说明本申请提供的光电二极管的制作方法。The fabrication method of the photodiode provided by the present application will be further described below with reference to the embodiments.
实施例1Example 1
本实施例提供了一种光电二极管的制作方法,包括以下步骤:This embodiment provides a method for fabricating a photodiode, comprising the following steps:
对Si衬底的上表面进行磷离子掺杂形成N型掺杂预备区,其中磷离子的掺杂浓度为1.0E+17atoms/cm3,磷离子的注入能量为100Kev,所形成N型掺杂预备区的厚度为220nm;Phosphorus ion doping is performed on the upper surface of the Si substrate to form an N-type doped preparatory region. The doping concentration of phosphorus ions is 1.0E+17atoms/cm 3 , and the implantation energy of phosphorus ions is 100Kev. The thickness of the preparation area is 220nm;
在上述N型掺杂预备区的内部掺杂硼离子形成第一P型掺杂区,其中硼离子的掺杂浓度为1.05E+17atoms/cm3,掺杂离子的注入能量为300Kev,所形成的第一P型掺杂区的体积为2.4E+3nm3;Boron ions are doped inside the above-mentioned N-type doping preparation region to form the first P-type doping region, wherein the doping concentration of boron ions is 1.05E+17atoms/cm 3 , and the implantation energy of doping ions is 300Kev. The volume of the first P-type doped region is 2.4E+3nm 3 ;
对Si衬底的上表面进行硼离子掺杂,以上述第一P型掺杂区的上方形成第二P型掺杂区,并形成与第二P型掺杂区的下表面相连的N型掺杂区,其中硼离子的掺杂浓度为1.05E+17atoms/cm3,掺杂离子的能量为100Kev,所形成第二P型掺杂区的厚度为20nm,N型掺杂区的厚度为200nm,N型掺杂区的体积为8.6E+6nm3,第一P型掺杂区的体积与N型掺杂区的体积之比为2.8×10-4。Doping the upper surface of the Si substrate with boron ions to form a second P-type doped region above the first P-type doped region, and form an N-type doped region connected to the lower surface of the second P-type doped region. The doped region, wherein the doping concentration of boron ions is 1.05E+17atoms/cm 3 , the energy of the doped ions is 100Kev, the thickness of the second P-type doped region formed is 20nm, and the thickness of the N-type doped region is 200 nm, the volume of the N-type doped region is 8.6E+6nm 3 , and the ratio of the volume of the first P-type doped region to the volume of the N-type doped region is 2.8×10 -4 .
实施例2Example 2
本实施例提供了一种光电二极管的制作方法,包括以下步骤:This embodiment provides a method for fabricating a photodiode, comprising the following steps:
对Si衬底的上表面进行磷离子掺杂形成N型掺杂预备区,其中磷离子的掺杂浓度为1.0E+21atoms/cm3,磷离子的注入能量为400Kev,所形成N型掺杂预备区的厚度为420nm;Phosphorus ion doping is performed on the upper surface of the Si substrate to form an N-type doped preparatory region. The doping concentration of phosphorus ions is 1.0E+ 21 atoms/cm 3 , and the implantation energy of phosphorus ions is 400Kev. The thickness of the preparation area is 420nm;
对上述N型掺杂预备区的内部进行硼离子掺杂,在垂直于衬底10表面的N型掺杂区21的中心线的两侧形成4个第一P型掺杂区22,其中硼离子的掺杂浓度为1.2E+21atoms/cm3,掺杂离子的注入能量为600Kev,所形成的第一P型掺杂区的总体积为7.2E+4nm3;Boron ion doping is carried out to the inside of the above-mentioned N-type doping preparation area, and four first P-type doping regions 22 are formed on both sides of the centerline of the N-type doping region 21 perpendicular to the surface of the substrate 10, wherein boron The doping concentration of ions is 1.2E+21atoms/cm 3 , the implantation energy of doping ions is 600Kev, and the total volume of the formed first P-type doped region is 7.2E+4nm 3 ;
对Si衬底的上表面进行硼离子掺杂,以在上述第一P型掺杂区的上方形成第二P型掺杂区,并形成与第二P型掺杂区的下表面相连的N型掺杂区,其中硼离子的掺杂浓度为1.2E+21atoms/cm3,掺杂离子的能量为400Kev,所形成的第二P型掺杂区的厚度为20nm,N型掺杂区的厚度为400nm,N型掺杂区的体积为9.2E+6nm3,第一P型掺杂区的体积与N型掺杂区的体积之比为7.8×10-3。Doping the upper surface of the Si substrate with boron ions to form a second P-type doped region above the first P-type doped region, and form a N type doped region, wherein the doping concentration of boron ions is 1.2E+21atoms/cm 3 , the energy of the doped ions is 400Kev, the thickness of the second P-type doped region formed is 20nm, and the thickness of the N-type doped region The thickness is 400nm, the volume of the N-type doped region is 9.2E+6nm 3 , and the ratio of the volume of the first P-type doped region to the volume of the N-type doped region is 7.8×10 -3 .
实施例3Example 3
本实施例提供了一种光电二极管的制作方法,包括以下步骤:This embodiment provides a method for fabricating a photodiode, comprising the following steps:
对Si衬底的上表面进行磷离子掺杂形成N型掺杂预备区,其中磷离子的掺杂浓度为1.1E+21atoms/cm3,磷离子的注入能量为500Kev,所形成的N型掺杂预备区的厚度为500nm;Phosphorus ion doping is performed on the upper surface of the Si substrate to form an N-type doped preparatory region. The doping concentration of phosphorus ions is 1.1E+ 21 atoms/cm 3 , and the implantation energy of phosphorus ions is 500Kev. The thickness of the impurity preparation area is 500nm;
在上述N型掺杂预备区的内部掺杂硼离子形成第一P型掺杂区,其中硼离子的掺杂浓度为1.6E+21atoms/cm3,掺杂离子的注入能量为700Kev,所形成的第一P型掺杂区的体积为3.1E+5nm3;Boron ions are doped inside the above-mentioned N-type doping preparation region to form the first P-type doping region, wherein the doping concentration of boron ions is 1.6E+21atoms/cm 3 , and the implantation energy of doping ions is 700Kev. The volume of the first P-type doped region is 3.1E+5nm 3 ;
对Si衬底的上表面进行硼离子掺杂,以在上述第一P型掺杂区的上方形成第二P型掺杂区,并形成与第二P型掺杂区下表面相连的N型掺杂区,其中硼离子的掺杂浓度为1.4E+21atoms/cm3,掺杂离子的能量为600Kev,所形成的第二P型掺杂区的厚度为20nm,N型掺杂区的厚度为480nm,N型掺杂区的体积为1.1E+6nm3,第一P型掺杂区的体积与N型掺杂区的体积之比为0.28。Doping the upper surface of the Si substrate with boron ions to form a second P-type doped region above the first P-type doped region, and form an N-type doped region connected to the lower surface of the second P-type doped region. The doping region, wherein the doping concentration of boron ions is 1.4E+21atoms/cm 3 , the energy of the doping ions is 600Kev, the thickness of the second P-type doping region formed is 20nm, and the thickness of the N-type doping region is The volume of the N-type doped region is 1.1E+6nm 3 , and the ratio of the volume of the first P-type doped region to the volume of the N-type doped region is 0.28.
对比例1Comparative example 1
本实施例提供了一种光电二极管的制作方法,包括以下步骤:This embodiment provides a method for fabricating a photodiode, comprising the following steps:
对Si衬底的上表面进行磷离子掺杂形成N型掺杂预备区,其中磷离子的掺杂浓度为1.0E+17atoms/cm3,磷离子的注入能量为100Kev,所形成的N型掺杂预备区的厚度为220nm。Phosphorus ion doping is performed on the upper surface of the Si substrate to form an N-type doped preparatory region. The doping concentration of phosphorus ions is 1.0E+17atoms/cm 3 , and the implantation energy of phosphorus ions is 100Kev. The thickness of the impurity preparation region was 220 nm.
对Si衬底的上表面进行硼离子掺杂,以在部分N型掺杂预备区和与其相连的部分Si衬底中形成P型掺杂区,并将剩余的N型掺杂预备区作为N型掺杂区,其中硼离子的掺杂浓度为1.05E+17atoms/cm3,掺杂离子的能量为100Kev,所形成P型掺杂区的厚度为20nm,N型掺杂区的厚度为200nm。The upper surface of the Si substrate is doped with boron ions to form a P-type doped region in part of the N-type doped preparation region and part of the Si substrate connected to it, and the remaining N-type doped preparation region is used as N type doped region, wherein the doping concentration of boron ions is 1.05E+17atoms/cm 3 , the energy of the doped ions is 100Kev, the thickness of the formed P-type doped region is 20nm, and the thickness of the N-type doped region is 200nm .
采用伏安特性测试方法对实施例1至3和对比例1得到的光电二极管进行测试,计算得出其光电转换效率,测试结果请见表1。The photodiodes obtained in Examples 1 to 3 and Comparative Example 1 were tested by using the volt-ampere characteristic test method, and their photoelectric conversion efficiencies were calculated. Please refer to Table 1 for the test results.
表1Table 1
从表1中的数据可以看出,实施例1至3得到的光电二极管的光电转换效率为82%~89%,而对比例1得到的光电二极管的光电转换效率仅为72%,明显低于实施例1至3得到的光电二极管的光电转换效率。As can be seen from the data in Table 1, the photoelectric conversion efficiency of the photodiodes obtained in Examples 1 to 3 is 82% to 89%, while the photoelectric conversion efficiency of the photodiodes obtained in Comparative Example 1 is only 72%, which is significantly lower than The photoelectric conversion efficiency of the photodiode that embodiment 1 to 3 obtains.
从以上的描述中,可以看出,本申请上述的实施例实现了如下技术效果:在光电二极管的N型掺杂区形成第一P型掺杂区。该第一P型掺杂区会在N型掺杂区中形成PN结耗尽层,进而提高光电二极管的光电转换效率。From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effect: the first P-type doped region is formed in the N-type doped region of the photodiode. The first P-type doping region will form a PN junction depletion layer in the N-type doping region, thereby improving the photoelectric conversion efficiency of the photodiode.
以上所述仅为本申请的优选实施例而已,并不用于限制本申请,对于本领域的技术人员来说,本申请可以有各种更改和变化。凡在本申请的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本申请的保护范围之内。The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, there may be various modifications and changes in the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included within the protection scope of this application.
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