CN104934449A - Display substrate and manufacturing method thereof, and display apparatus - Google Patents
Display substrate and manufacturing method thereof, and display apparatus Download PDFInfo
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- CN104934449A CN104934449A CN201510420098.0A CN201510420098A CN104934449A CN 104934449 A CN104934449 A CN 104934449A CN 201510420098 A CN201510420098 A CN 201510420098A CN 104934449 A CN104934449 A CN 104934449A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 title abstract 3
- 239000010409 thin film Substances 0.000 claims abstract description 28
- 238000002161 passivation Methods 0.000 claims description 50
- 229910044991 metal oxide Inorganic materials 0.000 claims description 38
- 150000004706 metal oxides Chemical class 0.000 claims description 38
- 239000011347 resin Substances 0.000 claims description 38
- 229920005989 resin Polymers 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 20
- 230000009467 reduction Effects 0.000 claims description 15
- 229910052738 indium Inorganic materials 0.000 claims description 12
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000011946 reduction process Methods 0.000 claims description 12
- 230000000903 blocking effect Effects 0.000 claims description 4
- 238000005286 illumination Methods 0.000 abstract description 6
- 230000001678 irradiating effect Effects 0.000 abstract 2
- 238000006722 reduction reaction Methods 0.000 description 12
- 230000000694 effects Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000009832 plasma treatment Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
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- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
- Liquid Crystal (AREA)
Abstract
The present invention relates to a display substrate and a manufacturing method thereof, and a display apparatus. The display substrate comprises: a thin film transistor which is provided with an active layer therein; and a light shield layer which is arranged over the active layer and is used for shielding lights irradiating towards the active layer. According to the technical scheme of the present invention, the light shield layer is arranged over the active layer, so that external lights can be effectively prevented from irradiating to the active layer in the thin film transistor, thereby avoiding unstable performance of the thin film transistor caused by influence on the active layer from the outside illumination.
Description
Technical field
The present invention relates to Display Technique field, in particular to a kind of display base plate, a kind of display unit and a kind of display base plate manufacture method.
Background technology
IGZO is a kind of oxide containing indium, gallium and zinc, carrier mobility is 20 ~ 30 times of amorphous silicon, active layer for making TFT (i.e. thin-film transistor) greatly can improve the charge-discharge velocity of TFT to pixel electrode, improve the response speed of pixel, realize refresh rate faster, respond the line scanning rate also substantially increasing pixel faster simultaneously, make ultrahigh resolution become possibility in TFT-LCD.In addition, reduce due to number of transistors and improve the light transmittance of each pixel, IGZO display has higher efficiency level, and efficiency is higher.
But when making the active layer in thin-film transistor by IGZO, because IGZO is easily by extraneous illumination effect, as shown in Figure 1, active layer can be made unstable, causing thin-film transistor service behaviour under the environment that there is ambient light unstable.
Summary of the invention
Technical problem to be solved by this invention is, how to avoid the active layer in thin-film transistor to be subject to the impact of ambient light.
For this purpose, the present invention proposes a kind of display base plate, comprising:
Thin-film transistor, is provided with active layer in described thin-film transistor;
Light shield layer, is arranged on described active layer, for blocking the light of active layer described in directive.
Preferably, also comprise:
First passivation layer, is arranged on described active layer;
Resin bed, is arranged on described first passivation layer;
Pixel electrode, is arranged on described resin bed, and material is metal oxide,
Wherein, described light shield layer and described pixel electrode are positioned at same layer, are formed by the metal oxide back in described pixel electrode.
Preferably, also comprise:
First passivation layer, is arranged on described active layer;
Resin bed, is arranged on described first passivation layer;
Public electrode, is arranged on described resin bed, and material is metal oxide,
Wherein, described light shield layer and described public electrode are positioned at same layer, are formed by the metal oxide back in described public electrode.
Preferably, also comprise:
First passivation layer, is arranged on described active layer;
Resin bed, is arranged on described first passivation layer;
Public electrode, is arranged on described resin bed, and material is metal oxide;
Second passivation layer, is arranged on described public electrode;
Pixel electrode, is arranged on described second passivation layer,
Wherein, described light shield layer comprises:
First light shield layer, is positioned at same layer with described public electrode, is formed by the metal oxide back in described public electrode,
Second light shield layer, is positioned at same layer with described pixel electrode, is formed by the metal oxide back in described pixel electrode.
Preferably, described thin-film transistor also comprises:
Source electrode and drain electrode, be arranged on described active layer,
Wherein, the subregion of described active layer is blocked in described source electrode and drain electrode respectively, then the area of described light shield layer is greater than described active layer not by the area of described source electrode with drain electrode occlusion area.
Preferably, described metal oxide is ITO, and the material of described light shield layer is indium metal.
The invention allows for a kind of display unit, comprise the display base plate described in above-mentioned any one.
The invention allows for a kind of display base plate manufacture method, comprising:
Form the active layer in thin-film transistor;
Light shield layer is formed, to block the light of active layer described in directive in active layer.
Preferably, also comprise:
The first passivation layer is formed in described active layer;
Resin bed is formed on described first passivation layer;
The pixel electrode that material is metal oxide is formed on described resin bed,
Then form described light shield layer to comprise:
Reduction treatment is carried out to the first area of described pixel electrode, using as described light shield layer.
Preferably, form described light shield layer to comprise:
On the first area of described pixel electrode, form intermediate tone mask, on other regions of described pixel electrode, form panchromatic tune mask;
Described pixel electrode place layer is etched, to obtain the pattern of described pixel electrode;
Cineration technics is carried out to the pattern of described pixel electrode, with the intermediate tone mask on the first area of removing described pixel electrode;
Plasma reduction process is carried out to the first area of described pixel electrode, using as described light shield layer.
Preferably, also comprise:
The first passivation layer is formed in described active layer;
Resin bed is formed on described first passivation layer;
The public electrode that material is metal oxide is formed on described resin bed,
Then form described light shield layer to comprise:
Reduction treatment is carried out to the second area of described public electrode, using as described light shield layer.
Preferably, form described light shield layer to comprise:
On the second area of described public electrode, form intermediate tone mask, on other regions of described public electrode, form panchromatic tune mask;
Described public electrode place layer is etched, to obtain the pattern of described public electrode;
Cineration technics is carried out to the pattern of described public electrode, with the intermediate tone mask on the second area removing described public electrode;
Plasma reduction process is carried out to the second area of described public electrode, using as described light shield layer.
Preferably, also comprise:
The first passivation layer is formed in described active layer;
Resin bed is formed on described first passivation layer;
The public electrode that material is metal oxide is formed on described resin bed;
The second passivation layer is formed on described public electrode;
The pixel electrode that material is metal oxide is formed on described second passivation layer,
Then form described light shield layer to comprise: form the first light shield layer and the second light shield layer,
Wherein, form described first light shield layer to comprise:
Reduction treatment is carried out to the second area of described public electrode, using as described first light shield layer,
Form described second light shield layer to comprise:
Reduction treatment is carried out to the first area of described pixel electrode, using as described second light shield layer.
Preferably, form described first light shield layer to comprise:
On the second area of described public electrode, form intermediate tone mask, on other regions of described public electrode, form panchromatic tune mask;
Described public electrode place layer is etched, to obtain the pattern of described public electrode;
Cineration technics is carried out to the pattern of described public electrode, with the intermediate tone mask on the second area removing described public electrode;
Plasma reduction process is carried out to the second area of described public electrode, using as described first light shield layer,
Form described second light shield layer to comprise:
On the first area of described pixel electrode, form intermediate tone mask, on other regions of described pixel electrode, form panchromatic tune mask;
Described pixel electrode place layer is etched, to obtain the pattern of described pixel electrode;
Cineration technics is carried out to the pattern of described pixel electrode, with the intermediate tone mask on the first area of removing described pixel electrode;
Plasma reduction process is carried out to the first area of described pixel electrode, using as described second light shield layer.
Preferably, the SiH of 800sccm is greater than by flow
4carry out reduction treatment.
According to technique scheme, by arranging light shield layer in active layer, can effectively avoid extraneous light to be irradiated to active layer in thin-film transistor, thus thin-film transistor performance that extraneous illumination effect causes is unstable to avoid active layer to be subject to.
Accompanying drawing explanation
Can understanding the features and advantages of the present invention clearly by reference to accompanying drawing, accompanying drawing is schematic and should not be construed as and carry out any restriction to the present invention, in the accompanying drawings:
Fig. 1 shows the structural representation of thin-film transistor in prior art;
Fig. 2 shows the structural representation of display base plate according to an embodiment of the invention;
Fig. 3 shows the structural representation of the display base plate according to another embodiment of the present invention;
Fig. 4 shows the structural representation of the display base plate according to another embodiment of the present invention;
Fig. 5 shows the schematic flow diagram forming light shield layer according to an embodiment of the invention;
Fig. 6 shows the schematic flow diagram of the formation light shield layer according to another embodiment of the present invention;
Fig. 7 shows the schematic flow diagram of the formation light shield layer according to another embodiment of the present invention;
Fig. 8 to Figure 12 shows the concrete schematic flow diagram of the formation light shield layer according to another embodiment of the present invention.
Drawing reference numeral illustrates:
1-active layer; 2-light shield layer; 21-first light shield layer; 22-second light shield layer; 3-first passivation layer; 4-resin bed; 5-pixel electrode; 6-public electrode; 7-second passivation layer; 8-source electrode; 9-drains; 11-intermediate tone mask; The panchromatic tune mask of 12-.
Embodiment
In order to more clearly understand above-mentioned purpose of the present invention, feature and advantage, below in conjunction with the drawings and specific embodiments, the present invention is further described in detail.It should be noted that, when not conflicting, the feature in the embodiment of the application and embodiment can combine mutually.
Set forth a lot of detail in the following description so that fully understand the present invention; but; the present invention can also adopt other to be different from other modes described here and implement, and therefore, protection scope of the present invention is not by the restriction of following public specific embodiment.
As shown in Figure 2, display base plate according to an embodiment of the invention, comprising:
Thin-film transistor, is provided with active layer 1 in thin-film transistor, and wherein, the material of active layer 1 can be IGZO;
Light shield layer 2, is arranged on active layer 1, for blocking the light of directive active layer 1.
By arranging light shield layer 2 on active layer 1, can effectively avoid extraneous light to be irradiated to active layer 1 in thin-film transistor, thus thin-film transistor performance that extraneous illumination effect causes is unstable to avoid active layer 1 to be subject to.
Wherein light shield layer 2 can be arranged on to contact on active layer 1, and also can be arranged on active layer 1, concrete structure can be arranged as required contactlessly.
Preferably, also comprise:
First passivation layer 3, is arranged on active layer 1;
Resin bed 4, is arranged on the first passivation layer 3;
Pixel electrode 5, is arranged on resin bed 4, and material is metal oxide,
Wherein, light shield layer 2 and pixel electrode position 5, in same layer, are formed by the metal oxide back in pixel electrode 5.
The material of such as pixel electrode 5 is ITO, so by carrying out reduction reaction to ITO, can obtain indium metal (i.e. In), because indium metal is lighttight, therefore effectively can block the light of directive active layer 1.
Wherein light shield layer 2 directly generates from pixel electrode 5, without the need to forming Rotating fields separately for forming light shield layer 2, simplifies the technique making light shield layer 2.Wherein resin bed 4 can provide planarization conditions for pixel electrode.
As shown in Figure 3, preferably, also comprise:
First passivation layer 3, is arranged on active layer 1;
Resin bed 4, is arranged on the first passivation layer 3;
Public electrode 6, is arranged on resin bed 4, and material is metal oxide,
Wherein, light shield layer and public electrode 6 are positioned at same layer, are formed by the metal oxide back in public electrode 6.
The material of such as public electrode 6 is ITO, so by carrying out reduction reaction to ITO, can obtain indium metal (i.e. In), because indium metal is lighttight, therefore effectively can block the light of directive active layer 1.
And light shield layer directly generates from public electrode 6, without the need to forming Rotating fields separately for forming light shield layer 2, simplify the technique making light shield layer 2.
As shown in Figure 4, preferably, also comprise:
First passivation layer 3, is arranged on active layer 1;
Resin bed 4, is arranged on the first passivation layer 3;
Public electrode 6, is arranged on resin bed 4, and material is metal oxide;
Second passivation layer 7, is arranged on public electrode 6;
Pixel electrode 5, is arranged on the second passivation layer 7,
Wherein, light shield layer 2 comprises:
First light shield layer 21, is positioned at same layer with public electrode 6, is formed by the metal oxide back in public electrode 6,
Second light shield layer 22, is positioned at same layer with pixel electrode 5, is formed by the metal oxide back in pixel electrode 5.
Light shield layer 2 in the present embodiment comprises two-layer light-shielding structure, relative to one deck light-shielding structure, more effectively can block the light of directive active layer 1.And the width of two-layer light shield layer can be adjusted as required, the width of two-layer light shield layer is set to identical or different.
And the first light shield layer 21 is directly formed by the metal oxide back in public electrode 6, second light shield layer 22 is directly formed by the metal oxide back in pixel electrode 5, form extra layer without the need to micro-first light shield layer 21 or the second light shield layer 22 again, simplify the technique making light shield layer.
Display base plate in the present embodiment can be the display base plate of ADS or IPS pattern, and wherein public electrode 6 and pixel electrode 5 are all arranged on array base palte.
Preferably, thin-film transistor also comprises:
Source electrode 8 and drain electrode 9, be arranged on active layer 1,
Wherein, the subregion of active layer 1 is blocked in source electrode 8 and drain electrode 9 respectively, then the area of light shield layer 2 is greater than active layer 1 not by the area of source electrode 8 with drain electrode 9 occlusion areas.Thus ensure that light shield layer 2 well can block the light of directive active layer 1.
Preferably, metal oxide is ITO, and the material of light shield layer is indium metal.
The invention allows for a kind of display unit, comprise the display base plate of above-mentioned any one.
It should be noted that, the display unit in the present embodiment can be: any product or parts with Presentation Function such as Electronic Paper, mobile phone, panel computer, television set, notebook computer, DPF, navigator.
As shown in Figure 5, display base plate manufacture method according to an embodiment of the invention, comprising:
Form the active layer 1 in thin-film transistor;
Light shield layer 2 is formed, to block the light of directive active layer 1 on active layer 1.
Preferably, also comprise:
The first passivation layer 3 is formed on active layer 1;
Resin bed 4 is formed on the first passivation layer 3;
The pixel electrode 5 that material is metal oxide is formed on resin bed 4,
Then form light shield layer 2 to comprise:
Reduction treatment is carried out to the first area of pixel electrode 5, using as light shield layer 2.
As shown in Figure 5, preferably, form light shield layer 2 to comprise:
A1, forms intermediate tone mask on the first area of pixel electrode 5, on other regions of pixel electrode 5, form panchromatic tune mask;
A2, etches pixel electrode 5 place layer, to obtain the pattern of pixel electrode 5;
A3, carries out cineration technics to the pattern of pixel electrode 5, with the intermediate tone mask on the first area of removing pixel electrode 5;
A4, carries out plasma reduction process to the first area of pixel electrode 5, using as light shield layer 2.
Preferably, also comprise:
The first passivation layer 3 is formed on active layer 1;
Resin bed 4 is formed on the first passivation layer 3;
The public electrode 6 that material is metal oxide is formed on resin bed 4,
Then form light shield layer 2 to comprise:
Reduction treatment is carried out to the second area of public electrode 6, using as light shield layer 2.
As shown in Figure 6, preferably, form light shield layer to comprise:
B1, forms intermediate tone mask 11 on the second area of public electrode 6, forms panchromatic tune mask 12, as shown in Figure 8 on other regions of public electrode 6;
B2, etches public electrode 6 place layer, to obtain the pattern of public electrode 6, as shown in Figure 9;
B3, carries out cineration technics to the pattern of public electrode 6, with the intermediate tone mask 11 on the second area removing public electrode 6, as shown in Figure 10;
B4, carries out plasma reduction process to the second area of public electrode 6, using as light shield layer 2, as shown in figure 11, certainly, also needs to remove the panchromatic tune mask 12 on other regions of public electrode 6, as shown in figure 12 after forming light shield layer 2.
Preferably, also comprise:
The first passivation layer 3 is formed on active layer 1;
Resin bed 4 is formed on the first passivation layer 3;
The public electrode 6 that material is metal oxide is formed on resin bed 4;
The second passivation layer 7 is formed on public electrode 6;
The pixel electrode 5 that material is metal oxide is formed on the second passivation layer 7,
Then form light shield layer 2 to comprise: form the first light shield layer 21 and the second light shield layer 22,
Wherein, form the first light shield layer 21 to comprise:
Reduction treatment is carried out to the second area of public electrode 6, using as the first light shield layer 21,
Form the second light shield layer to comprise:
Reduction treatment is carried out to the first area of pixel electrode 5, using as the second light shield layer 22.
As shown in Figure 8, preferably, form the first light shield layer 21 to comprise:
C1, forms intermediate tone mask on the second area of public electrode 6, on other regions of public electrode 6, form panchromatic tune mask;
C2, etches public electrode 6 place layer, to obtain the pattern of public electrode;
C3, carries out cineration technics to the pattern of public electrode 6, with the intermediate tone mask on the second area removing public electrode 6;
C4, carries out plasma reduction process to the second area of public electrode 6, using as the first light shield layer 21,
Form the second light shield layer 22 to comprise:
C5, forms intermediate tone mask on the first area of pixel electrode 5, on other regions of pixel electrode 5, form panchromatic tune mask;
C6, etches pixel electrode 5 place layer, to obtain the pattern of pixel electrode 5;
C7, carries out cineration technics to the pattern of pixel electrode 5, with the intermediate tone mask on the first area of removing pixel electrode 5;
C8, carries out plasma reduction process to the first area of pixel electrode 5, using as the second light shield layer 22.
Above-mentioned plasma treatment comprises passes through SiH
4plasma treatment is carried out, due to ITO and SiH in (i.e. silane) surface to pixel electrode 5 and/or public electrode 6
4reaction can form the indium metal condensing into block, and the transmitance of indium metal is very low, can block the light of directive active layer 1.And plasma treatment can ensure only to form layer of metal indium film, and blocked up metal level can not be formed, ensure that display base plate thickness is lower.
Preferably, the SiH of 800sccm is greater than by flow
4carry out reduction treatment.
Flow is greater than the SiH of 800sccm
4can ensure that the indium metal restored from ITO condenses into fine and close structure, not easily printing opacity, to ensure the light blocking directive active layer 1 completely.
Wherein, the formation process that above-mentioned flow process adopts such as can comprise: the patterning processes such as film-forming process and etching such as deposition, sputtering.
More than be described with reference to the accompanying drawings technical scheme of the present invention, considered in prior art, the active layer of thin-film transistor is easily subject to extraneous illumination effect and causes thin-film transistor performance bad.According to technical scheme of the present invention, by arranging light shield layer in active layer, can effectively avoid extraneous light to be irradiated to active layer in thin-film transistor, thus thin-film transistor performance that extraneous illumination effect causes is unstable to avoid active layer to be subject to.
It is pointed out that in the accompanying drawings, in order to the illustrated clear size that may be exaggerated layer and region.And be appreciated that when element or layer be called as another element or layer " on " time, directly on other elements, or can there is middle layer in it.In addition, being appreciated that when element or layer are called as at another element or layer D score, directly under other elements, or can there is layer or the element of more than one centre in it.In addition, be further appreciated that when layer or element be called as two-layer or two elements " between " time, it can be two-layer or layer only between two elements, maybe can also there is more than one intermediate layer or element.Reference marker similar in the whole text indicates similar element.
In the present invention, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance.Term " multiple " refers to two or more, unless otherwise clear and definite restriction.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (15)
1. a display base plate, is characterized in that, comprising:
Thin-film transistor, is provided with active layer in described thin-film transistor;
Light shield layer, is arranged on described active layer, for blocking the light of active layer described in directive.
2. display base plate according to claim 1, is characterized in that, also comprises:
First passivation layer, is arranged on described active layer;
Resin bed, is arranged on described first passivation layer;
Pixel electrode, is arranged on described resin bed, and material is metal oxide,
Wherein, described light shield layer and described pixel electrode are positioned at same layer, are formed by the metal oxide back in described pixel electrode.
3. display base plate according to claim 1, is characterized in that, also comprises:
First passivation layer, is arranged on described active layer;
Resin bed, is arranged on described first passivation layer;
Public electrode, is arranged on described resin bed, and material is metal oxide,
Wherein, described light shield layer and described public electrode are positioned at same layer, are formed by the metal oxide back in described public electrode.
4. display base plate according to claim 1, is characterized in that, also comprises:
First passivation layer, is arranged on described active layer;
Resin bed, is arranged on described first passivation layer;
Public electrode, is arranged on described resin bed, and material is metal oxide;
Second passivation layer, is arranged on described public electrode;
Pixel electrode, is arranged on described second passivation layer,
Wherein, described light shield layer comprises:
First light shield layer, is positioned at same layer with described public electrode, is formed by the metal oxide back in described public electrode,
Second light shield layer, is positioned at same layer with described pixel electrode, is formed by the metal oxide back in described pixel electrode.
5. display base plate according to any one of claim 1 to 4, is characterized in that, described thin-film transistor also comprises:
Source electrode and drain electrode, be arranged on described active layer,
Wherein, the subregion of described active layer is blocked in described source electrode and drain electrode respectively, then the area of described light shield layer is greater than described active layer not by the area of described source electrode with drain electrode occlusion area.
6. the display base plate according to any one of claim 2 to 4, is characterized in that, described metal oxide is ITO, and the material of described light shield layer is indium metal.
7. a display unit, is characterized in that, comprises the display base plate according to any one of claim 1 to 6.
8. a display base plate manufacture method, is characterized in that, comprising:
Form the active layer in thin-film transistor;
Light shield layer is formed, to block the light of active layer described in directive in active layer.
9. display base plate manufacture method according to claim 8, is characterized in that, also comprise:
The first passivation layer is formed in described active layer;
Resin bed is formed on described first passivation layer;
The pixel electrode that material is metal oxide is formed on described resin bed,
Then form described light shield layer to comprise:
Reduction treatment is carried out to the first area of described pixel electrode, using as described light shield layer.
10. display base plate manufacture method according to claim 9, is characterized in that, forms described light shield layer and comprises:
On the first area of described pixel electrode, form intermediate tone mask, on other regions of described pixel electrode, form panchromatic tune mask;
Described pixel electrode place layer is etched, to obtain the pattern of described pixel electrode;
Cineration technics is carried out to the pattern of described pixel electrode, with the intermediate tone mask on the first area of removing described pixel electrode;
Plasma reduction process is carried out to the first area of described pixel electrode, using as described light shield layer.
11. display base plate manufacture methods according to claim 8, is characterized in that, also comprise:
The first passivation layer is formed in described active layer;
Resin bed is formed on described first passivation layer;
The public electrode that material is metal oxide is formed on described resin bed,
Then form described light shield layer to comprise:
Reduction treatment is carried out to the second area of described public electrode, using as described light shield layer.
12. display base plate manufacture methods according to claim 11, is characterized in that, form described light shield layer and comprise:
On the second area of described public electrode, form intermediate tone mask, on other regions of described public electrode, form panchromatic tune mask;
Described public electrode place layer is etched, to obtain the pattern of described public electrode;
Cineration technics is carried out to the pattern of described public electrode, with the intermediate tone mask on the second area removing described public electrode;
Plasma reduction process is carried out to the second area of described public electrode, using as described light shield layer.
13. display base plate manufacture methods according to claim 8, is characterized in that, also comprise:
The first passivation layer is formed in described active layer;
Resin bed is formed on described first passivation layer;
The public electrode that material is metal oxide is formed on described resin bed;
The second passivation layer is formed on described public electrode;
The pixel electrode that material is metal oxide is formed on described second passivation layer,
Then form described light shield layer to comprise: form the first light shield layer and the second light shield layer,
Wherein, form described first light shield layer to comprise:
Reduction treatment is carried out to the second area of described public electrode, using as described first light shield layer,
Form described second light shield layer to comprise:
Reduction treatment is carried out to the first area of described pixel electrode, using as described second light shield layer.
14. display base plate manufacture methods according to claim 13, is characterized in that, form described first light shield layer and comprise:
On the second area of described public electrode, form intermediate tone mask, on other regions of described public electrode, form panchromatic tune mask;
Described public electrode place layer is etched, to obtain the pattern of described public electrode;
Cineration technics is carried out to the pattern of described public electrode, with the intermediate tone mask on the second area removing described public electrode;
Plasma reduction process is carried out to the second area of described public electrode, using as described first light shield layer,
Form described second light shield layer to comprise:
On the first area of described pixel electrode, form intermediate tone mask, on other regions of described pixel electrode, form panchromatic tune mask;
Described pixel electrode place layer is etched, to obtain the pattern of described pixel electrode;
Cineration technics is carried out to the pattern of described pixel electrode, with the intermediate tone mask on the first area of removing described pixel electrode;
Plasma reduction process is carried out to the first area of described pixel electrode, using as described second light shield layer.
15. display base plate manufacture methods according to any one of claim 9 to 14, be is characterized in that, be greater than the SiH of 800sccm by flow
4carry out reduction treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510420098.0A CN104934449B (en) | 2015-07-16 | 2015-07-16 | Display base plate and preparation method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510420098.0A CN104934449B (en) | 2015-07-16 | 2015-07-16 | Display base plate and preparation method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104934449A true CN104934449A (en) | 2015-09-23 |
| CN104934449B CN104934449B (en) | 2017-12-05 |
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| CN105514120A (en) * | 2016-01-21 | 2016-04-20 | 京东方科技集团股份有限公司 | Dual-gate TFT array substrate, manufacturing method thereof and display device |
| CN105629544A (en) * | 2016-01-14 | 2016-06-01 | 京东方科技集团股份有限公司 | Display base plate and manufacturing method of display base plate as well as display panel and display device |
| CN109757118A (en) * | 2017-09-04 | 2019-05-14 | 京东方科技集团股份有限公司 | Display substrates and display devices |
| WO2020024292A1 (en) * | 2018-08-03 | 2020-02-06 | 深圳市柔宇科技有限公司 | Array substrate and display device |
| CN113985667A (en) * | 2021-10-12 | 2022-01-28 | Tcl华星光电技术有限公司 | Array substrate, preparation method thereof and liquid crystal display panel |
| CN114137771A (en) * | 2021-12-08 | 2022-03-04 | Tcl华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| WO2024065358A1 (en) * | 2022-09-29 | 2024-04-04 | 京东方科技集团股份有限公司 | Array substrate, and display panel comprising same and preparation method therefor |
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| CN105629544A (en) * | 2016-01-14 | 2016-06-01 | 京东方科技集团股份有限公司 | Display base plate and manufacturing method of display base plate as well as display panel and display device |
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| CN114137771A (en) * | 2021-12-08 | 2022-03-04 | Tcl华星光电技术有限公司 | Array substrate and manufacturing method thereof |
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| WO2024065358A1 (en) * | 2022-09-29 | 2024-04-04 | 京东方科技集团股份有限公司 | Array substrate, and display panel comprising same and preparation method therefor |
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