CN104917498B - A kind of three mould clock generation circuits based on difference - Google Patents
A kind of three mould clock generation circuits based on difference Download PDFInfo
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- CN104917498B CN104917498B CN201510309684.8A CN201510309684A CN104917498B CN 104917498 B CN104917498 B CN 104917498B CN 201510309684 A CN201510309684 A CN 201510309684A CN 104917498 B CN104917498 B CN 104917498B
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Abstract
The present invention is a kind of can to configure the three mould clocks for producing different differences, and when occurring SET and SEU Single Point of Faliures, effectively can carry out the fault-tolerant three mould clock generation circuits based on difference to Single Point of Faliure；It includes the three road clock selection circuits that input connects clock clk respectively, and the phase difference that three road clock selection circuits export three mould clock clk1, clk2 and clk3, wherein clk2 and the clk1 of out of phase respectively is identical with clk3 and clk2 phase difference；Clock selection circuit includes selector, clock generation logic circuit and fault tolerable circuit；The selection end connection difference selection signal delaysel of selector, the input connection clock of fault tolerable circuit produces control signal ctrl, the input of clock generation logic circuit connects the output end of selector and the output end of fault tolerable circuit respectively, and the output end of clock generation logic circuit exports corresponding three mould clock all the way.
Description
Technical field
The present invention relates to hardware circuit design field, specially a kind of three mould clock generation circuits based on difference.
Background technology
Based on space flight reliability requirement, prevent single-ion transient state (SET) mistake and single-particle inversion (SEU) from causing mistake to be grasped
Make, chip design is using based on clock difference triplication redundancy register architecture design, but during existing three mould based on difference
The problem of clock generation circuit all has following, it is impossible to require different application environments according to Flouride-resistani acid phesphatase, enter to clock phase difference
Row configuration, makes system application narrower；SET or SEU Single Point of Faliure are there may be in clock generation circuit, when generation single-point
During failure, three mould clocks can make a mistake, and will result directly in system operation mistake.So as to cause three moulds clock of the prior art
The poor reliability of generation circuit, versatility is weaker.
The content of the invention
For problems of the prior art, the present invention provides a kind of when can configure three mould for producing different differences
Clock, and when occurring SET and SEU Single Point of Faliures, the fault-tolerant three mould clocks based on difference effectively can be carried out to Single Point of Faliure and produced
Raw circuit.
The present invention is to be achieved through the following technical solutions：
A kind of three mould clock generation circuits based on difference, including input connect clock clk three road clock choosings respectively
Select circuit, three road clock selection circuits export three mould clock clk1, clk2 and clk3 of out of phase respectively, wherein clk2 and
Clk1 phase difference is identical with clk3 and clk2 phase difference；
Clock selection circuit includes selector, clock generation logic circuit and fault tolerable circuit；The selection end connection of selector
Selection signal delaysel is differed, the input connection clock of fault tolerable circuit produces control signal ctrl, clock generation logic electricity
The input on road connects the output end of selector and the output end of fault tolerable circuit respectively, and the output end of clock generation logic circuit is defeated
Go out corresponding three mould clock all the way；
When the low-level input and high level input of selector mux1 in first via clock selection circuit are all connected with
Clock clk；
The low-level input of selector mux2 in second road clock selection circuit passes through delay unit D0 connection clocks
Clk, high level input passes through delay unit D1 connection clocks clk；
The low-level input of selector mux3 in 3rd road clock selection circuit by the delay unit D2 of series connection and
Delay unit D3 connection clock clk, delay unit D4 and delay unit D5 the connection clock that high level input passes through series connection
clk。
It is preferred that, delay unit D0, D2 and D3 delay length are equal, delay unit D1, D4 and D5 delay length phase
Deng.
It is preferred that, fault tolerable circuit includes delay unit and and/or door；And/or the input connection clock of door is produced
Control signal ctrl, another input is defeated through delay unit connection clock generation control signal ctrl, and/or the output end of door
Go out corresponding fault-tolerant processing signal.
Further, when it is that low level is effective that clock, which produces control signal ctrl, fault tolerable circuit include delay unit and/or
Door, the output end output low level fault-tolerant processing signal ctrl_low of OR gate.
Further, when it is effective for high level that clock, which produces control signal ctrl, fault tolerable circuit includes delay unit
With with door, with the output end of door output high level fault-tolerant processing signal ctrl_high.Compared with prior art, the present invention has
Beneficial technique effect below：
The three mould clock generation circuits of the invention based on difference, by differing selection signal delaysel to clock phase difference
Different application environments can be applied to by carrying out configuration, while can effectively prevent production by the setting of three road clock selection circuits
The raw three mould clocks based on difference are due to system mistake caused by SET and SEU phenomenons, when three mould clocks have a clock road hair
During raw Single Point of Faliure, on system without influence, the normal operation of system is can effectively ensure that, strengthens chip Radiation hardness, versatility
By force.
Further, by the control to delay unit delay length, it disclosure satisfy that wanting for three mould clock outs of phase difference
Ask.
Further, fault-tolerant processing is carried out to low level or high level by fault tolerable circuit, when SET or SEU occurs for ctrl
Single Point of Faliure when, still ensure that the correctness of two clocks in three mould clocks, due to use triplication redundancy register design, can
To ensure the normal operation of system.
Brief description of the drawings
Fig. 1 is the circuit diagram of the three mould clock generation circuits based on difference described in present example.
Fig. 2 is the fault tolerable circuit of the low level efficient clock generation control signal described in present example.
Fig. 3 is the fault tolerable circuit of the high level efficient clock generation control signal described in present example.
Embodiment
With reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
The three mould clock generation circuits of the invention based on difference, as shown in figure 1, its input clock is clk, during three mould of output
Clock is respectively clk1, clk2 and clk3, and D0-D5 is the delay unit based on difference, according to difference selection signal delaysel choosings
Select different phase differences.When delaysel is 0, difference is D0 between clk1 and clk2, and difference is D2+ between clk1 and clk2
D3, wherein D2=D3=D0；When delaysel is 1, difference is D1 between clk1 and clk2, and difference is between clk1 and clk2
D4+D5, wherein D4=D5=D1.The delay of difference is set according to concrete application, it can also be provided that 0；Delaysel digit
It can also be increased according to concrete application, to select a variety of differences, it is adaptable to different application environments.When in space flight
Or Flouride-resistani acid phesphatase is required under high environment in use, from big clock phase difference, prevent SET phenomenons from causing systemic breakdown, to increase
Strong chip Radiation hardness；When requiring on ground or to Flouride-resistani acid phesphatase under low environment in use, from small clock phase difference, having
The running frequency of increase system is imitated, performance is improved.
The three mould clocks that the MUX alternatively held by delaysel is produced be respectively clk1_t, clk2_t and
clk3_t.No matter delaysel is 0 or 1, all selects clk for clk1_t, clk1_t generation herein still uses multichannel
Selector circuit, it is ensured that clk1_t and clk2_t and clk3_t clock phases uniformity.Wherein, clk1_t, clk2_t and
Clk3_t through oversampling clock 1 produce logic circuit, clock 2 produce logic circuit and clock 3 produce logic circuit produce respectively clk1,
Clk2 and clk3.The clock that clock 1/2/3 produces logic produces control signal ctrl as Single Point of Faliure respectively through fault tolerable circuit
1/2/3 it is fault-tolerant after be re-used as clock 1/2/3 produce logic circuit input.
As clock is produced, control signal ctrl is low effectively, and fault tolerable circuit carries out fault-tolerant processing to low level；As clock is produced
Control signal ctrl is high effectively, and fault tolerable circuit carries out fault-tolerant processing to high level.When SET or SEU Single Point of Faliure occurs for ctrl
When, the correctness of two clocks in three mould clocks is still ensured that, due to using triplication redundancy register design, system is ensure that
Normal operation.
Three mould clock clk1, clk2 and clk3 generation is using three sets of circuit realirations in the present invention, when D0, D1, D2, D3,
D4, D5, mux1, mux2, mux3, fault tolerable circuit 1/2/3, clock 1/2/3 produce some in logic circuit and occur SET or SEU
Single Point of Faliure when, still ensure that the correctness of two clocks in three mould clocks, due to use triplication redundancy register design, can
To ensure the normal operation of system.
The present invention operationally, as shown in figure 1, difference selection signal delaysel connection selectors mux1/2/3 selection
End, clock clk connections mux1 0 end and 1 end connect D0, D1, D2, D4 input.D0 output connection mux2 0 end, D1's
Output connection mux2 1 end, D2 output clkd0 connections D3 input, D3 output connection mux3 0 end, D4 output
Clkd1 connections D5 input, D5 output connection mux3 1 end.Mux1 output clk1_t connections clock 1 produces the defeated of logic
Enter, mux2 output clk2_t connections clock 2 produces the input of logic, mux3 output clk3_t connections clock 3 produces logic
Input.Clock produces control signal ctrl connection fault tolerants circuit 1, fault tolerable circuit 2, the input of fault tolerable circuit 3, fault tolerable circuit 1
Export fault-tolerant processing signal ctrl1, the output fault-tolerant processing signal ctrl2 of fault tolerable circuit 2, the output fault-tolerant processing letter of fault tolerable circuit 3
Number ctrl3.Ctrl1 connections clock 1 produces the input of logic circuit, and ctrl2 connections clock 2 produces the input circuit of logic,
Ctrl3 connections clock 3 produces the input circuit of logic.Clock 1 produces logic circuit output clk1, and clock 2 produces logic circuit
Clk2 is exported, clock 3 produces logic circuit output clk3.
As shown in Fig. 2 control signal ctrl fault tolerable circuit is produced for the effective clock of low level, ctrl connections delay
The input of unit 1, the first input of the output ctrl_d1 connection OR gates of delay unit 1, the second input of ctrl connection OR gates,
OR gate exports ctrl_low.
As shown in figure 3, control signal ctrl fault tolerable circuit is produced for the effective clock of high level, ctrl connections delay
The input of unit 2, the output ctrl_d2 connections of delay unit 2 and the first input of door, ctrl connections and the second input of door,
Ctrl_high is exported with door.
Apply the present invention in a SoC that the design of triplication redundancy register architecture is differed based on clock, the SoC is used
Reliable three mould clock generation circuits based on difference in the present invention, make that SoC anti-single particle effects are stronger, and anti-single particle is turned over
Turn probability≤1E-11Error/Bit/Day (under 90% the worst GEO rail conditions), reliable and stable, performance efficiency.
Claims (5)
1. a kind of three mould clock generation circuits based on difference, it is characterised in that connect the three of clock clk respectively including input
Road clock selection circuit, three road clock selection circuits export three mould clock clk1, clk2 and clk3 of out of phase respectively, wherein
Clk2 and clk1 phase difference is identical with clk3 and clk2 phase difference；
Described clock selection circuit includes selector, clock generation logic circuit and fault tolerable circuit；The selection end of selector connects
Difference selection signal delaysel is met, the input connection clock of fault tolerable circuit produces control signal ctrl, clock generation logic
The input of circuit connects the output end of selector and the output end of fault tolerable circuit, the output end of clock generation logic circuit respectively
The corresponding three mould clock all the way of output；
The low-level input and high level input of selector mux1 in first via clock selection circuit is all connected with clock
clk；
The low-level input of selector mux2 in second road clock selection circuit by delay unit D0 connection clock clk,
High level input passes through delay unit D1 connection clocks clk；
The low-level input of selector mux3 in 3rd road clock selection circuit passes through the delay unit D2 of series connection and delay
Cells D 3 connects clock clk, delay unit D4 and delay unit D5 connection the clock clk that high level input passes through series connection.
2. a kind of three mould clock generation circuits based on difference according to claim 1, it is characterised in that delay unit
D0, D2 and D3 delay length are equal, and delay unit D1, D4 and D5 delay length are equal.
3. a kind of three mould clock generation circuits based on difference according to claim 1, it is characterised in that described is fault-tolerant
Circuit includes delay unit and and/or door；And/or the input connection clock of door produces control signal ctrl, another
Input produces control signal ctrl through delay unit connection clock, and/or the output end of door exports corresponding fault-tolerant processing letter
Number.
4. a kind of three mould clock generation circuits based on difference according to claim 3, it is characterised in that when clock is produced
When control signal ctrl is that low level is effective, fault tolerable circuit includes delay unit and OR gate, the output end output low level of OR gate
Fault-tolerant processing signal ctrl_low.
5. a kind of three mould clock generation circuits based on difference according to claim 3, it is characterised in that when clock is produced
Control signal ctrl be for high level it is effective when, fault tolerable circuit include delay unit and with door, export high with the output end of door
Level fault-tolerant processing signal ctrl_high.
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| CN201510309684.8A CN104917498B (en) | 2015-06-05 | 2015-06-05 | A kind of three mould clock generation circuits based on difference |
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|---|---|---|---|
| CN201510309684.8A CN104917498B (en) | 2015-06-05 | 2015-06-05 | A kind of three mould clock generation circuits based on difference |
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| CN104917498A CN104917498A (en) | 2015-09-16 |
| CN104917498B true CN104917498B (en) | 2017-08-04 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106301352B (en) * | 2015-05-18 | 2019-08-09 | 复旦大学 | A design method of anti-radiation fault-tolerant circuit based on AND gate, OR gate and selector |
| CN111082797B (en) * | 2019-11-08 | 2021-11-12 | 大连理工大学 | Triple-modular redundancy anti-irradiation reinforced unit circuit with TMR-5 DFF structure and application thereof |
| CN113346880B (en) * | 2021-06-15 | 2023-07-11 | 西安微电子技术研究所 | System and method for generating time-adjustable triple-modular redundant clock based on clock calibration |
| CN118282372B (en) * | 2024-06-03 | 2024-08-09 | 上海泰矽微电子有限公司 | Multi-switch control circuit and chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5537583A (en) * | 1994-10-11 | 1996-07-16 | The Boeing Company | Method and apparatus for a fault tolerant clock with dynamic reconfiguration |
| US5977809A (en) * | 1997-11-12 | 1999-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Programmable non-overlap clock generator |
| CN101958713A (en) * | 2010-09-28 | 2011-01-26 | 中国人民解放军国防科学技术大学 | A SET-hardened differential voltage-controlled oscillator based on triple-mode redundancy technology |
| CN102820879A (en) * | 2012-08-17 | 2012-12-12 | 中国电子科技集团公司第五十八研究所 | Radiation-proof triple-modular redundancy circuit structure |
-
2015
- 2015-06-05 CN CN201510309684.8A patent/CN104917498B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5537583A (en) * | 1994-10-11 | 1996-07-16 | The Boeing Company | Method and apparatus for a fault tolerant clock with dynamic reconfiguration |
| US5977809A (en) * | 1997-11-12 | 1999-11-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Programmable non-overlap clock generator |
| CN101958713A (en) * | 2010-09-28 | 2011-01-26 | 中国人民解放军国防科学技术大学 | A SET-hardened differential voltage-controlled oscillator based on triple-mode redundancy technology |
| CN102820879A (en) * | 2012-08-17 | 2012-12-12 | 中国电子科技集团公司第五十八研究所 | Radiation-proof triple-modular redundancy circuit structure |
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