CN104849889A - Liquid crystal display panel and liquid crystal display device - Google Patents
Liquid crystal display panel and liquid crystal display device Download PDFInfo
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- CN104849889A CN104849889A CN201510240028.7A CN201510240028A CN104849889A CN 104849889 A CN104849889 A CN 104849889A CN 201510240028 A CN201510240028 A CN 201510240028A CN 104849889 A CN104849889 A CN 104849889A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 33
- 239000000872 buffer Substances 0.000 claims description 10
- 230000000694 effects Effects 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 239000010409 thin film Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention provides a liquid crystal display panel and a liquid crystal display device. The liquid crystal display panel comprises a data wire, a scanning wire, a pixel unit and a drive circuit; the drive circuit comprises a shifting register and a first NAND gate. The invention further provides a liquid crystal display device. The liquid crystal display panel and the liquid crystal display device effectively and exactly output the scanning signal through the first NAND gate, a secondary clock signal and a main clock signal; the drive circuit is simple in whole structure, low in manufacturing cost, and well realizes a narrow side frame of the liquid crystal display panel.
Description
Technical field
The present invention relates to display driver field, particularly relate to a kind of display panels and liquid crystal indicator.
Background technology
Along with the development of science and technology, use the user of liquid crystal indicator to get more and more, therefore the quality requirements of people to liquid crystal indicator is also more and more higher.
Liquid crystal indicator exports sweep signal and data-signal by the corresponding thin film transistor (TFT) that is turned on or off.But due to delay effect, thin film transistor (TFT) may be caused not to be turned on or off timely, the data-signal of the pixel cell of next line may be made like this to be input in the pixel cell of one's own profession, thus cause the display of picture abnormal.
In order to ensure the accuracy that data-signal exports, output enable signal (OE signal is added in the driving circuit of liquid crystal indicator, Output Enable signal), as shown in FIG. 1A and 1B, Figure 1A is the drive singal sequential chart of the driving circuit of existing liquid crystal indicator; Figure 1B is the concrete structure figure of the driving circuit of existing liquid crystal indicator; Wherein 11 is shift registers, and 12 is level displacement shifters, and 13 is digital buffers, and 14 is not gates, and 15 is first Sheffer stroke gates, and 16 is second Sheffer stroke gates, and CPV is clock signal, and G1 to G5 is sweep signal, and RESET is reset signal.When OE signal is high level, all sweep signals are low level; When OE signal is low level, corresponding sweep signal is high level, like this by the setting of OE signal, can ensure timely conducting and the disconnection of thin film transistor (TFT) preferably.
But the increase of OE signal, makes the pin number of driving circuit need to increase, and then causes the area of driving circuit and the raising of cost of manufacture, affect the narrow frame design of display panels.
Therefore, be necessary to provide a kind of display panels and liquid crystal indicator, to solve the problem existing for prior art.
Summary of the invention
The object of the present invention is to provide that a kind of structure is simple, cost of manufacture is lower and display panels and the liquid crystal indicator of the narrow frame design of display panels can be realized preferably, higher and the technical matters of narrow frame design cannot be realized preferably with the cost of manufacture solving existing display panels and liquid crystal indicator.
For solving the problem, technical scheme provided by the invention is as follows:
The embodiment of the present invention provides a kind of display panels, and it comprises:
Data line, for transmission of data signals;
Sweep trace, for transmitting sweep signal;
Pixel cell, is staggered to form by described data line and described sweep trace, for carrying out picture display according to described data-signal and described sweep signal;
Driving circuit, for exporting described data-signal and described sweep signal;
Wherein said driving circuit comprises:
Shift register, for exporting multiple clock informations according to master clock signal and start signal; And
First Sheffer stroke gate, for exporting multiple sweep signal according to multiple described clock signals and described master clock signal.
In display panels of the present invention, the time interval of described time adjacent clock signal is identical.
In display panels of the present invention, described driving circuit also comprises the second Sheffer stroke gate for carrying out reset processing to described sweep signal.
In display panels of the present invention, described driving circuit also comprises the level shifter for carrying out level conversion to described sweep signal.
In display panels of the present invention, described driving circuit also comprises the data buffer for carrying out storage operation to described sweep signal.
In display panels of the present invention, described shift register comprises multiple shifting deposit unit, each described shifting deposit unit comprise master clock signal input end for inputting described master clock signal, for input start signal start signal input end, for the clock signal output terminal of described shifting deposit unit output timing signal of next stage and the secondary clock signal output terminal for exporting described clock signal.
In display panels of the present invention, according to the effect duration of described sweep signal and the interval duration of adjacent described sweep signal, determine the dutycycle of described master clock signal.
The present invention also provides a kind of liquid crystal indicator, and it comprises backlight and display panels;
Wherein said display panels comprises:
Data line, for transmission of data signals;
Sweep trace, for transmitting sweep signal;
Pixel cell, is staggered to form by described data line and described sweep trace, for carrying out picture display according to described data-signal and described sweep signal;
Driving circuit, for exporting described data-signal and described sweep signal;
Wherein said driving circuit comprises:
Shift register, for exporting multiple clock informations according to master clock signal and start signal; And
First Sheffer stroke gate, for exporting multiple sweep signal according to multiple described clock signals and described master clock signal.
In liquid crystal indicator of the present invention, described driving circuit also comprises the second Sheffer stroke gate for carrying out reset processing to described sweep signal, for carrying out the level shifter of level conversion and the data buffer for carrying out storage operation to described sweep signal to described sweep signal.
In liquid crystal indicator of the present invention, described shift register comprises multiple shifting deposit unit, each described shifting deposit unit comprise master clock signal input end for inputting described master clock signal, for input start signal start signal input end, for the clock signal output terminal of described shifting deposit unit output timing signal of next stage and the secondary clock signal output terminal for exporting described clock signal;
According to the effect duration of described sweep signal and the interval duration of adjacent described sweep signal, determine the dutycycle of described master clock signal.
Compared to existing display panels and liquid crystal indicator, display panels of the present invention and liquid crystal indicator achieve effectively accurately exporting of sweep signal by the first Sheffer stroke gate, secondary clock signal and master clock signal, and the total of driving circuit is simple, cost of manufacture is lower and well can realize the narrow frame design of display panels; Solve the cost of manufacture of existing display panels and liquid crystal indicator higher and the technical matters of narrow frame design cannot be realized preferably.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below:
Accompanying drawing explanation
Figure 1A is the drive singal sequential chart of the driving circuit of existing display panels;
Figure 1B is the concrete structure schematic diagram of the driving circuit of existing display panels;
Fig. 2 A is the concrete structure schematic diagram of the driving circuit of the preferred embodiment of display panels of the present invention;
Fig. 2 B is the drive singal sequential chart of the driving circuit of the preferred embodiment of display panels of the present invention.
Embodiment
The explanation of following embodiment is graphic with reference to what add, can in order to the specific embodiment implemented in order to illustrate the present invention.The direction term that the present invention mentions, such as " on ", D score, "front", "rear", "left", "right", " interior ", " outward ", " side " etc., be only the direction with reference to annexed drawings.Therefore, the direction term of use is in order to illustrate and to understand the present invention, and is not used to limit the present invention.
In the drawings, the unit that structure is similar represents with identical label.
Please refer to the concrete structure schematic diagram that Fig. 2 A and Fig. 2 B, Fig. 2 A is the driving circuit of the preferred embodiment of display panels of the present invention; Fig. 2 B is the drive singal sequential chart of the driving circuit of the preferred embodiment of display panels of the present invention.The display panels of this preferred embodiment comprises data line (not shown), sweep trace (not shown), pixel cell (not shown) and driving circuit 20.Data line is used for transmission of data signals, and sweep trace is for transmitting sweep signal, and pixel cell is staggered to form by data line and sweep trace, and for carrying out picture display according to data-signal and sweep signal, driving circuit 20 is for outputting data signals and sweep signal.
This driving circuit 20 comprises shift register 21, first Sheffer stroke gate 22, second Sheffer stroke gate 23, level shifter 24 and data buffer 25.Shift register 21 is for exporting multiple clock signals according to master clock signal CPV and start signal STV; First Sheffer stroke gate 22 is for exporting multiple sweep signal, if sweep signal G1 is to sweep signal G5 according to multiple clock signals and master clock signal CPV; Second Sheffer stroke gate 23 is for carrying out reset processing to sweep signal; Level shifter 24 is for carrying out level conversion to sweep signal; Data buffer 25 is for carrying out storage operation to sweep signal.
Wherein shift register 21 comprises multiple shifting deposit unit 211, and each shifting deposit unit 211 comprises master clock signal input end A, start signal input end B, clock signal output terminal C and secondary clock signal output terminal D.Master clock signal input end A is for inputting master clock signal CPV, start signal input end B is for inputting start signal STV, clock signal output terminal C is used for the shifting deposit unit 211 output timing signal to next stage, and secondary clock signal output terminal D is for exporting time clock signal.
When the driving circuit 20 of this preferred embodiment uses, first master clock signal CPV is inputed to the master clock signal input end A of each shifting deposit unit 211 in shift register 21, start signal STV is input to the start signal input end B of each shifting deposit unit 211.
The secondary clock signal output terminal D of shifting deposit unit 211 of every grade exports corresponding time clock signal subsequently, and the clock signal output terminal C of shifting deposit unit 211 is to the shifting deposit unit 211 output timing signal of next stage.
Then the secondary clock signal of every one-level is input to the first input end of the first Sheffer stroke gate 22, master clock signal CPV is input to the second input end of the first Sheffer stroke gate 22, first Sheffer stroke gate 22 exports corresponding sweep signal, if sweep signal G1 is to sweep signal G5 according to secondary clock signal and master clock signal CPV subsequently.Because master clock signal CPV is only high level when corresponding first Sheffer stroke gate 22 exports the sweep signal of high level, therefore the output of the sweep signal of high level is controlled by master clock signal CPV, avoid thin film transistor (TFT) Delayed conducting or disconnection, here master clock signal CPV can play the effect identical with the OE signal in background technology.For the ease of designing the dutycycle of master clock signal CPV, the time interval of adjacent secondary clock signal is identical, the time interval of sweep signal (as sweep signal G1 and sweep signal G2) adjacent is like this also identical, like this by the dutycycle of the effect duration of sweep signal and the interval duration determination master clock signal CPV of adjacent sweep signal.
When master clock signal CPV and time clock signal are high level, the sweep signal of the first Sheffer stroke gate 22 output low level, in other situations, the first Sheffer stroke gate 22 exports the sweep signal of high level.
The sweep signal that first Sheffer stroke gate 22 exports subsequently is input to the first input end of the second Sheffer stroke gate 23, reset signal RESET is input to the second input end of the second Sheffer stroke gate 23, and such second Sheffer stroke gate 23 carries out reset processing by reset signal RESET to sweep signal.As reset signal RESET is set to low level, the second then all Sheffer stroke gates 23 exports the sweep signal of high level signal, as reset signal RESET is set to high level, when then the sweep signal of the first input end input of the second Sheffer stroke gate 23 is low level, the second Sheffer stroke gate 23 exports the sweep signal of high level.
Then the sweep signal that the second Sheffer stroke gate 23 exports carries out level conversion by level shifter 24, so that drive the thin film transistor (TFT) of corresponding pixel cell.
The sweep signal that final data buffer 25 pairs of level shifters 24 export carries out storage operation, to be exported on corresponding pixel cell by sweep trace in time.
So namely, complete the driving process of the sweep signal of the driving circuit 20 of this preferred embodiment.
The driving circuit of the display panels of this preferred embodiment achieves effectively accurately exporting of sweep signal by the first Sheffer stroke gate, secondary clock signal and master clock signal, does not need to arrange independent output enable signal; And the total of driving circuit is simple, cost of manufacture is lower and well can realize the narrow frame design of display panels.
The present invention also provides a kind of liquid crystal indicator, and this liquid crystal indicator comprises backlight and display panels.This display panels comprises data line, sweep trace, pixel cell and driving circuit.Data line is used for transmission of data signals, and sweep trace is for transmitting sweep signal, and pixel cell is staggered to form by data line and sweep trace, and for carrying out picture display according to data-signal and sweep signal, driving circuit is used for outputting data signals and sweep signal.
This driving circuit comprises shift register, the first Sheffer stroke gate, the second Sheffer stroke gate, level shifter and data buffer.Shift register is used for exporting multiple clock signals according to master clock signal and its real signal; First Sheffer stroke gate is used for exporting multiple sweep signal according to multiple clock signals and master clock signal; Second Sheffer stroke gate is used for carrying out reset processing to sweep signal; Level shifter is used for carrying out level conversion to sweep signal; Data buffer is used for carrying out storage operation to sweep signal.
Wherein shift register comprises multiple shifting deposit unit, and each shifting deposit unit comprises master clock signal input end, start signal input end, clock signal output terminal and secondary clock signal output terminal.Master clock signal input end is for inputting master clock signal, and start signal input end is for inputting start signal, and clock signal output terminal is used for the shifting deposit unit output timing signal to next stage, and secondary clock signal output terminal is for exporting time clock signal.
Preferably, the time interval of adjacent secondary clock signal is identical.
Preferably, according to the effect duration of sweep signal and the interval duration of adjacent sweep signal, the dutycycle of master clock signal is determined.
Display panels of the present invention and liquid crystal indicator achieve effectively accurately exporting of sweep signal by the first Sheffer stroke gate, secondary clock signal and master clock signal, and the total of driving circuit is simple, cost of manufacture is lower and well can realize the narrow frame design of display panels; Solve the cost of manufacture of existing display panels and liquid crystal indicator higher and the technical matters of narrow frame design cannot be realized preferably.
In sum; although the present invention discloses as above with preferred embodiment; but above preferred embodiment is also not used to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; all can do various change and retouching, the scope that therefore protection scope of the present invention defines with claim is as the criterion.
Claims (10)
1. a display panels, is characterized in that, comprising:
Data line, for transmission of data signals;
Sweep trace, for transmitting sweep signal;
Pixel cell, is staggered to form by described data line and described sweep trace, for carrying out picture display according to described data-signal and described sweep signal; And
Driving circuit, for exporting described data-signal and described sweep signal;
Wherein said driving circuit comprises:
Shift register, for exporting multiple clock informations according to master clock signal and start signal; And
First Sheffer stroke gate, for exporting multiple sweep signal according to multiple described clock signals and described master clock signal.
2. display panels according to claim 1, is characterized in that, the time interval of described time adjacent clock signal is identical.
3. display panels according to claim 1, is characterized in that, described driving circuit also comprises the second Sheffer stroke gate for carrying out reset processing to described sweep signal.
4. display panels according to claim 1, is characterized in that, described driving circuit also comprises the level shifter for carrying out level conversion to described sweep signal.
5. display panels according to claim 1, is characterized in that, described driving circuit also comprises the data buffer for carrying out storage operation to described sweep signal.
6. display panels according to claim 1, it is characterized in that, described shift register comprises multiple shifting deposit unit, each described shifting deposit unit comprise master clock signal input end for inputting described master clock signal, for input start signal start signal input end, for the clock signal output terminal of described shifting deposit unit output timing signal of next stage and the secondary clock signal output terminal for exporting described clock signal.
7. display panels according to claim 6, is characterized in that, according to the effect duration of described sweep signal and the interval duration of adjacent described sweep signal, determines the dutycycle of described master clock signal.
8. a liquid crystal indicator, is characterized in that, comprises backlight and display panels;
Wherein said display panels comprises:
Data line, for transmission of data signals;
Sweep trace, for transmitting sweep signal;
Pixel cell, is staggered to form by described data line and described sweep trace, for carrying out picture display according to described data-signal and described sweep signal;
Driving circuit, for exporting described data-signal and described sweep signal;
Wherein said driving circuit comprises:
Shift register, for exporting multiple clock informations according to master clock signal and start signal; And
First Sheffer stroke gate, for exporting multiple sweep signal according to multiple described clock signals and described master clock signal.
9. liquid crystal indicator according to claim 8, it is characterized in that, described driving circuit also comprises the second Sheffer stroke gate for carrying out reset processing to described sweep signal, for carrying out the level shifter of level conversion and the data buffer for carrying out storage operation to described sweep signal to described sweep signal.
10. liquid crystal indicator according to claim 8, it is characterized in that, described shift register comprises multiple shifting deposit unit, each described shifting deposit unit comprise master clock signal input end for inputting described master clock signal, for input start signal start signal input end, for the clock signal output terminal of described shifting deposit unit output timing signal of next stage and the secondary clock signal output terminal for exporting described clock signal;
According to the effect duration of described sweep signal and the interval duration of adjacent described sweep signal, determine the dutycycle of described master clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510240028.7A CN104849889B (en) | 2015-05-12 | 2015-05-12 | Liquid crystal display panel and liquid crystal display device |
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| CN201510240028.7A CN104849889B (en) | 2015-05-12 | 2015-05-12 | Liquid crystal display panel and liquid crystal display device |
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| CN104849889B CN104849889B (en) | 2018-05-18 |
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| WO2024113336A1 (en) * | 2022-12-02 | 2024-06-06 | 上海显耀显示科技有限公司 | Driving circuit, method and system for micro-led pixels |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN104849889B (en) | 2018-05-18 |
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